BibSLEIGH — Timing optimization of FPGA placements by logic replication

Giancarlo Beraudo, John Lillis
Timing optimization of FPGA placements by logic replication
DAC, 2003.

DAC 2003

@inproceedings{DAC-2003-BeraudoL,
	author        = "Giancarlo Beraudo and John Lillis",
	booktitle     = "{Proceedings of the 40th Design Automation Conference}",
	doi           = "10.1145/775832.775885",
	isbn          = "1-58113-688-9",
	pages         = "196--201",
	publisher     = "{ACM}",
	title         = "{Timing optimization of FPGA placements by logic replication}",
	year          = 2003,
}

Giancarlo Beraudo, John LillisTiming optimization of FPGA placements by logic replicationDAC, 2003.

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Giancarlo Beraudo, John Lillis
Timing optimization of FPGA placements by logic replication
DAC, 2003.