Travelled to:8 × USA
Collaborated with:C.Cheng M.Hrkic G.Beraudo S.Hur P.Buch A.Jagannathan J.Li L.Liu T.Y.Lin C.Ho
Talks about:placement (4) optim (3) rout (3) techniqu (2) approach (2) perform (2) cluster (2) replic (2) linear (2) insert (2)
Person: John Lillis
DBLP: Lillis:John
Contributed to:
20042003200220001999199819971996Wrote 9 papers:
- DAC-2004-HrkicLB #approach #logic #replication
- An approach to placement-coupled logic replication (MH, JL, GB), pp. 711–716.
- DAC-2003-BeraudoL #logic #optimisation #replication
- Timing optimization of FPGA placements by logic replication (GB, JL), pp. 196–201.
- DAC-2002-HrkicL #named #synthesis
- S-Tree: a technique for buffered routing tree synthesis (MH, JL), pp. 578–583.
- DAC-2000-JagannathanHL #algorithm #performance
- A fast algorithm for context-aware buffer insertion (AJ, SWH, JL), pp. 368–373.
- DAC-1999-HurL #clustering #framework #linear
- Relaxation and Clustering in a Local Search Framework: Application to Linear Placement (SWH, JL), pp. 360–366.
- DAC-1998-LillisB
- Table-Lookup Methods for Improved Performance-Driven Routing (JL, PB), pp. 368–373.
- DAC-1997-LillisC #multi #optimisation
- Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion (JL, CKC), pp. 214–219.
- DAC-1996-LiLLC #approach #clustering #linear
- New Spectral Linear Placement and Clustering Approach (JL, JL, LTL, CKC), pp. 88–93.
- DAC-1996-LillisCLH #performance #trade-off
- New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing (JL, CKC, TTYL, CYH), pp. 395–400.