BibSLEIGH — Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
DATE, 2005.

DATE 2005

@inproceedings{DATE-2005-KitaharaKMSF,
	author        = "Takeshi Kitahara and Naoyuki Kawabe and Fumihiro Minami and Katsuhiro Seta and Toshiyuki Furusawa",
	booktitle     = "{Proceedings of the Ninth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.2005.68",
	isbn          = "0-7695-2288-2",
	pages         = "646--647",
	publisher     = "{IEEE Computer Society}",
	title         = "{Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction}",
	year          = 2005,
}

Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki FurusawaArea-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power ReductionDATE, 2005.

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Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
DATE, 2005.