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Used together with:
power (52)
reduct (26)
inform (18)
gate (18)
awar (18)

Stem leakag$ (all stems)

134 papers:

DACDAC-2015-AgostaBPS #information management
Information leakage chaff: feeding red herrings to side channel attackers (GA, AB, GP, MS), p. 6.
DATEDATE-2015-LiXWNP #fine-grained #multi #power management #reduction #using
Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique (JL, QX, YW, SN, MP), pp. 1579–1582.
ICALPICALP-v1-2015-FaonioNV
Mind Your Coins: Fully Leakage-Resilient Signatures with Graceful Degradation (AF, JBN, DV), pp. 456–468.
DATEDATE-2014-YehHN #power management
Leakage-power-aware clock period minimization (HHY, SHH, YTN), pp. 1–6.
FMFM-2014-WenMM #analysis #formal method #information management #towards
Towards a Formal Analysis of Information Leakage for Signature Attacks in Preferential Elections (RW, AM, CM), pp. 595–610.
ICEISICEIS-v2-2014-Hauer #state of the art
Data Leakage Prevention — A Position to State-of-the-Art Capabilities and Remaining Risk (BH), pp. 361–367.
SACSAC-2014-HalderZC #analysis #database #information management #query
Information leakage analysis of database query languages (RH, MZ, AC), pp. 813–820.
HPCAHPCA-2014-FletcherRYDKD #information management #performance #ram #trade-off
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs (CWF, LR, XY, MvD, OK, SD), pp. 213–224.
ISSTAISSTA-2014-ZhangC #automation #detection #exception #information management #lightweight
Lightweight automated detection of unsafe information leakage via exceptions (BZ, JC), pp. 327–338.
DATEDATE-2013-JoshiLBBG #estimation #performance #statistics
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits (SJ, AL, MB, EB, SG), pp. 1056–1057.
DATEDATE-2013-KahngKP #power management #reduction
Active-mode leakage reduction with data-retained power gating (ABK, SK, BP), pp. 1209–1214.
DATEDATE-2013-ZapaterAMVGC #energy #performance
Leakage and temperature aware server control for improving energy efficiency in data centers (MZ, JLA, JMM, KV, KCG, AKC), pp. 266–269.
HPCAHPCA-2013-ChangRLJ #comparison #energy #scalability
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM (MTC, PR, SLL, BJ), pp. 143–154.
CAVCAV-2013-ChothiaKN #information management
A Tool for Estimating Information Leakage (TC, YK, CN), pp. 690–695.
VMCAIVMCAI-2013-BiondiLMW #information management #protocol #random
Quantifying Information Leakage of Randomized Protocols (FB, AL, PM, AW), pp. 68–87.
CASECASE-2012-KimRYCKKP #case study #metric
A study on the measurement of axial cracks in the Magnetic Flux Leakage NDT system (HMK, YWR, HRY, SHC, DKK, SJK, GSP), pp. 624–629.
DATEDATE-2012-HeuserSS #modelling
Revealing side-channel issues of complex circuits by enhanced leakage models (AH, WS, MS), pp. 1179–1184.
DATEDATE-2012-HuangHLLLG #power management
Off-path leakage power aware routing for SRAM-based FPGAs (KH, YH, XL, BL, HL, JG), pp. 87–92.
DATEDATE-2012-JuanCMC #modelling #optimisation #power management #statistics
Statistical thermal modeling and optimization considering leakage power variations (DCJ, YLC, DM, YWC), pp. 605–610.
DATEDATE-2012-RahmanS #power management
Post-synthesis leakage power minimization (MR, CS), pp. 99–104.
DATEDATE-2012-WangRR #energy #runtime
Run-time power-gating in caches of GPUs for leakage energy savings (YW, SR, NR), pp. 300–303.
DATEDATE-2012-XuLHRHT #analysis #power management
Variation-aware leakage power model extraction for system-level hierarchical power analysis (YX, BL, RH, BR, CH, JT), pp. 346–351.
VLDBVLDB-2012-MouratidisY #information management
Shortest Path Computation with No Information Leakage (KM, MLY), pp. 692–703.
STOCSTOC-2012-BoyleGJK #memory management #multi
Multiparty computation secure against continual memory leakage (EB, SG, AJ, YTK), pp. 1235–1254.
SACSAC-2012-ZanioliFC #information management #named #static analysis
SAILS: static analysis of information leakage with sample (MZ, PF, AC), pp. 1308–1313.
DACDAC-2011-AbrishamiLQFP #optimisation #power management
Post sign-off leakage power optimization (HA, JL, JQ, JF, MP), pp. 453–458.
DACDAC-2011-BanY #layout #modelling #optimisation
Layout aware line-edge roughness modeling and poly optimization for leakage minimization (YB, JSY), pp. 447–452.
DACDAC-2011-KimG #reliability
Leakage-aware redundancy for reliable sub-threshold memories (SK, MRG), pp. 435–440.
DACDAC-2011-KimKY #named #network #power management
FlexiBuffer: reducing leakage power in on-chip network routers (GK, JK, SY), pp. 936–941.
DATEDATE-2011-HuangQ #constraints #energy #realtime
Leakage aware energy minimization for real-time systems under the maximum temperature constraint (HH, GQ), pp. 479–484.
DATEDATE-2011-MistryAFH #power management
Sub-clock power-gating technique for minimising leakage power during active mode (JNM, BMAH, DF, SH), pp. 106–111.
DATEDATE-2011-TsengHWFC #black box #compilation #library #modelling #power management
Black-box leakage power modeling for cell library and SRAM compiler (CKT, SYH, CCW, SCF, JJC), pp. 637–642.
FoSSaCSFoSSaCS-2011-BorealePP #information management
Asymptotic Information Leakage under One-Try Attacks (MB, FP, MP), pp. 396–410.
ICALPICALP-v1-2011-FaustPV #how
Tamper-Proof Circuits: How to Trade Leakage for Tamper-Resilience (SF, KP, DV), pp. 391–402.
KDDKDD-2011-KaufmanRP #data mining #detection #mining
Leakage in data mining: formulation, detection, and avoidance (SK, SR, CP), pp. 556–563.
DACDAC-2010-GaoYWY #analysis #correlation #estimation #performance #statistics
Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis (MG, ZY, YW, ZY), pp. 475–480.
DACDAC-2010-ShenTX #algorithm #analysis #correlation #linear #power management #statistics
A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation (RS, SXDT, JX), pp. 481–486.
DACDAC-2010-YuVH #adaptation #multi #realtime #scheduling
Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems (HY, BV, YH), pp. 493–498.
DATEDATE-2010-DasMZC #detection #hardware #information management #memory management
Detecting/preventing information leakage on the memory bus due to malicious hardware (AD, GM, JZ, ANC), pp. 861–866.
DATEDATE-2010-MeynardGDS
Far Correlation-based EMA with a precharacterized leakage model (OM, SG, JLD, LS), pp. 977–980.
DATEDATE-2010-TieDWC #performance #reduction #scheduling
Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement (MT, HD, TW, XC), pp. 520–525.
DATEDATE-2010-YangCTK #energy #realtime #scheduling
Energy-efficient real-time task scheduling with temperature-dependent leakage (CYY, JJC, LT, TWK), pp. 9–14.
DATEDATE-2010-YuZQB #behaviour #design #power management
Behavioral level dual-vth design for reduced leakage power with thermal awareness (JY, QZ, GQ, JB), pp. 1261–1266.
TACASTACAS-2010-AndresPRS #information management
Computing the Leakage of Information-Hiding Systems (MEA, CP, PvR, GS), pp. 373–389.
TACASTACAS-2010-ChatzikokolakisCG #information management #metric #statistics
Statistical Measurement of Information Leakage (KC, TC, AG), pp. 390–404.
DACDAC-2009-VeetilSBSR #analysis #dependence #performance
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence (VV, DS, DB, SS, SR), pp. 154–159.
DATEDATE-2009-0002CWCXY #optimisation
Gate replacement techniques for simultaneous leakage and aging optimization (YW, XC, WW, YC, YX, HY), pp. 328–333.
DATEDATE-2009-VignonCDMF #3d #architecture #novel
A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context (AV, SC, WD, PM, MF), pp. 929–933.
DATEDATE-2009-XuVJ #runtime
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage (HX, RV, WBJ), pp. 594–597.
DACDAC-2008-AlkabaniMKP #variability
Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability (YA, TM, FK, MP), pp. 606–609.
DACDAC-2008-JeongKPY #power management #reduction
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction (KJ, ABK, CHP, HY), pp. 516–521.
DACDAC-2008-JoshiCSBA #power management #reduction #using
Leakage power reduction using stress-enhanced layouts (VJ, BC, DS, DB, KA), pp. 912–917.
DACDAC-2008-LiZY #analysis #verification
Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification (TL, WZ, ZY), pp. 594–599.
DACDAC-2008-NiM #power management #reduction #scheduling
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction (MN, SOM), pp. 610–613.
DATEDATE-2008-FrenkilCU #analysis #design #physics #power management
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis (JF, KC, KU).
DATEDATE-2008-HaidZLK #communication
Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication (JH, BZ, TL, TK), pp. 784–787.
DACDAC-2007-ChandraLRD #power management
System-on-Chip Power Management Considering Leakage Power Variations (SC, KL, AR, SD), pp. 877–882.
DACDAC-2007-ChiouJCC #algorithm #fine-grained #power management
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization (DSC, DCJ, YTC, SCC), pp. 81–86.
DACDAC-2007-GuSK #modelling #random #statistics
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift (JG, SSS, CHK), pp. 87–92.
DACDAC-2007-HeloueAN #correlation #estimation #modelling
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation (KRH, NA, FNN), pp. 93–98.
DACDAC-2007-LiY #analysis #power management #statistics
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage (TL, ZY), pp. 99–102.
DACDAC-2007-RastogiCK #on the
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method (AR, WC, SK), pp. 712–715.
DACDAC-2007-SeomunKS
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits (JS, JK, YS), pp. 103–106.
DACDAC-2007-YeZL #optimisation #performance #power management #statistics #using
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization (XY, YZ, PL), pp. 853–858.
DATEDATE-2007-GillPW #fault #interactive #power management #symmetry
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA (BSG, CAP, FGW), pp. 1460–1465.
DATEDATE-2007-GolubevaLPM #architecture
Architectural leakage-aware management of partitioned scratchpad memories (OG, ML, MP, EM), pp. 1665–1670.
DATEDATE-2007-JayakumarK #algorithm
An algorithm to minimize leakage through simultaneous input vector control and circuit modification (NJ, SPK), pp. 618–623.
DATEDATE-2007-LiuDSY #estimation #power management
Accurate temperature-dependent integrated circuit leakage power estimation is easy (YL, RPD, LS, HY), pp. 1526–1531.
DATEDATE-2007-MogalB #architecture #reduction
Microarchitecture floorplanning for sub-threshold leakage reduction (HM, KB), pp. 1238–1243.
LCTESLCTES-2007-ZhuM #feedback #named #reduction #scalability #scheduling
DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling (YZ, FM), pp. 31–40.
DACDAC-2006-AnanthanR #physics #process
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS (HA, KR), pp. 413–418.
DACDAC-2006-ChengDCW #algorithm #generative #performance #power management #reduction
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction (LC, LD, DC, MDFW), pp. 117–120.
DACDAC-2006-HuangG #embedded #scalability
Leakage-aware intraprogram voltage scaling for embedded processors (PKH, SG), pp. 364–369.
DACDAC-2006-LiLP #analysis #power management #statistics
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions (XL, JL, LTP), pp. 103–108.
DACDAC-2006-MengSK #embedded #power management #reduction
Leakage power reduction of embedded memories on FPGAs through location assignment (YM, TS, RK), pp. 612–617.
DACDAC-2006-NabaaAN #adaptation #architecture #process
An adaptive FPGA architecture with process variation compensation and reduced leakage (GN, NA, FNN), pp. 624–629.
DACDAC-2006-ShahGK #library #optimisation #reduction #standard
Standard cell library optimization for leakage reduction (SS, PG, ABK), pp. 983–986.
DACDAC-2006-SinghMPO #nondeterminism #runtime
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty (AKS, MM, RP, MO), pp. 522–527.
DATEDATE-2006-AmelifardFP #using
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment (BA, FF, MP), pp. 995–1000.
DATEDATE-2006-BabighianBMM
Enabling fine-grain leakage management by voltage anchor insertion (PB, LB, AM, EM), pp. 868–873.
DATEDATE-2006-KandemirCLIK #clustering #process
Activity clustering for leakage management in SPMs (MTK, GC, FL, MJI, IK), pp. 696–697.
DATEDATE-2006-KumarA #power management
An analytical state dependent leakage power model for FPGAs (AK, MA), pp. 612–617.
DATEDATE-2006-MohantyVK #optimisation
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits (SPM, RV, EK), pp. 1191–1196.
DATEDATE-2006-RaychowdhuryPBR #case study #comparative #power management
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies (AR, BCP, SB, KR), pp. 856–861.
SIGMODSIGMOD-2006-KabraRS #data access #fine-grained #information management
Redundancy and information leakage in fine-grained access control (GK, RR, SS), pp. 133–144.
ICALPICALP-v2-2006-Boreale #calculus #information management #process
Quantifying Information Leakage in Process Calculi (MB), pp. 119–131.
LCTESLCTES-2006-ChenK #scalability #scheduling
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor (JJC, TWK), pp. 153–162.
DACDAC-2005-BhardwajV #random
Leakage minimization of nano-scale circuits in the presence of systematic and random variations (SB, SBKV), pp. 541–546.
DACDAC-2005-BhuniaBCMR #approach #novel #power management #reduction #synthesis #using
A novel synthesis approach for active leakage power reduction using dynamic supply gating (SB, NB, QC, HMM, KR), pp. 479–484.
DACDAC-2005-ChangS #analysis #correlation #power management #process
Full-chip analysis of leakage power under process variations, including spatial correlations (HC, SSS), pp. 523–528.
DACDAC-2005-JayakumarDK #monitoring #self
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents (NJ, SD, SPK), pp. 43–46.
DACDAC-2005-LinH #performance #reduction
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction (YL, LH), pp. 720–725.
DACDAC-2005-RoyannezMDWSBBCSDSPRK #design #framework #reduction
A design platform for 90-nm leakage reduction techniques (PR, HM, FD, MW, MS, LB, JB, HC, GS, JD, DS, BP, CR, UK), pp. 549–550.
DACDAC-2005-SrivastavaSASBD #correlation #estimation #parametricity #performance #power management
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (AS, SS, KA, DS, DB, SWD), pp. 535–540.
DACDAC-2005-TangZB #library #optimisation #power management #synthesis
Leakage power optimization with dual-Vth library in high-level synthesis (XT, HZ, PB), pp. 202–207.
DACDAC-2005-TiriHHLYSV #embedded #encryption
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing (KT, DDH, AH, BCL, SY, PS, IV), pp. 222–227.
DACDAC-2005-YuanQ #reduction
Enhanced leakage reduction Technique by gate replacement (LY, GQ), pp. 47–50.
DATEDATE-2005-BaiKKSM #multi #trade-off
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage (RB, NSK, TK, DS, TNM), pp. 650–651.
DATEDATE-2005-HassanADE #power management #process #reduction
Activity Packing in FPGAs for Leakage Power Reduction (HH, MA, AED, MIE), pp. 212–217.
DATEDATE-2005-KitaharaKMSF #design #multi #power management #reduction
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction (TK, NK, FM, KS, TF), pp. 646–647.
DATEDATE-2005-MukhopadhyayBR #analysis #logic #modelling
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits (SM, SB, KR), pp. 224–229.
DATEDATE-2005-TsaiVXI #network
Leakage-Aware Interconnect for On-Chip Network (YFT, NV, YX, MJI), pp. 230–231.
DRRDRR-2005-LoprestiS #documentation #information management
Information leakage through document redaction: attacks and countermeasures (DPL, ALS), pp. 183–190.
CIKMCIKM-2005-XiongSK #database #learning #multi #privacy
Privacy leakage in multi-relational databases via pattern based semi-supervised learning (HX, MS, VK), pp. 355–356.
HPCAHPCA-2005-MengSK #on the #power management #reduction
On the Limits of Leakage Power Reduction in Caches (YM, TS, RK), pp. 154–165.
DACDAC-2004-AgarwalKMR #design
Leakage in nano-scale technologies: mechanisms, impact and design considerations (AA, CHK, SM, KR), pp. 6–11.
DACDAC-2004-BasuLWMB #optimisation #power management
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era (AB, SCL, VW, AM, KB), pp. 884–887.
DACDAC-2004-DeogunRSB #encoding #reduction
Leakage-and crosstalk-aware bus encoding for total power reduction (HD, RRR, DS, DB), pp. 779–782.
DACDAC-2004-GuptaKSS #effectiveness #runtime
Selective gate-length biasing for cost-effective runtime leakage control (PG, ABK, PS, DS), pp. 327–330.
DACDAC-2004-HeLS #reduction
System level leakage reduction considering the interdependence of temperature and leakage (LH, WL, MRS), pp. 12–17.
DACDAC-2004-JejurikarPG #embedded #realtime #scalability
Leakage aware dynamic voltage scaling for real-time embedded systems (RJ, CP, RKG), pp. 275–280.
DACDAC-2004-RaoDBS #estimation #parametricity #variability
Parametric yield estimation considering leakage variability (RRR, AD, DB, DS), pp. 442–447.
DACDAC-2004-SrivastavaSB #optimisation #power management #process #statistics #using
Statistical optimization of leakage power considering process variations using dual-Vth and sizing (AS, DS, DB), pp. 773–778.
DACDAC-2004-SultaniaSS #trade-off
Tradeoffs between date oxide leakage and delay for dual Tox circuits (AKS, DS, SSS), pp. 761–766.
DATEDATE-v1-2004-AndreiSEPA #energy #reduction
Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems (AA, MTS, PE, ZP, BMAH), pp. 518–525.
DATEDATE-v1-2004-BabighianBM04a #distributed
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating (PB, LB, EM), pp. 720–723.
DATEDATE-v1-2004-ChenG #adaptation #bias #low cost #performance #power management #reduction
A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations (TWC, JG), pp. 240–245.
DATEDATE-v1-2004-LiPZSSS
State-Preserving vs. Non-State-Preserving Leakage Control in Caches (YL, DP, YZ, KS, MRS, KS), pp. 22–29.
VLDBVLDB-2004-YangL #information management #xml
Secure XML Publishing without Information Leakage in the Presence of Data Inference (XY, CL), pp. 96–107.
ASPLOSASPLOS-2004-ZhuangZP #framework #information management #named
HIDE: an infrastructure for efficiently protecting information leakage on the address bus (XZ, TZ, SP), pp. 72–84.
DACDAC-2003-FerzliN #estimation #grid #power management #process #statistics
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations (IAF, FNN), pp. 856–859.
DACDAC-2003-LeeB #reduction
Static leakage reduction through simultaneous threshold voltage and state assignment (DL, DB), pp. 191–194.
DACDAC-2003-LeeKBS #analysis
Analysis and minimization techniques for total leakage considering gate oxide leakage (DL, WK, DB, DS), pp. 175–180.
DACDAC-2003-MukhopadhyayRR #estimation #logic #modelling
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling (SM, AR, KR), pp. 169–174.
DACDAC-2003-TsaiDVI #reduction #scalability
Implications of technology scaling on leakage reduction techniques (YFT, DD, NV, MJI), pp. 187–190.
DATEDATE-2003-ZhangKVID #compilation #energy
Compiler Support for Reducing Leakage Energy Consumption (WZ, MTK, NV, MJI, VD), pp. 11146–11147.
LCTESLCTES-2003-KimVKI #adaptation #architecture #optimisation #parallel
Adapting instruction level parallelism for optimizing leakage in VLIW architectures (HSK, NV, MTK, MJI), pp. 275–283.
DACDAC-2002-AnisMEA #automation #clustering #performance #power management #reduction #using
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique (MA, MM, MIE, SA), pp. 480–485.
DATEDATE-2002-KimR #power management #reduction #scalability
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction (CHK, KR), pp. 163–167.
DATEDATE-2001-NaiduJ #power management
Minimizing stand-by leakage power in static CMOS circuits (SRN, ETAFJ), pp. 370–376.
QAPLQAPL-2001-ClarkHM #analysis
Quantitative Analysis of the Leakage of Confidential Data (DC, SH, PM), pp. 238–251.
HPCAHPCA-2001-YangPFRV #approach #architecture
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches (SHY, MDP, BF, KR, TNV), pp. 147–157.
DACDAC-1999-JohnsonSR #performance
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS (MCJ, DS, KR), pp. 442–445.
DACDAC-1992-ChakravartyL #algorithm #fault #monitoring
Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults (SC, ML), pp. 353–356.

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