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power management
Google power management

Tag #power management

597 papers:

KDDKDD-2019-ZhaoWSNHJSNBRPL #detection #smarttech
Raise to Speak: An Accurate, Low-power Detector for Activating Voice Assistants on Smartwatches (SZ, BW, SS, HN, RH, MJ, KS, BN, MB, SR, TP, KL, CG), pp. 2736–2744.
CASECASE-2018-ChuBIICS #learning #multi #online #using
Plug-and-Play Power Management Control of All-Electric Vehicles Using Multi-Agent System and On-line Gaussian Learning (KCC, GB, MI, AI, CC, KS), pp. 1599–1604.
CGOCGO-2018-BaghsorkhiM #automation #performance
Automating efficient variable-grained resiliency for low-power IoT systems (SSB, CM), pp. 38–49.
ASPLOSASPLOS-2017-BaiLI #performance
Voltage Regulator Efficiency Aware Power Management (YB, VWL, EI), pp. 825–838.
ASPLOSASPLOS-2017-CherupalliDY0S #energy #requirements
Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors (HC, HD, WY, RK0, JS), pp. 3–16.
CASECASE-2017-FangDDW #grid
Peak shaving strategy of power grid with concentrating solar power plant (LF, HD, KD, NW), pp. 1633–1638.
CASECASE-2017-MengZRLT #case study #process
Study on the power consumption of different milling modes and number of inserts in face milling processes (LM, CZ, YR, ML, GT), pp. 1475–1480.
CASECASE-2017-WangXBYL #constraints #evaluation #grid #hybrid #reliability #security
Reliability evaluation of AC/DC hybrid power grid considering transient security constraints (CW, HX, ZB, CY, YL), pp. 1237–1242.
MSRMSR-2016-BaoLXWT #android #commit #developer #empirical #how #mining
How android app developers manage power consumption?: an empirical study by mining power management commits (LB, DL0, XX0, XW0, CT), pp. 37–48.
CASECASE-2016-MengZZT #predict #process
A new model for predicting power consumption of machining processes: A turning case (LM, MZ, CZ, GT), pp. 1289–1294.
HCIDHM-EH-2015-LiuCKQF #data analysis
Balancing Power Consumption and Data Analysis Accuracy Through Adjusting Sampling Rates: Seeking for the Optimal Configuration of Inertial Sensors for Power Wheelchair Users (TL, CC, MK, GQ, JF), pp. 184–192.
SIGIRSIGIR-2015-CatenaMT #cpu #web
Load-sensitive CPU Power Management for Web Search Engines (MC, CM, NT), pp. 751–754.
SACSAC-2015-Jung0B #analysis #embedded #encoding #identification
Identification of embedded control units by state encoding and power consumption analysis (EJ, CM, LB), pp. 1957–1959.
SACSAC-2015-LagoMM #estimation #network
High speed network impacts and power consumption estimation for cloud data centers (DGdL, ERMM, DM), pp. 615–620.
SACSAC-2015-MonteiroL #clustering #scalability #web
Scalable model for dynamic configuration and power management in virtualized heterogeneous web clusters (AFM, OL), pp. 464–467.
SACSAC-2015-XiongN #estimation #low cost
Cost-efficient and attack-resilient approaches for state estimation in power grids (KX, PN), pp. 2192–2197.
ASPLOSASPLOS-2015-XuLWZ #automation #runtime
Automated OS-level Device Runtime Power Management (CX, FXL, YW, LZ), pp. 239–252.
DACDAC-2015-ChenCX #classification #named #video
DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification (XC, YC, CJX), p. 6.
DACDAC-2015-ChiangCLJ #design #scalability
Scalable sequence-constrained retention register minimization in power gating design (TWC, KHC, YTL, JHRJ), p. 6.
DACDAC-2015-GangopadhyayNR
Integrated power management in IoT devices under wide dynamic ranges of operation (SG, SBN, AR), p. 6.
DACDAC-2015-JiangWS #clustering #sorting
A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space (ZJ, QW, MS), p. 6.
DACDAC-2015-LiCSHLWY #hybrid
A STT-RAM-based low-power hybrid register file for GPGPUs (GL, XC, GS, HH, YL, YW, HY), p. 6.
DACDAC-2015-PanthSDL #3d #clustering #delivery #mobile #trade-off
Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications (SP, KS, YD, SKL), p. 6.
DACDAC-2015-RakshitWLGM #design #robust
Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design (JR, RW, KTL, JG, KM), p. 6.
DACDAC-2015-WangLYSOC #grid #novel #reduction
Novel power grid reduction method based on L1 regularization (YW, ML, XY, ZS, MO, CC), p. 6.
DACDAC-2015-ZhanOGZ0 #approach #named #network #towards
DimNoC: a dim silicon approach towards power-efficient on-chip network (JZ, JO, FG, JZ, YX), p. 6.
DATEDATE-2015-AmirhosseinRBCM
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission (MSA, PMR, AB, MC, MM, DD, GM), pp. 1479–1484.
DATEDATE-2015-BortolottiMBRSB #monitoring
An ultra-low power dual-mode ECG monitor for healthcare and wellness (DB, MM, AB, RR, GS, LB), pp. 1611–1616.
DATEDATE-2015-DoustiP #distributed
Power-efficient control of thermoelectric coolers considering distributed hot spots (MJD, MP), pp. 966–971.
DATEDATE-2015-GaillardonTSTOS
A ultra-low-power FPGA based on monolithically integrated RRAMs (PEG, XT, JS, MT, SRO, DS, YL, GDM), pp. 1203–1208.
DATEDATE-2015-HaghbayanRFLPNT #manycore #online #testing
Power-aware online testing of manycore systems in the dark silicon era (MHH, AMR, MF, PL, JP, ZN, HT), pp. 435–440.
DATEDATE-2015-HanyuSOMNM #architecture #in memory #paradigm #reliability #towards
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm (TH, DS, NO, SM, MN, AM), pp. 1006–1011.
DATEDATE-2015-KhanSH #adaptation #manycore
Power-efficient accelerator allocation in adaptive dark silicon many-core systems (MUKK, MS, JH), pp. 916–919.
DATEDATE-2015-LiuHFRQR
Power minimization for data center with guaranteed QoS (SL, SH, MF, SR, GQ, SR), pp. 1347–1352.
DATEDATE-2015-LiXWNP #fine-grained #multi #reduction #using
Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique (JL, QX, YW, SN, MP), pp. 1579–1582.
DATEDATE-2015-MamaghanianV #design
Ultra-low-power ECG front-end design based on compressed sensing (HM, PV), pp. 671–676.
DATEDATE-2015-MuzaffarYSE
A pulsed-index technique for single-channel, low-power, dynamic signaling (SM, JY, AS, IAME), pp. 1485–1490.
DATEDATE-2015-Sharma #optimisation
Minimum current consumption transition time optimization methodology for low power CTS (VS), pp. 412–416.
DATEDATE-2015-SinglaKUO #mobile #platform #predict
Predictive dynamic thermal and power management for heterogeneous mobile platforms (GS, GK, AKU, ÜYO), pp. 960–965.
DATEDATE-2015-TouatiBDGVBR #functional #source code #testing
Exploring the impact of functional test programs re-used for power-aware testing (AT, AB, LD, PG, AV, PB, MSR), pp. 1277–1280.
DATEDATE-2015-ZhangYWLC #design #logic
Giant spin hall effect (GSHE) logic design for low power application (YZ, BY, WW, HL, YC), pp. 1000–1005.
HPCAHPCA-2015-AroraMPJT #behaviour #benchmark #comprehension #cpu #gpu #metric
Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems (MA, SM, IP, NJ, DMT), pp. 366–377.
SOSPSOSP-2015-LentzLB
Drowsy power management (ML, JL, BB), pp. 230–244.
VLDBVLDB-2014-YuYWLC #big data #classification #design #detection
Big Data Small Footprint: The Design of A Low-Power Classifier for Detecting Transportation Modes (MCY, TY, SCW, CJL, EYC), pp. 1429–1440.
CHICHI-2014-KihmGKM #interactive #symmetry #using
Using asymmetric cores to reduce power consumption for interactive devices with bi-stable displays (JK, FG, JK, RM), pp. 1059–1062.
SEKESEKE-2014-ParkHL #refactoring
Investigation for Software Power Consumption of Code Refactoring Techniques (JJP, JEH, SHL), pp. 717–722.
PLDIPLDI-2014-PhothilimthanaJSTCB #architecture #compilation #named
Chlorophyll: synthesis-aided compiler for low-power spatial architectures (PMP, TJ, RS, NT, SC, RB), p. 42.
ASPLOSASPLOS-2014-MuthukaruppanPM #multi
Price theory based power management for heterogeneous multi-cores (TSM, AP, TM), pp. 161–176.
DACDAC-2014-AhnYC #hybrid #memory management
Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes (JA, SY, KC), p. 6.
DACDAC-2014-AkgulPLBPBT
Power management through DVFS and dynamic body biasing in FD-SOI circuits (YA, DP, SL, EB, IMP, PB, LT), p. 6.
DACDAC-2014-AlbalawiLL #algorithm #classification #design #fixpoint #implementation #machine learning
Computer-Aided Design of Machine Learning Algorithm: Training Fixed-Point Classifier for On-Chip Low-Power Implementation (HA, YL, XL), p. 6.
DACDAC-2014-BraojosMJAARM #design #monitoring #smarttech
Ultra-Low Power Design of Wearable Cardiac Monitoring Systems (RB, HM, ADJ, GA, DA, FJR, SM), p. 6.
DACDAC-2014-ClercqUHV #implementation
Ultra Low-Power implementation of ECC on the ARM Cortex-M0+ (RdC, LU, AVH, IV), p. 6.
DACDAC-2014-DoustiP #deployment
Power-Aware Deployment and Control of Forced-Convection and Thermoelectric Coolers (MJD, MP), p. 6.
DACDAC-2014-HuangYST #assessment #grid #network
Physics-based Electromigration Assessment for Power Grid Networks (XH, TY, VS, SXDT), p. 6.
DACDAC-2014-IyengarG #analysis #embedded #memory management #modelling #robust
Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory (AI, SG), p. 6.
DACDAC-2014-LinKH #mobile
Catch Your Attention: Quality-retaining Power Saving on Mobile OLED Displays (CHL, CKK, PCH), p. 6.
DACDAC-2014-LinWC #data mining #design #logic #mining #named #synthesis
C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs (CHL, LW, DC), p. 6.
DACDAC-2014-ParikhDB #configuration management
Power-Aware NoCs through Routing and Topology Reconfiguration (RP, RD, VB), p. 6.
DACDAC-2014-PathaniaJPM #3d #cpu #game studies #gpu #mobile
Integrated CPU-GPU Power Management for 3D Mobile Games (AP, QJ, AP, TM), p. 6.
DACDAC-2014-QiuLX #performance
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM (KQ, QL, CJX), p. 6.
DACDAC-2014-SorinMZ #architecture
Architecting Dynamic Power Management to be Formally Verifiable (DJS, OM, MZ), p. 3.
DACDAC-2014-ZhangPL #hardware
Low Power GPGPU Computation with Imprecise Hardware (HZ, MP, JL), p. 6.
DACDAC-2014-ZhuoGS #design #grid #modelling #optimisation
Early-Stage Power Grid Design: Extraction, Modeling and Optimization (CZ, HG, WKS), p. 6.
DATEDATE-2014-AhariAKT #architecture #configuration management #using
A power-efficient reconfigurable architecture using PCM configuration technology (AA, HA, BK, MBT), pp. 1–6.
DATEDATE-2014-AlordaCB #embedded #reliability
Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications (BA, CC, SAB), pp. 1–6.
DATEDATE-2014-AshammagariMH #configuration management #design #functional #performance
Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design (ARA, HM, HH), pp. 1–6.
DATEDATE-2014-BishnoiEOT #symmetry #termination
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM (RB, ME, FO, MBT), pp. 1–6.
DATEDATE-2014-BortolottiBWRB #architecture #hybrid #manycore #memory management #scalability
Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors (DB, AB, CW, DR, LB), pp. 1–6.
DATEDATE-2014-BraojosDBAA #approach #hardware #manycore
Hardware/software approach for code synchronization in low-power multi-core sensor nodes (RB, AYD, IB, GA, DA), pp. 1–6.
DATEDATE-2014-CasamassimaFB #network
Context aware power management for motion-sensing body area network nodes (FC, EF, LB), pp. 1–6.
DATEDATE-2014-ConosMDP #coordination #energy #using
Provably minimal energy using coordinated DVS and power gating (NAC, SM, FD, MP), pp. 1–6.
DATEDATE-2014-DuricPSUCVB #execution #named
EVX: Vector execution on low power EDGE cores (MD, OP, AS, OSÜ, AC, MV, DB), pp. 1–4.
DATEDATE-2014-HeYH0 #design #named
SuperRange: Wide operational range power delivery design for both STV and NTV computing (XH, GY, YH, XL), pp. 1–6.
DATEDATE-2014-KhanSH #architecture #manycore #performance #video
Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing (MUKK, MS, JH), pp. 1–6.
DATEDATE-2014-LeeA #architecture #hybrid #novel #using
A novel low power 11-bit hybrid ADC using flash and delay line architectures (HCL, JAA), pp. 1–4.
DATEDATE-2014-LiuHL #approximate #configuration management #fault #multi
A low-power, high-performance approximate multiplier with configurable partial error recovery (CL, JH, FL), pp. 1–4.
DATEDATE-2014-NejatAA #process
Dynamic Flip-Flop conversion to tolerate process variation in low power circuits (MN, BA, AAK), pp. 1–4.
DATEDATE-2014-PrenatPLGJDSPN #logic
Magnetic memories: From DRAM replacement to ultra low power logic chips (GP, GdP, CL, OG, KJ, BD, RCS, ILP, JPN), p. 1.
DATEDATE-2014-PuEMG #logic #scalability #synthesis
Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling (YP, JDE, MM, JPdG), pp. 1–2.
DATEDATE-2014-SunMSPL #design #robust
A low power and robust carbon nanotube 6T SRAM design with metallic tolerance (LS, JM, RAS, DKP, ZL), pp. 1–4.
DATEDATE-2014-TrivediAM
Ultra-low power electronics with Si/Ge tunnel FET (ART, MFA, SM), pp. 1–6.
DATEDATE-2014-WangXWCWW #manycore
Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors (XW, JX, ZW, KJC, XW, ZW), pp. 1–4.
DATEDATE-2014-YehHN
Leakage-power-aware clock period minimization (HHY, SHH, YTN), pp. 1–6.
DATEDATE-2014-ZhangZKKQZRC
Spintronics for low-power computing (YZ, WZ, JOK, WK, DQ, YZ, DR, CC), pp. 1–6.
HPCAHPCA-2014-DiTomasoKL #architecture #fault tolerance #named
QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers (DD, AKK, AL), pp. 320–331.
HPCAHPCA-2014-MatthewsZS
Scalably verifiable dynamic power management (OM, MZ, DJS), pp. 579–590.
HPCAHPCA-2014-WonCGHS #learning #network #online
Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management (JYW, XC, PG, JH, VS), pp. 308–319.
PDPPDP-2014-TradowskyGBSMB #adaptation #concept #locality #named
SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor (CT, TG, TB, WS, KDMG, JB), pp. 478–481.
EDOCEDOC-2013-NowakBLU #process #re-engineering
Determining Power Consumption of Business Processes and Their Activities to Enable Green Business Process Reengineering (AN, TB, FL, NU), pp. 259–266.
MLDMMLDM-2013-YasojimaFBOS #analysis #case study #generative
Partial Discharge Analysis and Inspection Alert Generation in High Power Transformers: A Case Study of an Autotransformer Bank at Eletrobrás-ELETRONORTE Vila do Conde Station (CTKY, MSF, FdSB, TFdO, AMdS), pp. 367–378.
DACDAC-2013-CalhounC #delivery #energy #flexibility #performance
Flexible on-chip power delivery for energy efficient heterogeneous systems (BHC, KC), p. 6.
DACDAC-2013-CarloYM #3d #delivery #induction #integration #on the
On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery (SC, WY, SM), p. 8.
DACDAC-2013-Feng #grid #scalability #verification
Scalable vectorless power grid current integrity verification (ZF), p. 8.
DACDAC-2013-Flynn
Power gating applied to MP-SoCs for standby-mode power management (DF), p. 5.
DACDAC-2013-KarnikPB #delivery
Power management and delivery for high-performance microprocessors (TK, M(P, SB), p. 3.
DACDAC-2013-MishraS #grid
The impact of electromigration in copper interconnects on power grid integrity (VM, SSS), p. 6.
DACDAC-2013-MuthukaruppanPVMV #manycore #symmetry
Hierarchical power management for asymmetric multi-core in dark silicon era (TSM, MP, VV, TM, SV), p. 9.
DACDAC-2013-OnizawaG #clustering #network #scalability
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks (NO, WJG), p. 6.
DACDAC-2013-SharadFR #memory management
Ultra low power associative computing with spin neurons and resistive crossbar memory (MS, DF, KR), p. 6.
DACDAC-2013-SunWL #design #memory management
Cross-layer racetrack memory design for ultra high density and low power consumption (ZS, WW, HHL), p. 6.
DACDAC-2013-TrivediCM #case study
Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier (ART, SC, SM), p. 6.
DACDAC-2013-TsengGS
Underpowering NAND flash: profits and perils (HWT, LMG, SS), p. 6.
DACDAC-2013-WangYRNZMMB #design #grid
Role of power grid in side channel attack and power-grid-aware secure design (XW, WY, DBR, SN, YZ, SM, DM, SB), p. 9.
DACDAC-2013-XiongW #abstraction #constraints #grid #verification
Constraint abstraction for vectorless power grid verification (XX, JW), p. 6.
DATEDATE-2013-DaloukasMETS #approach #delivery #network #parallel #performance
A parallel fast transform-based preconditioning approach for electrical-thermal co-simulation of power delivery networks (KD, AM, NEE, PT, GIS), pp. 1689–1694.
DATEDATE-2013-DarbelL
SoC low-power practices for wireless applications (ND, SL), p. 778.
DATEDATE-2013-DoganBCABA #analysis #embedded #execution #multi #platform
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms (AYD, RB, JC, GA, AB, DA), pp. 396–399.
DATEDATE-2013-DutoitGP #3d #integration
3D integration for power-efficient computing (DD, EG, IMP), pp. 779–784.
DATEDATE-2013-Feng #geometry #grid #reduction #scalability
Large-scale flip-chip power grid reduction with geometric templates (ZF), pp. 1679–1682.
DATEDATE-2013-GrimmMP #challenge
Ultra-low power: an EDA challenge (CG, JM, XP), p. 483.
DATEDATE-2013-JooyaB #using
Using synchronization stalls in power-aware accelerators (AJ, AB), pp. 400–403.
DATEDATE-2013-KahngKP #reduction
Active-mode leakage reduction with data-retained power gating (ABK, SK, BP), pp. 1209–1214.
DATEDATE-2013-KappelHHHHH #concept #energy #self
Alternative power supply concepts for self-sufficient wireless sensor nodes by energy harvesting (RK, GH, GH, TH, GH, GH), p. 481.
DATEDATE-2013-KodakaTSYKTXSUTMM #manycore #predict
A near-future prediction method for low power consumption on a many-core processor (TK, AT, SS, AY, TK, TT, HX, TS, HU, JT, TM, NM), pp. 1058–1059.
DATEDATE-2013-LorenteVSPCLD #ram
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes (VL, AV, JS, SP, RC, PL, JD), pp. 83–88.
DATEDATE-2013-LotfianJ #architecture #hardware #smarttech #using
An ultra-low power hardware accelerator architecture for wearable computers using dynamic time warping (RL, RJ), pp. 913–916.
DATEDATE-2013-MishraBTRF #energy
A sub-μa power management circuit in 0.18μm CMOS for energy harvesters (BM, CB, GT, CR, PAF), pp. 1197–1202.
DATEDATE-2013-MiyamoriXKUST #development #manycore
Development of low power many-core SoC for multimedia applications (TM, HX, TK, HU, TS, JT), pp. 773–777.
DATEDATE-2013-OlivoGCM #delivery
Electronic implants: power delivery and management (JO, SSG, SC, GDM), pp. 1540–1545.
DATEDATE-2013-PerelliCMBMB #design #health #monitoring
Design of an ultra-low power device for aircraft structural health monitoring (AP, CC, LDM, DB, AM, LB), pp. 1127–1130.
DATEDATE-2013-RaminiGBB #3d #analysis #manycore #using
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis (LR, PG, SB, DB), pp. 1589–1594.
DATEDATE-2013-RethyDSDG #interface #network
A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks (JVR, HD, VDS, WD, GGEG), pp. 1431–1435.
DATEDATE-2013-ShafiqueVH #adaptation #hybrid #manycore #self
Self-adaptive hybrid dynamic power management for many-core systems (MS, BV, JH), pp. 51–56.
DATEDATE-2013-StanisicVCDMLM #analysis #embedded #performance #platform
Performance analysis of HPC applications on low-power embedded platforms (LS, BV, JC, AD, VMM, AL, JFM), pp. 475–480.
DATEDATE-2013-XiaoINSC
Saliency aware display power management (YX, KMI, VN, DS, NC), pp. 1203–1208.
DATEDATE-2013-ZhouMS #locality #optimisation
Placement optimization of power supply pads based on locality (PZ, VM, SSS), pp. 1655–1660.
DATEDATE-2013-ZordanBDGTVB #fault
Test solution for data retention faults in low-power SRAMs (LBZ, AB, LD, PG, AT, AV, NB), pp. 442–447.
HPCAHPCA-2013-GilaniKS
Power-efficient computing for compute-intensive GPGPU applications (SZG, NSK, MJS), pp. 330–341.
HPCAHPCA-2013-LeeKH0
Skinflint DRAM system: Minimizing DRAM chip writes for low power (YL, SK, SH, JL), pp. 25–34.
LCTESLCTES-2013-LiJZHX #compilation #performance
Compiler directed write-mode selection for high performance low power volatile PCM (QL, LJ, YZ, YH, CJX), pp. 101–110.
PDPPDP-2013-BachCMK #clustering #data analysis #grid #multi
Power Grid Time Series Data Analysis with Pig on a Hadoop Cluster Compared to Multi Core Systems (FB, HKÇ, HM, UGK), pp. 208–212.
MSRMSR-2012-Hindle #mining
Green mining: A methodology of relating software change to power consumption (AH), pp. 78–87.
KDDKDD-2012-BellalaMALB
Following the electrons: methods for power management in commercial buildings (GB, MM, MFA, GL, CB), pp. 994–1002.
SEKESEKE-2012-XiePDMRTR #categorisation #clustering #grid
Progressive Clustering with Learned Seeds: An Event Categorization System for Power Grid (BX, RJP, HD, JYM, AR, AT, CR), pp. 100–105.
ICSEICSE-2012-Hindle #mining
Green mining: Investigating power consumption across versions (AH), pp. 1301–1304.
SACSAC-2012-MbarekKPA #design #modelling #using
Using model driven engineering to reliably accelerate early Low Power Intent Exploration for a system-on-chip design (OM, AK, AP, MA), pp. 1580–1587.
ASPLOSASPLOS-2012-LinWLZ #named #smarttech #using
Reflex: using low-power processors in smartphones without knowing them (FXL, ZW, RL, LZ), pp. 13–24.
DACDAC-2012-AbhishekN #grid #incremental #verification
Incremental power grid verification (A, FNN), pp. 151–156.
DACDAC-2012-ChangH
Near-threshold operation for power-efficient computing?: it depends.. (LC, WH), pp. 1159–1163.
DACDAC-2012-ChristmannBCWP #energy
Energy harvesting and power management for autonomous sensor nodes (JFC, EB, CC, JW, CP), pp. 1049–1054.
DACDAC-2012-GhasemiSSK #delivery #effectiveness
Cost-effective power delivery to support per-core voltage domains for power-constrained processors (HRG, AAS, MJS, NSK), pp. 56–61.
DACDAC-2012-LeeKYBS #design #guidelines
Circuit and system design guidelines for ultra-low power sensor nodes (YL, YK, DY, DB, DS), pp. 1037–1042.
DACDAC-2012-ShafiqueZWBH #adaptation #memory management #multi #video
Adaptive power management of on-chip video memory for multiview video coding (MS, BZ, FLW, SB, JH), pp. 866–875.
DATEDATE-2012-BonamyPPC #configuration management #named
UPaRC — Ultra-fast power-aware reconfiguration controller (RB, HMP, SP, DC), pp. 1373–1378.
DATEDATE-2012-BoseBDGHJNRSVW #challenge #manycore
Power management of multi-core chips: Challenges and pitfalls (PB, AB, JAD, MSG, MBH, HMJ, IN, JAR, JS, AV, AJW), pp. 977–982.
DATEDATE-2012-DoganCRBA #architecture #design #health #manycore #monitoring #smarttech
Multi-core architecture design for ultra-low-power wearable health monitoring systems (AYD, JC, MR, AB, DA), pp. 988–993.
DATEDATE-2012-HanPC #architecture #configuration management
State-based full predication for low power coarse-grained reconfigurable architecture (KH, SP, KC), pp. 1367–1372.
DATEDATE-2012-HuangHLLLG
Off-path leakage power aware routing for SRAM-based FPGAs (KH, YH, XL, BL, HL, JG), pp. 87–92.
DATEDATE-2012-JeongKKRS #memory management #named
MAPG: Memory access power gating (KJ, ABK, SK, TSR, RDS), pp. 1054–1059.
DATEDATE-2012-JuanCMC #modelling #optimisation #statistics
Statistical thermal modeling and optimization considering leakage power variations (DCJ, YLC, DM, YWC), pp. 605–610.
DATEDATE-2012-MagnoMBPOB #network
Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks (MM, SJM, DB, EMP, BO, LB), pp. 75–80.
DATEDATE-2012-MakosiejTVA #design #embedded #optimisation
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization (AM, OT, AV, AA), pp. 93–98.
DATEDATE-2012-MorchePMV #architecture #named
UWB: Innovative architectures enable disruptive low power wireless applications (DM, MP, GM, PV), pp. 1156–1160.
DATEDATE-2012-RahmanS
Post-synthesis leakage power minimization (MR, CS), pp. 99–104.
DATEDATE-2012-ShafiqueZRKH #adaptation
Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding (MS, BZ, SR, FK, JH), pp. 697–702.
DATEDATE-2012-SharmaCAHCD #variability
Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM (VS, SC, MA, JH, FC, WD), pp. 1042–1047.
DATEDATE-2012-TabkhiS #approach
Application-specific power-efficient approach for reducing register file vulnerability (HT, GS), pp. 574–577.
DATEDATE-2012-TurturiciSFF #embedded #realtime
Low-power embedded system for real-time correction of fish-eye automotive cameras (MT, SS, LF, EF), pp. 340–341.
DATEDATE-2012-WangJZD #design
Low power aging-aware register file design by duty cycle balancing (SW, TJ, CZ, GD), pp. 546–549.
DATEDATE-2012-WilleDOO #automation #design #synthesis #using
Automatic design of low-power encoders using reversible circuit synthesis (RW, RD, CO, AGO), pp. 1036–1041.
DATEDATE-2012-XuLHRHT #analysis
Variation-aware leakage power model extraction for system-level hierarchical power analysis (YX, BL, RH, BR, CH, JT), pp. 346–351.
DATEDATE-2012-YuBL #adaptation #complexity
A complexity adaptive channel estimator for low power (ZY, CHvB, HL), pp. 1531–1536.
DATEDATE-2012-ZhangPM #3d #analysis #grid
Voltage propagation method for 3-D power grid analysis (CZ, VFP, GDM), pp. 844–847.
DATEDATE-2012-ZhengLGBYC #communication #configuration management
Power-efficient calibration and reconfiguration for on-chip optical communication (YZ, PL, MG, JB, SY, KTC), pp. 1501–1506.
DATEDATE-2012-ZimmermannBR #analysis #multi
Analysis of multi-domain scenarios for optimized dynamic power management strategies (JZ, OB, WR), pp. 862–865.
HPDCHPDC-2012-GamellRPM #framework #platform
Exploring cross-layer power management for PGAS applications on the SCC platform (MG, IR, MP, RM), pp. 235–246.
HCIHCI-ITE-2011-PatkiGNP
Low Power Wireless EEG Headset for BCI Applications (SP, BG, TN, JP), pp. 481–490.
MLDMMLDM-2011-AdolfHHCH #analysis #grid
Techniques for Improving Filters in Power Grid Contingency Analysis (RA, DH, MH, YC, ZH), pp. 599–611.
SEKESEKE-2011-LiuGCJ #architecture #design #distributed #grid #realtime
Designing a Distributed Systems Architecture Testbed for Real-Time Power Grid Systems (YL, IG, YC, SJ), pp. 268–271.
PLDIPLDI-2011-SampsonDFGCG #approximate #data type #named
EnerJ: approximate data types for safe and general low-power computation (AS, WD, EF, DG, LC, DG), pp. 164–174.
SACSAC-2011-ChenHT #clustering #quality #requirements
Power management schemes for heterogeneous clusters under quality of service requirements (JJC, KH, LT), pp. 546–553.
SACSAC-2011-LeePKKS #grid #reduction #scheduling #smarttech
Power consumption scheduling for peak load reduction in smart grid homes (JL, GLP, SWK, HJK, COS), pp. 584–588.
ASPLOSASPLOS-2011-DengMRWB #in memory #memory management #named
MemScale: active low-power modes for main memory (QD, DM, LER, TFW, RB), pp. 225–238.
ASPLOSASPLOS-2011-HoffmannSCMAR
Dynamic knobs for responsive power-aware computing (HH, SS, MC, SM, AA, MCR), pp. 199–212.
DACDAC-2011-AbrishamiLQFP #optimisation
Post sign-off leakage power optimization (HA, JL, JQ, JF, MP), pp. 453–458.
DACDAC-2011-CevreroRSBIL #library #logic #standard
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library (AC, FR, MS, SB, PI, YL), pp. 1014–1019.
DACDAC-2011-GhaniN #branch #grid #using #verification
Power grid verification using node and branch dominance (NHAG, FNN), pp. 682–687.
DACDAC-2011-HaddadN #analysis #grid #using
Power grid correction using sensitivity analysis under an RC model (PAH, FNN), pp. 688–693.
DACDAC-2011-HenrySN #embedded
A case for NEMS-based functional-unit power gating of low-power embedded microprocessors (MBH, MS, LN), pp. 872–877.
DACDAC-2011-HuangSH
Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips (TWH, HYS, TYH), pp. 741–746.
DACDAC-2011-IqbalSH #dependence #fault #monte carlo #named #probability #scheduling
SEAL: soft error aware low power scheduling by Monte Carlo state space under the influence of stochastic spatial and temporal dependencies (NI, MAS, JH), pp. 134–139.
DACDAC-2011-JavaidSPH #adaptation #case study #multi #pipes and filters #video
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study (HJ, MS, SP, JH), pp. 1032–1037.
DACDAC-2011-KimKY #named #network
FlexiBuffer: reducing leakage power in on-chip network routers (GK, JK, SY), pp. 936–941.
DACDAC-2011-LiuZXL #clustering #hybrid #in memory #memory management
Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory (TL, YZ, CJX, ML), pp. 405–410.
DACDAC-2011-ParkYL #hybrid #in memory #memory management
Power management of hybrid DRAM/PRAM-based main memory (HP, SY, SL), pp. 59–64.
DACDAC-2011-SunLT #analysis #approximate #grid #incremental #performance
Efficient incremental analysis of on-chip power grid via sparse approximation (PS, XL, MYT), pp. 676–681.
DACDAC-2011-WangXAP #classification #learning #policy #using
Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classification (YW, QX, ACA, MP), pp. 41–46.
DACDAC-2011-WhatmoughDBD
Error-resilient low-power DSP via path-delay shaping (PNW, SD, DMB, ID), pp. 1008–1013.
DACDAC-2011-XuLY #design
Decoupling for power gating: sources of power noise and design strategies (TX, PL, BY), pp. 1002–1007.
DATEDATE-2011-AcquavivaPOS #reliability
System level techniques to improve reliability in high power microcontrollers for automotive applications (AA, MP, MO, MS), pp. 1123–1124.
DATEDATE-2011-BalasubramanianSMNDKMPPVT #low cost #robust
Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system (LB, PS, RKM, PN, RKD, ADK, SM, SP, HP, RCV, ST), pp. 551–554.
DATEDATE-2011-BathenD #distributed #embedded #named #reliability
E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories (LADB, NDD), pp. 1141–1146.
DATEDATE-2011-BernardC
A low-power VLIW processor for 3GPP-LTE complex numbers processing (CB, FC), pp. 234–239.
DATEDATE-2011-BilgicPGB #industrial
Low-power smart industrial control (AB, VP, MG, FB), pp. 595–599.
DATEDATE-2011-BoghratiS #analysis #grid #performance #random
A scaled random walk solver for fast power grid analysis (BB, SSS), pp. 38–43.
DATEDATE-2011-Brown #roadmap
Power management trends in portable consumer applications (JB), pp. 1048–1052.
DATEDATE-2011-CarliBBR #effectiveness #energy #multi
An effective multi-source energy harvester for low power applications (DC, DB, LB, MR), pp. 836–841.
DATEDATE-2011-GhasemazarP #architecture #multi
Variation aware dynamic power management for chip multiprocessor architectures (MG, MP), pp. 473–478.
DATEDATE-2011-GoyalN #grid #performance #using #verification
Efficient RC power grid verification using node elimination (AG, FNN), pp. 257–260.
DATEDATE-2011-KapoorHT #case study #experience #verification
Power management verification experiences in Wireless SoCs (BK, AH, PT), pp. 507–508.
DATEDATE-2011-KapoorJ #design #embedded #tutorial #verification
Embedded tutorial: Addressing critical power management verification issues in low power designs (BK, KMJ), p. 124.
DATEDATE-2011-KobayashiH #analysis #correlation
An LOCV-based static timing analysis considering spatial correlations of power supply variations (SK, KH), pp. 559–562.
DATEDATE-2011-KolpeZS #clustering #manycore
Enabling improved power management in multicore processors through clustered DVFS (TK, AZ, SSS), pp. 293–298.
DATEDATE-2011-MistryAFH
Sub-clock power-gating technique for minimising leakage power during active mode (JNM, BMAH, DF, SH), pp. 106–111.
DATEDATE-2011-PangrleBCDJ #design #verification
Beyond UPF & CPF: Low-power design and verification (BMP, JB, CC, OD, KMJ), p. 252.
DATEDATE-2011-ParkYL #novel
A novel tag access scheme for low power L2 cache (HP, SY, SL), pp. 655–660.
DATEDATE-2011-ReddyCBJ #complexity
A low complexity stopping criterion for reducing power consumption in turbo decoders (PR, FC, AB, MJ), pp. 649–654.
DATEDATE-2011-RinaudoGCMP #approach #design #energy #performance
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems (SR, GG, AC, AM, MP), pp. 1127–1128.
DATEDATE-2011-SterponeCMWF #configuration management
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.
DATEDATE-2011-TsengHWFC #black box #compilation #library #modelling
Black-box leakage power modeling for cell library and SRAM compiler (CKT, SYH, CCW, SCF, JJC), pp. 637–642.
DATEDATE-2011-Wang #coordination #gpu #kernel
Coordinate strip-mining and kernel fusion to lower power consumption on GPU (GW), pp. 1218–1219.
DATEDATE-2011-WeddellMA
Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodes (ASW, GVM, BMAH), pp. 905–908.
DATEDATE-2011-WohSDKSBM
Low power interconnects for SIMD computers (MW, SS, RGD, DK, DS, DB, TNM), pp. 600–605.
DATEDATE-2011-ZhangHCW #grid #network #reduction
A block-diagonal structured model reduction scheme for power grid networks (ZZ, XH, CKC, NW), pp. 44–49.
HPCAHPCA-2011-LiZCL #architecture #energy #manycore #named
SolarCore: Solar energy driven multi-core architecture power management (CL, WZ, CBC, TL), pp. 205–216.
HPCAHPCA-2011-MadanBBA #manycore
A case for guarded power gating for multi-core processors (NM, AB, PB, MA), pp. 291–300.
CHICHI-2010-PatelGR #design #evaluation
The design and evaluation of an end-user-deployable, whole house, contactless power consumption sensor (SNP, SG, MSR), pp. 2471–2480.
SACSAC-2010-BautistaSHPD #clustering #requirements #set
Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption (DB, JS, HH, SP, JD), pp. 521–526.
ASPLOSASPLOS-2010-KirmanM #using
A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing (NK, JFM), pp. 15–28.
DACDAC-2010-CabeQS
Stacking SRAM banks for ultra low power standby mode operation (ACC, ZQ, MRS), pp. 699–704.
DACDAC-2010-Chiprout
On-die power grids: the missing link (EC), pp. 940–945.
DACDAC-2010-FengZ #analysis #grid #parallel #robust
Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis (ZF, ZZ), pp. 661–666.
DACDAC-2010-FujitaYLCAW
Detachable nano-carbon chip with ultra low power (SF, SY, DL, XC, DA, HSPW), pp. 631–632.
DACDAC-2010-KahngKKS #design
Recovery-driven design: a power minimization methodology for error-tolerant processor modules (ABK, SK, RK, JS), pp. 825–830.
DACDAC-2010-Koushanfar #hybrid #network
Hierarchical hybrid power supply networks (FK), pp. 629–630.
DACDAC-2010-NsBNPSGB #design #future of #question #what
What’s cool for the future of ultra low power designs? (NN, JB, KN, VP, TS, AG, SB), pp. 523–524.
DACDAC-2010-PashaDS #architecture #generative
A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking (MAP, SD, OS), pp. 693–698.
DACDAC-2010-SeomunSS #implementation #synthesis
Synthesis and implementation of active mode power gating circuits (JS, IS, YS), pp. 487–492.
DACDAC-2010-ShenTX #algorithm #analysis #correlation #linear #statistics
A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation (RS, SXDT, JX), pp. 481–486.
DACDAC-2010-SridharanM #embedded #realtime #reliability
Reliability aware power management for dual-processor real-time embedded systems (RS, RNM), pp. 819–824.
DACDAC-2010-XiongW #algorithm #constraints #grid #linear #performance #verification
An efficient dual algorithm for vectorless power grid verification under linear current constraints (XX, JW), pp. 837–842.
DACDAC-2010-ZengYFL #analysis #delivery #network #optimisation #trade-off
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation (ZZ, XY, ZF, PL), pp. 831–836.
DATEDATE-2010-AhlendorfG #challenge #design #hardware #monitoring
Hardware / software design challenges of low-power sensor nodes for condition monitoring (HA, LG), p. 659.
DATEDATE-2010-AlordaTBS
Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs (BA, GT, SAB, JS), pp. 429–434.
DATEDATE-2010-Aue #internet #mobile #using
Low power mobile internet devices using LTE technology (VA), p. 794.
DATEDATE-2010-BalatsoukaTKC #fault #testing
Defect aware X-filling for low-power scan testing (SB, VT, XK, KC), pp. 873–878.
DATEDATE-2010-BellasiBCFS #framework #mobile #multi
Constrained Power Management: Application to a multimedia mobile platform (PB, SB, MC, WF, DS), pp. 989–992.
DATEDATE-2010-ChenLTL #design #standard
Power gating design for standard-cell-like structured ASICs (SYC, RBL, HHT, KWL), pp. 514–519.
DATEDATE-2010-HenryN
From transistors to MEMS: Throughput-aware power gating in CMOS circuits (MBH, LN), pp. 130–135.
DATEDATE-2010-JamaaMM #logic
Power consumption of logic circuits in ambipolar carbon nanotube technology (MHBJ, KM, GDM), pp. 303–306.
DATEDATE-2010-JungP #network #nondeterminism #optimisation
Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times (HJ, MP), pp. 351–356.
DATEDATE-2010-LiuTL #automation #design #optimisation
Combining optimizations in automated low power design (QL, TT, WL), pp. 1791–1796.
DATEDATE-2010-LiuTQ #algorithm #constraints #performance
Enhanced Q-learning algorithm for dynamic power management with performance constraint (WL, YT, QQ), pp. 602–605.
DATEDATE-2010-LiuZYX #pseudo #testing
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects (XL, YZ, FY, QX), pp. 1432–1437.
DATEDATE-2010-MishraJ #optimisation #synthesis #using
Low-power FinFET circuit synthesis using surface orientation optimization (PM, NKJ), pp. 311–314.
DATEDATE-2010-PakbazniaGP #resource management
Temperature-aware dynamic resource provisioning in a power-optimized datacenter (EP, MG, MP), pp. 124–129.
DATEDATE-2010-PasettiFS
A High-Voltage Low-Power DC-DC buck regulator for automotive applications (GP, LF, RS), pp. 937–940.
DATEDATE-2010-RaabBHLSESE #design
Low power design of the X-GOLD® SDR 20 baseband processor (WR, JB, JAUH, DL, MS, HE, JUS, GE), pp. 792–793.
DATEDATE-2010-RickettsSRVP
Investigating the impact of NBTI on different power saving cache strategies (AJR, JS, KR, NV, DKP), pp. 592–597.
DATEDATE-2010-ShafikAC #design #embedded #optimisation
Soft error-aware design optimization of low power and time-constrained embedded systems (RAS, BMAH, KC), pp. 1462–1467.
DATEDATE-2010-TajalliL #design #framework #using
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits (AT, YL), pp. 711–716.
DATEDATE-2010-ThonnartVC #framework #integration
A fully-asynchronous low-power framework for GALS NoC integration (YT, PV, FC), pp. 33–38.
DATEDATE-2010-VenutoSCP
Ultra low-power 12-bit SAR ADC for RFID applications (DDV, ES, DTC, YP), pp. 1071–1075.
DATEDATE-2010-YangAFK #design #reliability
Scan based methodology for reliable state retention power gating designs (SY, BMAH, DF, SSK), pp. 69–74.
DATEDATE-2010-YuZQB #behaviour #design
Behavioral level dual-vth design for reduced leakage power with thermal awareness (JY, QZ, GQ, JB), pp. 1261–1266.
HPCAHPCA-2010-WareRFBRRC #approach #architecture
Architecting for power management: The IBM POWER7TM approach (MSW, KR, MSF, BB, JCR, FLRI, JBC), pp. 1–11.
PDPPDP-2010-RayoBMPD #embedded #manycore #parallel #requirements #thread
Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption (DBR, JSB, HHM, SP, JD), pp. 200–204.
PDPPDP-2010-WangHLB
Area and Power-efficient Innovative Network-on-Chip Architecurte (CW, WHH, SEL, NB), pp. 533–539.
CHICHI-2009-ChettyBMJ #comprehension
It’s not easy being green: understanding home computer power management (MC, AJBB, BM, PJ), pp. 1033–1042.
SACSAC-2009-PetrucciLM #adaptation #clustering #framework
A framework for dynamic adaptation of power-aware server clusters (VP, OL, DM), pp. 1034–1039.
ASPLOSASPLOS-2009-CaulfieldGS #clustering #data-driven #memory management #named #performance #using
Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications (AMC, LMG, SS), pp. 217–228.
DACDAC-2009-DingZHCP #framework #integration #named
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration (DD, YZ, HH, RTC, DZP), pp. 264–269.
DACDAC-2009-GhaniN #approximate #grid #performance #using #verification
Fast vectorless power grid verification using an approximate inverse technique (NHAG, FNN), pp. 184–189.
DACDAC-2009-ShiCHMTHW #analysis #gpu #grid #network #performance
GPU friendly fast Poisson solver for structured power grid network analysis (JS, YC, WH, LM, SXDT, PHH, XW), pp. 178–183.
DACDAC-2009-WangCSC #graph #synthesis #using
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (RW, NCC, BS, CKC), pp. 166–171.
DATEDATE-2009-BachmannGHBS
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing (CB, AG, JH, MB, CS), pp. 1614–1619.
DATEDATE-2009-BardineCFGP #migration
A power-efficient migration mechanism for D-NUCA caches (AB, MC, PF, GG, CAP), pp. 598–601.
DATEDATE-2009-BellasiFS #analysis #modelling #multi #predict
Predictive models for multimedia applications power consumption based on use-case and OS level analysis (PB, WF, DS), pp. 1446–1451.
DATEDATE-2009-BolzaniCMMP #concurrent #design #industrial
Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.
DATEDATE-2009-GuXZ #multi
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip (HG, JX, WZ), pp. 3–8.
DATEDATE-2009-SartoriK #architecture #distributed #manycore
Distributed peak power management for many-core architectures (JS, RK), pp. 1556–1559.
DATEDATE-2009-SinghPHMM #embedded
Single ended 6T SRAM with isolated read-port for low-power embedded systems (JS, DKP, SH, SPM, JM), pp. 917–922.
DATEDATE-2009-TaoL #grid
Decoupling capacitor planning with analytical delay model on RLC power grid (YT, SKL), pp. 839–844.
VLDBVLDB-2008-PoessN #analysis #challenge #energy
Energy cost, the key challenge of today’s data centers: a power consumption analysis of TPC-C results (MP, RON), pp. 1229–1240.
SACSAC-2008-TsaiHC #design #queue #scalability
Power-efficient and scalable load/store queue design via address compression (YYT, CJH, CHC), pp. 1523–1527.
ASPLOSASPLOS-2008-RaghavendraRTWZ #coordination #multi
No “power” struggles: coordinated multi-level power management for the data center (RR, PR, VT, ZW, XZ), pp. 48–59.
ASPLOSASPLOS-2008-SulemanQP #concurrent #execution #multi #thread
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs (MAS, MKQ, YNP), pp. 277–286.
DACDAC-2008-ChoLKC #design
The design of a low power carbon nanotube chemical sensor system (TSC, KJL, JK, APC), pp. 84–89.
DACDAC-2008-HsuW #algorithm #memory management #network
A generalized network flow based algorithm for power-aware FPGA memory mapping (TYH, TCW), pp. 30–33.
DACDAC-2008-JeongKPY #reduction
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction (KJ, ABK, CHP, HY), pp. 516–521.
DACDAC-2008-JiangM #reduction #scheduling
Power gating scheduling for power/ground noise reduction (HJ, MMS), pp. 980–985.
DACDAC-2008-JoshiCSBA #reduction #using
Leakage power reduction using stress-enhanced layouts (VJ, BC, DS, DB, KA), pp. 912–917.
DACDAC-2008-LeeJCHKKK
Applying passive RFID system to wireless headphones for extreme low power consumption (JGL, DJ, JC, SH, JKK, JK, SWK), pp. 486–491.
DACDAC-2008-LiBNPC #approach #how #implementation #set
How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach (ML, BB, DN, LVdP, FC), pp. 345–346.
DACDAC-2008-MenezesKA #grid #verification
A “true” electrical cell model for timing, noise, and power grid verification (NM, CVK, CSA), pp. 462–467.
DACDAC-2008-NiM #reduction #scheduling
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction (MN, SOM), pp. 610–613.
DACDAC-2008-SenNSC #adaptation #named #process
Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems (SS, VN, RS, AC), pp. 492–497.
DACDAC-2008-SridharanGM #embedded #realtime
Feedback-controlled reliability-aware power management for real-time embedded systems (RS, NG, RNM), pp. 185–190.
DACDAC-2008-ZhangYZDKDKC #optimisation #using
Low power passive equalizer optimization using tritonic step response (LZ, WY, HZ, AD, GAK, DMD, ESK, CKC), pp. 570–573.
DATEDATE-2008-CalimeraBM #constraints #performance
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints (AC, LB, EM), pp. 973–978.
DATEDATE-2008-ChandraNK #architecture #reduction #testing
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction (AC, FN, RK), pp. 462–467.
DATEDATE-2008-EberleG #architecture #automation #communication #design #network #scalability
A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers (WE, MG), pp. 710–715.
DATEDATE-2008-FrenkilCU #analysis #design #physics
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis (JF, KC, KU).
DATEDATE-2008-GizopoulosRGNW #testing
Power-Aware Testing and Test Strategies for Low Power Devices (DG, KR, PG, NN, XW).
DATEDATE-2008-JungP #nondeterminism
Resilient Dynamic Power Management under Uncertainty (HJ, MP), pp. 224–229.
DATEDATE-2008-LiTM #analysis #grid #named #network
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis (DL, SXDT, BM), pp. 432–437.
DATEDATE-2008-PaulssonHB #integration #metric
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs (KP, MH, JB), pp. 50–55.
DATEDATE-2008-PurnaprajnaPP #configuration management #encryption #multi
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography (MP, CP, MP), pp. 1462–1467.
DATEDATE-2008-RavikumarHW
Test Strategies for Low Power Devices (CPR, MH, XW), pp. 728–733.
DATEDATE-2008-SilvaPS #analysis #performance #representation
Efficient Representation and Analysis of Power Grids (JMSS, JRP, LMS), pp. 420–425.
DATEDATE-2008-TanQ #framework #markov #probability #using
A Framework of Stochastic Power Management Using Hidden Markov Model (YT, QQ), pp. 92–97.
HPCAHPCA-2008-AggarwalCLS
Power-Efficient DRAM Speculation (NA, JFC, MHL, JES), pp. 317–328.
HPCAHPCA-2008-HurL #approach
A comprehensive approach to DRAM power management (IH, CL), pp. 305–316.
CAVCAV-2008-EisnerNY #composition #design #functional #reasoning #verification
Functional Verification of Power Gated Designs by Compositional Reasoning (CE, AN, KY), pp. 433–445.
HCIHCI-IPT-2007-JungC #feedback #mobile
Perceived Magnitude and Power Consumption of Vibration Feedback in Mobile Devices (JJ, SC), pp. 354–363.
HCIHIMI-IIE-2007-KimL07d
Power Saving Medium Access for Beacon-Enabled IEEE 802.15.4 LR-WPANs (JK, WL), pp. 555–562.
HCIHIMI-MTT-2007-ParkPLC #adaptation #framework #human-computer #mobile #network
A Network Framework on Adaptive Power Management in HCI Mobile Terminals (HP, KP, TJL, HC), pp. 728–737.
AdaEuropeAdaEurope-2007-ChanCCTZ #network #testing #towards
Towards the Testing of Power-Aware Software Applications for Wireless Sensor Networks (WKC, TYC, SCC, THT, ZZ), pp. 84–99.
DACDAC-2007-AmelifardP #delivery #network
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network (BA, MP), pp. 168–173.
DACDAC-2007-ChandraLRD
System-on-Chip Power Management Considering Leakage Power Variations (SC, KL, AR, SD), pp. 877–882.
DACDAC-2007-ChengCW #named
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches (LC, DC, MDFW), pp. 318–323.
DACDAC-2007-ChiouJCC #algorithm #fine-grained
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization (DSC, DCJ, YTC, SCC), pp. 81–86.
DACDAC-2007-DadgourB #analysis #design #hybrid
Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications (HFD, KB), pp. 306–311.
DACDAC-2007-KamhiMMNWKMKC #design #question #validation
Early Power-Aware Design & Validation: Myth or Reality? (GK, SM, SBM, WN, YCW, JK, EM, SVK, SC), pp. 210–211.
DACDAC-2007-KangKR #design #using
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop (KK, KK, KR), pp. 934–939.
DACDAC-2007-LiKBR #flexibility #performance
High Performance and Low Power Electronics on Flexible Substrate (JL, KK, AB, KR), pp. 274–275.
DACDAC-2007-LiY #analysis #statistics
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage (TL, ZY), pp. 99–102.
DACDAC-2007-MrugalskiRCT #testing
New Test Data Decompressor for Low Power Applications (GM, JR, DC, JT), pp. 539–544.
DACDAC-2007-ShachamBC #network
The Case for Low-Power Photonic Networks on Chip (AS, KB, LPC), pp. 132–135.
DACDAC-2007-YeZL #optimisation #performance #statistics #using
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization (XY, YZ, PL), pp. 853–858.
DACDAC-2007-ZhuGSDK #architecture #towards #using
Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors (CZ, Z(G, LS, RPD, RGK), pp. 312–317.
DACDAC-2007-ZhuoCLC #hybrid
Dynamic Power Management with Hybrid Power Sources (JZ, CC, KL, NC), pp. 871–876.
DATEDATE-2007-BanerjeeKR #architecture #process
Process variation tolerant low power DCT architecture (NB, GK, KR), pp. 630–635.
DATEDATE-2007-GeWL #configuration management #embedded #memory management #named
DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems (ZG, WFW, HBL), pp. 1343–1348.
DATEDATE-2007-GillPW #fault #interactive #symmetry
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA (BSG, CAP, FGW), pp. 1460–1465.
DATEDATE-2007-JungP #nondeterminism
Dynamic power management under uncertain information (HJ, MP), pp. 1060–1065.
DATEDATE-2007-LiuDSY #estimation
Accurate temperature-dependent integrated circuit leakage power estimation is easy (YL, RPD, LS, HY), pp. 1526–1531.
DATEDATE-2007-Lysecky #embedded #performance
Low-power warp processor for power efficient high-performance embedded systems (RLL), pp. 141–146.
DATEDATE-2007-MoserTBB #adaptation #energy
Adaptive power management in energy harvesting systems (CM, LT, DB, LB), pp. 773–778.
DATEDATE-2007-QiuTW #modelling #optimisation #probability #robust
Stochastic modeling and optimization for robust power management in a partially observable system (QQ, YT, QW), pp. 779–784.
DATEDATE-2007-RaghavanLJCVC #embedded #symmetry
Very wide register: an asymmetric register file organization for low power embedded processors (PR, AL, MJ, FC, DV, HC), pp. 1066–1071.
DATEDATE-2007-SchamannHLB #algorithm #architecture #case study #design
Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system (MS, SH, UL, MB), pp. 1406–1411.
DATEDATE-2007-Stanley-MarbellM #communication #energy #interface #multi
An 0.9 × 1.2”, low power, energy-harvesting system with custom multi-channel communication interface (PSM, DM), pp. 15–20.
DATEDATE-2007-X07a
Power supply and power management in Ubicom, p. 827.
DATEDATE-2007-XuRC #analysis #interactive #pipes and filters
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining (JX, AR, MHC), pp. 1218–1223.
LCTESLCTES-2007-RavindranCM
Compiler-managed partitioned data caches for low power (RAR, MLC, SAM), pp. 237–247.
SOSPSOSP-2007-NathujiS #coordination #enterprise #named
VirtualPower: coordinated power management in virtualized enterprise systems (RN, KS), pp. 265–278.
CGOCGO-2006-SonCK #approach #locality
A Compiler-Guided Approach for Reducing Disk Power Consumption by Exploiting Disk Access Locality (SWS, GC, MTK), pp. 256–268.
DACDAC-2006-BrahmbhattZWQ #adaptation #algorithm #encoding #hybrid #using
Low-power bus encoding using an adaptive hybrid algorithm (ARB, JZ, QW, QQ), pp. 987–990.
DACDAC-2006-BurginCHMMSKFF #adaptation #algorithm #architecture #implementation #trade-off
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm (FB, FC, MH, HM, RMP, RS, HK, NF, WF), pp. 558–561.
DACDAC-2006-ChengDCW #algorithm #generative #performance #reduction
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction (LC, LD, DC, MDFW), pp. 117–120.
DACDAC-2006-ChiouCCY
Timing driven power gating (DSC, SHC, SCC, CY), pp. 121–124.
DACDAC-2006-ChoCCV #cost analysis #embedded #energy
High-level power management of embedded systems with application-specific energy cost functions (YC, NC, CC, SBKV), pp. 568–573.
DACDAC-2006-DadgourJB #architecture #novel
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates (HFD, RVJ, KB), pp. 977–982.
DACDAC-2006-GhantaVBP #analysis #correlation #probability #scalability
Stochastic variational analysis of large power grids considering intra-die correlations (PG, SBKV, SB, RP), pp. 211–216.
DACDAC-2006-GhoshMKR #reduction #self
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM (SG, SM, KK, KR), pp. 971–976.
DACDAC-2006-HattoriIIYKSYNYKTHAHTSMYHMYHTYIKMYITAAO #mobile
Hierarchical power distribution and power management scheme for a single chip mobile processor (TH, TI, MI, EY, HK, GS, TY, KN, HY, TK, YT, MH, HA, IH, KT, YS, NM, YY, TH, YM, KY, KH, ST, SY, TI, YK, HM, TY, NI, RT, NA, TA, KO), pp. 292–295.
DACDAC-2006-HuZCGC #communication #latency #synthesis
Communication latency aware low power NoC synthesis (YH, YZ, HC, RLG, CKC), pp. 574–579.
DACDAC-2006-IranliLP #mobile
Backlight dimming in power-aware mobile displays (AI, WL, MP), pp. 604–607.
DACDAC-2006-JonesHDTSFCM #automation #configuration management
An automated, reconfigurable, low-power RFID tag (AKJ, RRH, SRD, SCT, RS, JF, JTC, MHM), pp. 131–136.
DACDAC-2006-KansalHSR #network
Harvesting aware power management for sensor networks (AK, JH, MBS, VR), pp. 651–656.
DACDAC-2006-KimSKE #design #physics #standard
Physical design methodology of power gating circuits for standard-cell-based design (HOK, YS, HK, IE), pp. 109–112.
DACDAC-2006-LiLP #analysis #statistics
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions (XL, JL, LTP), pp. 103–108.
DACDAC-2006-MengSK #embedded #reduction
Leakage power reduction of embedded memories on FPGAs through location assignment (YM, TS, RK), pp. 612–617.
DACDAC-2006-PantC #grid #physics
Power grid physics and implications for CAD (SP, EC), pp. 199–204.
DACDAC-2006-PengL #constraints
Low-power repeater insertion with both delay and slew rate constraints (YP, XL), pp. 302–307.
DACDAC-2006-ShiH #challenge #design #implementation
Challenges in sleep transistor design and implementation in low-power designs (KS, DH), pp. 113–116.
DACDAC-2006-YuSH #analysis #grid #order #performance #reduction
Fast analysis of structured power grid by triangularization based structure preserving model order reduction (HY, YS, LH), pp. 205–210.
DATEDATE-2006-BalachandranBCWRNB #analysis #grid #modelling
Analysis and modeling of power grid transmission lines (JB, SB, GC, TW, WDR, BN, EB), pp. 33–38.
DATEDATE-2006-BanerjeeRMB #fine-grained #logic #synthesis #using
Low power synthesis of dynamic logic circuits using fine-grained clock gating (NB, KR, HMM, SB), pp. 862–867.
DATEDATE-2006-BudnikR #distributed #network #novel #using
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network (MMB, KR), pp. 1116–1121.
DATEDATE-2006-CarbognaniBFKF
Two-phase resonant clocking for ultra-low-power hearing aid applications (FC, FB, NF, HK, WF), pp. 73–78.
DATEDATE-2006-Chang #design
An ultra low-power TLB design (YJC), pp. 1122–1127.
DATEDATE-2006-ChenMBR #case study #design
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design (QC, SM, AB, KR), pp. 983–988.
DATEDATE-2006-El-HoiydiACCDEGGLMPPPRRRV
The ultra low-power wiseNET system (AEH, CA, RC, SC, JDD, CCE, FG, SG, EL, TM, VP, FXP, PDP, NR, AR, DR, PV), pp. 971–976.
DATEDATE-2006-GianniniNBCCDB #design #synthesis
A synthesis tool for power-efficient base-band filter design (VG, PN, FDB, JC, BC, SD, AB), pp. 162–163.
DATEDATE-2006-HuangG06a #adaptation #compilation #embedded #scalability
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities (PKH, SG), pp. 943–944.
DATEDATE-2006-KumarA
An analytical state dependent leakage power model for FPGAs (AK, MA), pp. 612–617.
DATEDATE-2006-MaciiPFADZ #design #matter #question #tool support
Low-power design tools: are EDA vendors taking this matter seriously? (EM, MP, DF, RCA, AD, RZ), p. 1227.
DATEDATE-2006-MallikSBZ #design #optimisation
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment (AM, DS, PB, HZ), pp. 618–623.
DATEDATE-2006-PaciMPB #design
Exploring “temperature-aware” design in low-power MPSoCs (GP, PM, FP, LB), pp. 838–843.
DATEDATE-2006-PaulinPLBBLLL #distributed #modelling #multi
Distributed object models for multi-processor SoC’s, with application to low-power multimedia wireless systems (PGP, CP, ML, EB, OB, DL, BL, DL), pp. 482–487.
DATEDATE-2006-RaychowdhuryPBR #case study #comparative
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies (AR, BCP, SB, KR), pp. 856–861.
DATEDATE-2006-SchusterNPF #architecture
Architectural and technology influence on the optimal total power consumption (CS, JLN, CP, PAF), pp. 989–994.
DATEDATE-2006-ViswanathAJ #automation #pipes and filters
Automatic insertion of low power annotations in RTL for pipelined microprocessors (VV, JAA, WAHJ), pp. 496–501.
DATEDATE-2006-ZhouSMS #analysis #composition #grid #scalability #using
Large power grid analysis using domain decomposition (QZ, KS, KM, DCS), pp. 27–32.
DATEDATE-DF-2006-SamaPFBR #3d #low cost #named
3dID: a low-power, low-cost hand motion capture device (MS, VP, EF, LB, BR), pp. 136–141.
ISMMISMM-2006-Mendelson #challenge #memory management
Memory management challenges in the power-aware computing era (AM), pp. 1–2.
SFMSFM-2005-AcquavivaABBBL #formal method #impact analysis #predict
A Methodology Based on Formal Methods for Predicting the Impact of Dynamic Power Management (AA, AA, MB, AB, EB, EL), pp. 155–189.
SFMSFM-2005-AcquavivaBL #standard
Dynamic Power Management Strategies Within the IEEE 802.11 Standard (AA, EB, EL), pp. 190–214.
SACSAC-2005-GriffinSC #case study #design #embedded #garbage collection #java #on the
On designing a low-power garbage collector for java embedded devices: a case study (PAG, WSa, JMC), pp. 868–873.
CGOCGO-2005-RavindranNDMSMB #compilation
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache (RAR, PDN, GSD, EDM, RMS, SAM, RBB), pp. 179–190.
DACDAC-2005-AziziKDN #design #scalability
Variations-aware low-power design with voltage scaling (NA, MMK, VD, FNN), pp. 529–534.
DACDAC-2005-BhuniaBCMR #approach #novel #reduction #synthesis #using
A novel synthesis approach for active leakage power reduction using dynamic supply gating (SB, NB, QC, HMM, KR), pp. 479–484.
DACDAC-2005-ChangS #analysis #correlation #process
Full-chip analysis of leakage power under process variations, including spatial correlations (HC, SSS), pp. 523–528.
DACDAC-2005-CheonHKRW
Power-aware placement (YC, PHH, ABK, SR, QW), pp. 795–800.
DACDAC-2005-ChoiCK #embedded
DC-DC converter-aware power management for battery-operated embedded systems (YC, NC, TK), pp. 895–900.
DACDAC-2005-Li #analysis #grid #performance #simulation
Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation (PL), pp. 664–669.
DACDAC-2005-LuoYYB #design #network #using
Low power network processor design using clock gating (YL, JY, JY, LNB), pp. 712–715.
DACDAC-2005-NedevschiPB #hardware #low cost #recognition #speech #user interface
Hardware speech recognition for user interfaces in low cost, low power devices (SN, RKP, EAB), pp. 684–689.
DACDAC-2005-PengL #named #performance #using
Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method (YP, XL), pp. 813–818.
DACDAC-2005-SaneeiAN #encoding #reduction
Sign bit reduction encoding for low power applications (MS, AAK, ZN), pp. 214–217.
DACDAC-2005-SrivastavaSASBD #correlation #estimation #parametricity #performance
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (AS, SS, KA, DS, DB, SWD), pp. 535–540.
DACDAC-2005-TangZB #library #optimisation #synthesis
Leakage power optimization with dual-Vth library in high-level synthesis (XT, HZ, PB), pp. 202–207.
DACDAC-2005-WeiR #configuration management #implementation #trade-off
Implementing low-power configurable processors: practical options and tradeoffs (JW, CR), pp. 706–711.
DATEDATE-2005-CaiL #memory management
Joint Power Management of Memory and Disk (LC, YHL), pp. 86–91.
DATEDATE-2005-Conti #analysis #architecture
SystemC Analysis of a New Dynamic Power Management Architectur (MC), pp. 177–178.
DATEDATE-2005-GhantaVPW #analysis #grid #probability #process
Stochastic Power Grid Analysis Considering Process Variations (PG, SBKV, RP, JMW), pp. 964–969.
DATEDATE-2005-HassanADE #process #reduction
Activity Packing in FPGAs for Leakage Power Reduction (HH, MA, AED, MIE), pp. 212–217.
DATEDATE-2005-IshiharaF
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors (TI, FF), pp. 358–363.
DATEDATE-2005-KitaharaKMSF #design #multi #reduction
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction (TK, NK, FM, KS, TF), pp. 646–647.
DATEDATE-2005-LiuPP #hybrid #named #performance
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power (XL, YP, MCP), pp. 1330–1335.
DATEDATE-2005-LiWYY #named #performance
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique (ML, XW, RY, XY), pp. 526–527.
DATEDATE-2005-MullerTAL #design #multi #top-down
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit (PM, AT, SMA, YL), pp. 258–263.
DATEDATE-2005-Simunic
Power Saving Techniques for Wireless LANs (TS), pp. 96–97.
DATEDATE-2005-TangWD #complexity #synthesis
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption (HT, YW, AD), pp. 264–269.
DATEDATE-2005-TiriV #constant #design #difference #logic
Design Method for Constant Power Consumption of Differential Logic Circuits (KT, IV), pp. 628–633.
DATEDATE-2005-VerleMAMA #optimisation #protocol
Low Power Oriented CMOS Circuit Optimization Protocol (AV, XM, NA, PM, DA), pp. 640–645.
DATEDATE-2005-YangVTV #automation #debugging #design #fault #modelling
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs (YSY, AGV, PJT, SV), pp. 996–1001.
DATEDATE-2005-YardiHMH #multi #quality
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing (SMY, MSH, TLM, DSH), pp. 340–345.
DATEDATE-2005-ZuberWOSH #optimisation #reduction
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization (PZ, AW, RMBdO, WS, AH), pp. 986–987.
HPCAHPCA-2005-ChenPWHP #design
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems (XC, LSP, GYW, YKH, PRP), pp. 120–131.
HPCAHPCA-2005-KondoN #clustering #performance
A Small, Fast and Low-Power Register File by Bit-Partitioning (MK, HN), pp. 40–49.
HPCAHPCA-2005-MengSK #on the #reduction
On the Limits of Leakage Power Reduction in Caches (YM, TS, RK), pp. 154–165.
HPCAHPCA-2005-VenkatesanAR #memory management
Tapping ZettaRAMTM for Low-Power Memory Systems (RKV, ASAZ, ER), pp. 83–94.
SACSAC-2004-AgostaPS #architecture #design #embedded #multi #program transformation #source code
Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems (GA, GP, CS), pp. 891–896.
SACSAC-2004-UhrigU #fine-grained #parallel #thread
Fine-grained power management for multithreaded processor cores (SU, TU), pp. 907–908.
ASPLOSASPLOS-2004-EkanayakeKM #network
An ultra low-power processor for sensor networks (VNE, CKI, RM), pp. 27–36.
DACDAC-2004-BasuLWMB #optimisation
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era (AB, SCL, VW, AM, KB), pp. 884–887.
DACDAC-2004-KouroussisAN #worst-case
Worst-case circuit delay taking into account power supply variations (DK, RA, FNN), pp. 652–657.
DACDAC-2004-LiuPP #library #question #what
Practical repeater insertion for low power: what repeater library do we need? (XL, YP, MCP), pp. 30–35.
DACDAC-2004-PantBZSP #analysis #approach #grid #probability
A stochastic approach To power grid analysis (SP, DB, VZ, SS, RP), pp. 171–176.
DACDAC-2004-ParkCYC #testing
A new state assignment technique for testing and low power (SP, SC, SY, MJC), pp. 510–513.
DACDAC-2004-SrivastavaSB #optimisation #process #statistics #using
Statistical optimization of leakage power considering process variations using dual-Vth and sizing (AS, DS, DB), pp. 773–778.
DACDAC-2004-SrivastavaSB04a #using
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (AS, DS, DB), pp. 783–787.
DACDAC-2004-WangM #constraints
Buffer sizing for clock power minimization subject to general skew constraints (KW, MMS), pp. 159–164.
DACDAC-2004-ZhaoFZSP
Optimal placement of power supply pads and pins (MZ, YF, VZ, SS, RP), pp. 165–170.
DATEDATE-DF-2004-MenichelliOBDB #architecture #design #multi
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design (FM, MO, LB, MD, LB), pp. 312–317.
DATEDATE-DF-2004-NeffeRSWRM #energy #estimation #modelling #smarttech
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards (UN, KR, CS, RW, ER, AM), pp. 300–305.
DATEDATE-DF-2004-Saul
Low Power Analogue 90 Degree Phase Shifter (PHS), pp. 28–33.
DATEDATE-v1-2004-BonhommeGGLPV #design
Design of Routing-Constrained Low Power Scan Chains (YB, PG, LG, CL, SP, AV), pp. 62–67.
DATEDATE-v1-2004-CaiL #using
Dynamic Power Management Using Data Buffers (LC, YHL), pp. 526–531.
DATEDATE-v1-2004-Cao #on the
On Transfer Function and Power Consumption Transient Response (LC), pp. 688–689.
DATEDATE-v1-2004-ChenG #adaptation #bias #low cost #performance #reduction
A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations (TWC, JG), pp. 240–245.
DATEDATE-v1-2004-ChengHP #concurrent #scalability
Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling (WCC, YH, MP), pp. 252–259.
DATEDATE-v1-2004-KretzschmarNM #why
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work (CK, AKN, DM), pp. 512–517.
DATEDATE-v1-2004-KuoHW #composition #design
Decomposition of Instruction Decoder for Low Power Design (WAK, TH, ACHW), pp. 664–665.
DATEDATE-v1-2004-LaurentJSM #analysis #approach #functional #modelling #performance
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors (JL, NJ, ES, EM), pp. 666–667.
DATEDATE-v1-2004-LeeDBS
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization (DL, HD, DB, DS), pp. 494–499.
DATEDATE-v1-2004-NikitovicB #mobile
A Low Power Strategy for Future Mobile Terminals (MN, MB), pp. 702–703.
DATEDATE-v1-2004-PiguetGHOS #logic
Extremely Low-Power Logic (CP, JG, CH, IO, US), pp. 656–663.
DATEDATE-v1-2004-RenKM #adaptation
Hierarchical Adaptive Dynamic Power Management (ZR, BHK, RM), pp. 136–141.
DATEDATE-v1-2004-SinanogluO
Scan Power Minimization through Stimulus and Response Transformations (OS, AO), pp. 404–409.
DATEDATE-v1-2004-SrivastavaSB #concurrent #design
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design (AS, DS, DB), pp. 718–719.
DATEDATE-v1-2004-WangH #clustering #memory management #multi #scheduling
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks (ZW, XSH), pp. 312–317.
DATEDATE-v1-2004-WongT #configuration management #encoding
Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus (SKW, CYT), pp. 130–135.
DATEDATE-v2-2004-AcquavivaLB #network
Power-Aware Network Swapping for Wireless Palmtop PCs (AA, EL, AB), pp. 858–863.
DATEDATE-v2-2004-LiverisB #design #interface #synthesis
Power Aware Interface Synthesis for Bus-Based SoC Design (NDL, PB), pp. 864–869.
DATEDATE-v2-2004-NaculG #configuration management
Dynamic Voltage and Cache Reconfiguration for Low Power (ACN, TG), pp. 1376–1379.
DATEDATE-v2-2004-TirumurtiKSC #approach #modelling
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit (CT, SK, SSK, YSC), pp. 1078–1083.
DATEDATE-v2-2004-VazquezG #fault #monitoring
Power Supply Noise Monitor for Signal Integrity Faults (JRV, JPdG), pp. 1406–1407.
HPCAHPCA-2004-GniadyHL
Program Counter Based Techniques for Dynamic Power Management (CG, YCH, YHL), pp. 24–35.
HPCAHPCA-2004-ZhuDDLZC #energy #using
Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management (QZ, FMD, CFD, ZL, YZ, PC), pp. 118–129.
LCTESLCTES-2004-ZhuangP #embedded
Power-efficient prefetching via bit-differential offset assignment on embedded processors (XZ, SP), pp. 67–77.
DATEDATE-2005-Hillman04 #reduction #using
Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm (DH), pp. 240–246.
DATEDATE-2005-SandnerCSHK04
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS (CS, MC, AS, TH, FK), pp. 223–226.
DACDAC-2003-BashirullahLC #adaptation #design
Low-power design methodology for an on-chip bus with adaptive bandwidth capability (RB, WL, RKCI), pp. 628–633.
DACDAC-2003-FerzliN #estimation #grid #process #statistics
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations (IAF, FNN), pp. 856–859.
DACDAC-2003-KouroussisN #grid #independence #verification
A static pattern-independent technique for power grid voltage integrity verification (DK, FNN), pp. 99–104.
DACDAC-2003-LiXC #architecture #modelling #optimisation #scalability
Scalable modeling and optimization of mode transitions based on decoupled power management architecture (DL, QX, PHC), pp. 119–124.
DACDAC-2003-MoreshetB #design #queue
Power-aware issue queue design for speculative instructions (TM, RIB), pp. 634–637.
DACDAC-2003-ShiG #hybrid #performance
Hybrid hierarchical timing closure methodology for a high performance and low power DSP (KS, GG), pp. 850–855.
DACDAC-2003-SuAN #algebra #grid #multi #reduction
Power grid reduction based on algebraic multigrid principles (HS, EA, SRN), pp. 109–112.
DACDAC-2003-WangM #multi #network #optimisation #using
On-chip power supply network optimization using multigrid-based technique (KW, MMS), pp. 113–118.
DATEDATE-2003-BeeckGBMCD #data transformation #implementation #realtime
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor (POdB, CG, EB, MM, FC, GD), pp. 11144–11145.
DATEDATE-2003-ChengP #encoding #interface #visual notation
Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface (WCC, MP), pp. 10694–10699.
DATEDATE-2003-ChiouBR #multi #synthesis
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications (LYC, SB, KR), pp. 10096–10103.
DATEDATE-2003-ChooMR #architecture #named #synthesis
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters (HC, KM, KR), pp. 10700–10705.
DATEDATE-2003-HagaRBM #functional
Dynamic Functional Unit Assignment for Low Power (SH, NR, RB, DM), pp. 11052–11057.
DATEDATE-2003-LeeC #3d #grid #linear #simulation
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method (YML, CCPC), pp. 11020–11025.
DATEDATE-2003-LeeHH #composition #design #finite #state machine
Decomposition of Extended Finite State Machine for Low Power Design (ML, TH, SYH), pp. 11152–11153.
DATEDATE-2003-MamidipakaD #architecture #embedded #memory management #stack
On-chip Stack Based Memory Organization for Low Power Embedded Architectures (MM, NDD), pp. 11082–11089.
DATEDATE-2003-NicolaescuVN #embedded
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors (DN, AVV, AN), pp. 11064–11069.
DATEDATE-2003-SirisantanaR #logic
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies (NS, KR), pp. 11160–11161.
DATEDATE-2003-WuAE #embedded #graph #scheduling #synthesis
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems (DW, BMAH, PE), pp. 10090–10095.
HPCAHPCA-2003-AragonGG
Power-Aware Control Speculation through Selective Throttling (JLA, JG, AG), pp. 103–112.
TACASTACAS-2003-SokolskyPLC #analysis #modelling
Modeling and Analysis of Power-Aware Systems (OS, AP, IL, KC), pp. 409–425.
SIGMODSIGMOD-2002-MaddenH #network #query
Distributing queries over low-power wireless sensor networks (SM, JMH), p. 622.
DACDAC-2002-AgarwalLR #named
DRG-cache: a data retention gated-ground cache for low power (AA, HL, KR), pp. 473–478.
DACDAC-2002-AnisMEA #automation #clustering #performance #reduction #using
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique (MA, MM, MIE, SA), pp. 480–485.
DACDAC-2002-CaoLCC #delivery #megamodelling #named
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery (YC, YML, THC, CCPC), pp. 379–384.
DACDAC-2002-KangSC #synthesis
An optimal voltage synthesis technique for a power-efficient satellite application (DIK, JS, SPC), pp. 492–497.
DACDAC-2002-LahiriDR #architecture #communication #design #performance
Communication architecture based power management for battery efficient system design (KL, SD, AR), pp. 691–696.
DACDAC-2002-LiuP #design
Design of a high-throughput low-power IS95 Viterbi decoder (XL, MCP), pp. 263–268.
DACDAC-2002-SteyaertV #named #paradigm #question
CMOS: a paradigm for low power wireless? (MS, PJV), pp. 836–841.
DACDAC-2002-YeMB #analysis #network
Analysis of power consumption on switch fabrics in network routers (TTY, GDM, LB), pp. 524–529.
DATEDATE-2002-AghaghiriPF #encoding #multi
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses (YA, MP, FF), p. 1102.
DATEDATE-2002-BertozziBM #encoding #fault
Low Power Error Resilient Encoding for On-Chip Data Buses (DB, LB, GDM), pp. 102–109.
DATEDATE-2002-BrandtnerW #network #simulation
Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network (TB, RW), pp. 1028–1032.
DATEDATE-2002-BrockELSDBOK #design
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs (KB, CE, RL, US, AD, JB, DO, MK), p. 538.
DATEDATE-2002-DuarteVI
A Complete Phase-Locked Loop Power Consumption Model (DD, NV, MJI), p. 1108.
DATEDATE-2002-HuVKI
Power-Efficient Trace Caches (JSH, NV, MTK, MJI), p. 1091.
DATEDATE-2002-IraniGS #analysis #multi
Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States (SI, RKG, SKS), pp. 117–123.
DATEDATE-2002-KimR #reduction #scalability
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction (CHK, KR), pp. 163–167.
DATEDATE-2002-MartinezAQSK #encoding #implementation
An Encoding Technique for Low Power CMOS Implementations of Controllers (MM, MJA, JMQ, HS, MK), p. 1083.
DATEDATE-2002-MetraSRF #online #self #testing
Self-Checking Scheme for the On-Line Testing of Power Supply Noise (CM, LS, BR, MF), pp. 832–836.
DATEDATE-2002-OrtizKG #estimation
Estimation of Power Consumption in Encoded Data Buses (AGO, LDK, MG), p. 1103.
DATEDATE-2002-PeymandoustSM #algebra #embedded #optimisation #using
Low Power Embedded Software Optimization Using Symbolic Algebra (AP, TS, GDM), pp. 1052–1058.
DATEDATE-2002-SimunicB #network
Managing Power Consumption in Networks on Chip (TS, SPB), pp. 110–116.
DATEDATE-2002-TangGN #embedded
Power Savings in Embedded Processors through Decode Filer Cache (WT, RKG, AN), pp. 443–448.
HPCAHPCA-2002-GrochowskiAT #architecture #simulation
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation (EG, DA, VT), pp. 7–16.
DACDAC-2001-BaiBH #analysis
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits (GB, SB, INH), pp. 295–300.
DACDAC-2001-ChandraC #testing
Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip (AC, KC), pp. 166–169.
DACDAC-2001-ChenC #analysis #grid #performance #scalability
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods (THC, CCPC), pp. 559–562.
DACDAC-2001-HenkelL #adaptation #design #named
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs (JH, HL), pp. 744–749.
DACDAC-2001-LiuCBK #constraints #embedded #scheduling
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems (JL, PHC, NB, FJK), pp. 840–845.
DACDAC-2001-QiuWP #mobile #multi
Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service (QQ, QW, MP), pp. 834–839.
DACDAC-2001-ShinS #design
Coupling-Driven Bus Design for Low-Power Application-Specific Systems (YS, TS), pp. 750–753.
DACDAC-2001-SimunicBAGM #scalability
Dynamic Voltage Scaling and Power Management for Portable Systems (TS, LB, AA, PWG, GDM), pp. 524–529.
DATEDATE-2001-AcquavivaBR #adaptation #algorithm #multi #streaming
An adaptive algorithm for low-power streaming multimedia processing (AA, LB, BR), pp. 273–279.
DATEDATE-2001-Chen #grid #on the
On the impact of on-chip inductance on signal nets under the influence of power grid noise (TC), pp. 451–459.
DATEDATE-2001-DielissenMBHSHW
Power-efficient layered turbo decoder processor (JD, JLvM, MB, FH, SS, JH, AvdW), pp. 246–251.
DATEDATE-2001-GarnicaLH #pseudo
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits (OG, JL, RH), p. 810.
DATEDATE-2001-GerfersM #design
A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters (FG, YM), pp. 361–369.
DATEDATE-2001-GrunDN #embedded #memory management
Access pattern based local memory customization for low power embedded systems (PG, NDD, AN), pp. 778–784.
DATEDATE-2001-IyerM #architecture #scalability
Power aware microarchitecture resource scaling (AI, DM), pp. 190–196.
DATEDATE-2001-NaiduJ
Minimizing stand-by leakage power in static CMOS circuits (SRN, ETAFJ), pp. 370–376.
DATEDATE-2001-PiguetRO
Low-power systems on chips (SOCs) (CP, MR, TJFO), p. 488.
DATEDATE-2001-WormLW #architecture #design #performance
Design of low-power high-speed maximum a priori decoder architectures (AW, HL, NW), pp. 258–267.
LCTESLCTES-OM-2001-KangCS #design #distributed #realtime #synthesis
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems (DIK, SPC, JS), pp. 20–28.
LCTESLCTES-OM-2001-KimH #embedded #hybrid #realtime #runtime #scalability
Hybrid Run-time Power Management Technique for Real-time Embedded System with Voltage Scalable Processor (MK, SH), pp. 11–19.
SOSPSOSP-2001-PillaiS #embedded #operating system #realtime #scalability
Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems (PP, KGS), pp. 89–102.
ASPLOSASPLOS-2000-LebeckFZE
Power Aware Page Allocation (ARL, XF, HZ, CSE), pp. 105–116.
DACDAC-2000-ChangKC #encoding #memory management
Bus encoding for low-power high-performance memory systems (NC, KK, JC), pp. 800–805.
DACDAC-2000-GebotysGW #architecture
Power minimization derived from architectural-usage of VLIW processors (CHG, RJG, SW), pp. 308–311.
DACDAC-2000-HeijningenBDEB #generative #simulation
High-level simulation of substrate noise generation including power supply noise coupling (MvH, MB, SD, ME, IB), pp. 446–451.
DACDAC-2000-LeeS #realtime #runtime
Run-time voltage hopping for low-power real-time systems (SL, TS), pp. 806–809.
DACDAC-2000-LekatsasHW #design #embedded
Code compression for low power embedded system design (HL, JH, WW), pp. 294–299.
DACDAC-2000-NassifK #grid #performance #simulation
Fast power grid simulation (SRN, JNK), pp. 156–161.
DACDAC-2000-QiuWP #petri net #probability #using
Dynamic power management of complex systems using generalized stochastic Petri nets (QQ, QW, MP), pp. 352–356.
DACDAC-2000-RaoN #using
Power minimization using control generated clocks (MSR, SKN), pp. 794–799.
DACDAC-2000-UmKL #fine-grained #optimisation #synthesis
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis (JU, TK, CLL), pp. 98–103.
DACDAC-2000-ZhouW #composition
Optimal low power X OR gate decomposition (HZ, DFW), pp. 104–107.
DATEDATE-2000-GizopoulosKPPZ #effectiveness
Effective Low Power BIST for Datapaths (DG, NK, MP, AMP, YZ), p. 757.
DATEDATE-2000-KruseSJSN #bound #constraints #data flow #graph
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints (LK, ES, GJ, AS, WN), p. 737.
DATEDATE-2000-LuCSMB #algorithm #comparison
Quantitative Comparison of Power Management Algorithms (YHL, EYC, TS, GDM, LB), pp. 20–26.
DATEDATE-2000-MunchWWMS #automation
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths (MM, NW, BW, RM, JS), pp. 624–631.
DATEDATE-2000-NicoliciA #clustering #multi
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits (NN, BMAH), pp. 715–722.
DATEDATE-2000-RamanathanG #algorithm #online
System Level Online Power Management Algorithms (DR, RKG), pp. 606–611.
DATEDATE-2000-SimunicBGM
Dynamic Power Management of Laptop Hard Disk (TS, LB, PWG, GDM), p. 736.
HPDCHPDC-2000-HinkeN #data mining #grid #mining
Data Mining on NASA’s Information Power Grid (THH, JN), pp. 292–293.
LCTESLCTES-2000-ChildersN #memory management #order #transaction
Reordering Memory Bus Transactions for Reduced Power Consumption (BRC, TN), pp. 146–161.
SACSAC-1999-RudenkoRPK #framework
The Remote Processing Framework for Portable Computer Power Saving (AR, PLR, GJP, GHK), pp. 365–372.
DACDAC-1999-BeniniMMPS #communication #interface #synthesis
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses (LB, AM, EM, MP, RS), pp. 128–133.
DACDAC-1999-ErcegovacKP #behaviour #multi #optimisation #precise #synthesis #using
Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic (MDE, DK, MP), pp. 568–573.
DACDAC-1999-HashimotoOT #design #reduction
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (MH, HO, KT), pp. 446–451.
DACDAC-1999-HemaniMKPONOEL #design #using
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style (AH, TM, SK, AP, TO, PN, , PE, DL), pp. 873–878.
DACDAC-1999-Henkel #approach #clustering #embedded #hardware
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems (JH), pp. 122–127.
DACDAC-1999-JiangC #analysis #performance
Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices (YMJ, KTC), pp. 760–765.
DACDAC-1999-PatraN #automation #synthesis
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits (PP, UN), pp. 379–384.
DACDAC-1999-QiuP #markov #process
Dynamic Power Management Based on Continuous-Time Markov Decision Processes (QQ, MP), pp. 555–561.
DACDAC-1999-ShiueC #embedded #memory management
Memory Exploration for Low Power, Embedded Systems (WTS, CC), pp. 140–145.
DACDAC-1999-SirichotiyakulEOZDPB
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.
DACDAC-1999-SundararajanP #synthesis #using
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages (VS, KKP), pp. 72–75.
DACDAC-1999-WeiCRYD #design
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (LW, ZC, KR, YY, VD), pp. 430–435.
DATEDATE-1999-BeniniMMMPS
Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.
DATEDATE-1999-ChungBBM
Dynamic Power Management for non-stationary service requests (EYC, LB, AB, GDM), pp. 77–81.
DATEDATE-1999-HwangVH #clustering #functional
FSMD Functional Partitioning for Low Power (EH, FV, YCH), pp. 22–27.
DATEDATE-1999-KimKHL #logic #synthesis
Logic Transformation for Low Power Synthesis (KWK, SMK, TH, CLL), pp. 158–162.
DATEDATE-1999-NoethK #encoding
Spanning Tree-based State Encoding for Low Power Dissipation (WN, RK), pp. 168–174.
HPDCHPDC-1999-JohnstonGN #aspect-oriented #grid
Grids as Production Computing Environments: The Engineering Aspects of NASA’s Information Power Grid (WEJ, DG, BN), pp. 197–204.
DACDAC-1998-HwangCH #approach #design #re-engineering #using
A Re-engineering Approach to Low Power FPGA Design Using SPFD (JMH, FYC, TH), pp. 722–725.
DACDAC-1998-LakshminarayanaJ98a #behaviour #synthesis
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions (GL, NKJ), pp. 439–444.
DACDAC-1998-MonteiroO #composition #finite #state machine
Finite State Machine Decomposition For Low Power (JCM, ALO), pp. 758–763.
DACDAC-1998-PaleologoBBM #optimisation #policy
Policy Optimization for Dynamic Power Management (GAP, LB, AB, GDM), pp. 182–187.
DACDAC-1998-UsamiIIKTHATK #design #scalability
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques (KU, MI, TI, MK, MT, MH, HA, TT, TK), pp. 483–488.
DATEDATE-1998-KhouriLJ #control flow #named #synthesis
IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits (KSK, GL, NKJ), pp. 848–854.
DATEDATE-1998-RoyAB #clustering #named
PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions (SR, HA, PB), pp. 967–968.
DACDAC-1997-ChenHL #approach #design #re-engineering
Low Power FPGA Design — A Re-engineering Approach (CSC, TH, CLL), pp. 656–661.
DACDAC-1997-ChenL #analysis #design
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design (HHC, DDL), pp. 638–643.
DACDAC-1997-Frenkil #design #tool support
Tools and Methodologies for Low Power Design (JF), pp. 76–81.
DACDAC-1997-KirovskiP #realtime #synthesis
System-Level Synthesis of Low-Power Hard Real-Time Systems (DK, MP), pp. 697–702.
DACDAC-1997-MurofushiIMM #layout
Layout Driven Re-synthesis for Low Power Consumption LSIs (MM, TI, MM, TM), pp. 666–669.
DACDAC-1997-PandaN #synthesis
Technology-Dependent Transformations for Low-Power Synthesis (RP, FNN), pp. 650–655.
DACDAC-1997-PantDC #energy #logic #network #optimisation #random
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks (PP, VD, AC), pp. 403–408.
DACDAC-1997-RaghunathanDJW #control flow #design
Power Management Techniques for Control-Flow Intensive Designs (AR, SD, NKJ, KW), pp. 429–434.
DACDAC-1997-TsuiCWDP #design #estimation #framework #video
A Power Estimation Framework for Designing Low Power Portable Video Applications (CYT, KKC, QW, CSD, MP), pp. 421–424.
DATEEDTC-1997-SurtiCT #automaton #design #encoding #using
Low power FSM design using Huffman-style encoding (PS, LFC, AT), pp. 521–525.
DACDAC-1996-ChenS #algorithm
An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing (DSC, MS), pp. 783–788.
DACDAC-1996-MonteiroDAM #scheduling
Scheduling Techniques to Enable Power Management (JM, SD, PA, AM), pp. 349–352.
DACDAC-1996-PapachristouSN #design #effectiveness #multi
An Effective Power Management Scheme for RTL Design Based on Multiple Clocks (CAP, MS, MN), pp. 337–342.
DACDAC-1996-Wolfe
Opportunities and Obstacles in Low-Power System-Level CAD (AW), pp. 15–20.
DACDAC-1996-XiD #design
Useful-Skew Clock Routing With Gate Sizing for Low Power Design (JGX, WWMD), pp. 383–388.
DACDAC-1995-ChangP
Register Allocation and Binding for Low Power (JMC, MP), pp. 29–35.
DACDAC-1995-DevadasM #optimisation #overview
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits (SD, SM), pp. 242–247.
DACDAC-1995-ImanP #logic
Logic Extraction and Factorization for Low Power (SI, MP), pp. 248–253.
DACDAC-1995-LavagnoMSS #design #synthesis
Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool (LL, PCM, AS, ALSV), pp. 254–260.
DACDAC-1995-MartinK #behaviour #named #optimisation
Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level (RSM, JPK), pp. 42–47.
DACDAC-1995-XiD #process
Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution (JGX, WWMD), pp. 491–496.
DACDAC-1994-SchobingerN #design
Low Power CMOS Design Strategies (MS, TGN), pp. 594–595.
DATEEDAC-1994-AkitaA #logic #probability
A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability (JA, KA), pp. 420–424.
DATEEDAC-1994-KarkkainenTW #bound #monitoring #testing
Boundary Scan Testing Combined with Power Supply Current Monitoring (MK, KT, MW), pp. 232–235.
DACDAC-1993-TsuiPD #composition
Technology Decomposition and Mapping Targeting Low Power Dissipation (CYT, MP, AMD), pp. 68–73.
DACDAC-1988-StarkH #network #using
Analyzing CMOS Power Supply Networks Using Ariel (DS, MH), pp. 460–464.
DACDAC-1986-DeJesusCW #layout #named
PEARL: an expert system for power supply layout (EJD, JPC, CRW), pp. 615–621.
DACDAC-1981-RothermelM #layout
Computation of power supply nets in VLSI layout (HJR, DAM), pp. 37–42.

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