A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache
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Kyungsu Kang, Sangho Park, Jong-Bae Lee, Luca Benini, Giovanni De Micheli
A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache
DATE, 2016.

DATE 2016
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@inproceedings{DATE-2016-KangPLBM,
	author        = "Kyungsu Kang and Sangho Park and Jong-Bae Lee and Luca Benini and Giovanni De Micheli",
	booktitle     = "{Proceedings of the 20th Conference and Exhibition on Design, Automation and Test in Europe}",
	ee            = "http://ieeexplore.ieee.org/document/7459541/",
	isbn          = "978-3-9815-3707-9",
	pages         = "1465--1468",
	publisher     = "{IEEE}",
	title         = "{A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache}",
	year          = 2016,
}


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