BibSLEIGH — Proceedings of the 20th Conference and Exhibition on Design, Automation and Test in Europe

Luca Fanucci, Jürgen Teich
Proceedings of the 20th Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2016.

SYS

@proceedings{DATE-2016,
	editor        = "Luca Fanucci and Jürgen Teich",
	ee            = "https://ieeexplore.ieee.org/xpl/conhome/7454909/proceeding",
	isbn          = "978-3-9815-3707-9",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 20th Conference and Exhibition on Design, Automation and Test in Europe}",
	year          = 2016,
}

Contents (307 items)

DATE-2016-HenkelPKKRS: Towards performance and reliability-efficient computing in the dark silicon era (JH, SP, HK, FK, SR, MS0), pp. 1–6.
DATE-2016-PahlevanPZRZBVA: Towards near-threshold server processors (AP, JP, APZ, DR, MZ, AB, PGDV, DA, LB, BF), pp. 7–12.
DATE-2016-PerriconeHNN: Can beyond-CMOS devices illuminate dark silicon? (RP, XSH, JN, MTN), pp. 13–18.
DATE-2016-VatanparvarF: OTEM: Optimized Thermal and Energy Management for Hybrid Electrical Energy Storage in Electric Vehicles (KV, MAAF), pp. 19–24.
DATE-2016-KehrPQBSACS: Supertask: Maximizing runnable-level parallelism in AUTOSAR applications (SK, MP, EQ, BB, JBS, JA, FJC, GS), pp. 25–30.
DATE-2016-ThieleE: Formal analysis based evaluation of software defined networking for time-sensitive Ethernet (DT, RE), pp. 31–36.
DATE-2016-ShreejithAF: Accelerated Artificial Neural Networks on FPGA for fault detection in automotive systems (SS, BA, SAF), pp. 37–42.
DATE-2016-KuangY: Optimization for Multiple Patterning Lithography with cutting process and beyond (JK0, EFYY), pp. 43–48.
DATE-2016-Awad0K: A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation (AA0, AT0, CK), pp. 49–54.
DATE-2016-ChungSS: Redundant via insertion in directed self-assembly lithography (WC, SS, YS), pp. 55–60.
DATE-2016-HanKL: Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking (KH, ABK, JL), pp. 61–66.
DATE-2016-CuiZH: A discrete thermal controller for chip-multiprocessors (YC, WZ0, BH), pp. 67–72.
DATE-2016-HollisK: Swallow: Building an energy-transparent many-core embedded real-time system (SJH, SK), pp. 73–78.
DATE-2016-ChenTLWH: A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements (YHC, YLT, YYL, ACHW, TH), pp. 79–84.
DATE-2016-LiL: Efficient kernel management on GPUs (XL, YL0), pp. 85–90.
DATE-2016-HardyPS: Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults (DH, IP, YS), pp. 91–96.
DATE-2016-Al-bayatiCMZ: A four-mode model for efficient fault-tolerant mixed-criticality systems (ZAb, JC, BHM, HZ), pp. 97–102.
DATE-2016-RamboSE: Providing formal latency guarantees for ARQ-based protocols in Networks-on-Chip (EAR, SS, RE), pp. 103–108.
DATE-2016-LiuNMB: Achieving 100% cell-aware coverage by design (ZL0, BN, SM, RD(B), pp. 109–114.
DATE-2016-NikdastNTL: Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects (MN, GN, JT, OLL), pp. 115–120.
DATE-2016-LiaoTZSZ0: Efficient spatial variation modeling via robust dictionary learning (CL, JT, XZ0, YS, DZ, XL0), pp. 121–126.
DATE-2016-YangRMDV: TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware (BY0, VR, NM, WD, IV), pp. 127–132.
DATE-2016-LecomteFM: On-chip fingerprinting of IC topology for integrity verification (ML, JJAF, PM), pp. 133–138.
DATE-2016-YasinSRS: Activation of logic encrypted chips: Pre-test or post-test? (MY, SMS, JR, OS), pp. 139–144.
DATE-2016-SarwarVRR: Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing (SSS, SV, AR, KR0), pp. 145–150.
DATE-2016-SrinivasanWSJR: Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks (GS, PW, SSS, AJ, KR0), pp. 151–156.
DATE-2016-JuKK: Network delay-aware energy management for mobile systems (MJ, HK, SK), pp. 157–162.
DATE-2016-ParkWKPC: Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs (SP, AW, UK, LSP, APC), pp. 163–168.
DATE-2016-TrommerHBMWRV: Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits (JT, AH, TB, TM, WMW, MR, MV), pp. 169–174.
DATE-2016-AmaruGW: Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking (LGA, PEG, RW, GDM), pp. 175–180.
DATE-2016-ChoiKH: Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems (JC, DK, SH), pp. 181–186.
DATE-2016-ThieleE16a: Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper (DT, RE), pp. 187–192.
DATE-2016-BiondiB: Real-time analysis of engine control applications with speed estimation (AB, GCB), pp. 193–198.
DATE-2016-LiM: Trace-based analysis methodology of program flash contention in embedded multicore systems (LL, AM), pp. 199–204.
DATE-2016-GebregiorgisKOB: A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing (AG, SK, FO, RB, MBT), pp. 205–210.
DATE-2016-HuangLW: Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault (HMH, YL, CHPW), pp. 211–216.
DATE-2016-RieraCA0: A detailed methodology to compute Soft Error Rates in advanced technologies (MR, RC, JA, AG0), pp. 217–222.
DATE-2016-UnutulmazHEMKN: Analysis of NBTI effects on high frequency digital circuits (AU, DH, RE, MM, BK, WN), pp. 223–228.
DATE-2016-HuangHBMK: A scalable lane detection algorithm on COTSs with OpenCL (KH0, BH, JB, NM, AK), pp. 229–232.
DATE-2016-HospachMRB: Simulation of falling rain for robustness testing of video-based surround sensing systems (DH, SM, WR, OB0), pp. 233–236.
DATE-2016-SakumotoT: Proposal for fast directional energy interchange used in MCMC-based autonomous decentralized mechanism toward resilient microgrid (YS, IT), pp. 237–240.
DATE-2016-IharaH0K: Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern (TI, TH, AT0, CK), pp. 241–244.
DATE-2016-LuJLZCLL: Practical ILP-based routing of standard cells (HJL, EJJ, AL, YTZ, YHC, CHL, RBL), pp. 245–248.
DATE-2016-ShiDL: A procedure for improving the distribution of congestion in global routing (DS, AD, JTL), pp. 249–252.
DATE-2016-JainPS: Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network (RJ0, PRP, SS), pp. 253–256.
DATE-2016-AbdullahL0: Improving performance by monitoring while maintaining worst-case guarantees (SMJA, KL, WY0), pp. 257–260.
DATE-2016-BishnoiOT: Fault Tolerant Non-Volatile spintronic flip-flop (RB, FO, MBT), pp. 261–264.
DATE-2016-MoursyZITTPSSGA: Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs (YM, HZ, RI, PT, DMT, GP, ES, AS, TG, HA), pp. 265–268.
DATE-2016-LiuZMLJ: HPAZ: A high-throughput pipeline architecture of ZUC in hardware (ZL, QZ, CM, CL, JJ), pp. 269–272.
DATE-2016-VatajeluNP: Towards a highly reliable SRAM-based PUFs (EIV, GDN, PP), pp. 273–276.
DATE-2016-ZhangYPB: Current based PUF exploiting random variations in SRAM cells (FZ, SY, JP, SB), pp. 277–280.
DATE-2016-NaM: Behavioral modeling of timing slack variation in digital circuits due to power supply noise (TN, SM), pp. 281–284.
DATE-2016-LinPCFC: Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system (PCL, YHP, YHC, SYF, CCPC), pp. 285–288.
DATE-2016-FusellaC: PhoNoCMap: An application mapping tool for photonic networks-on-chip (EF, AC), pp. 289–292.
DATE-2016-Pathan: Design of an efficient ready queue for earliest-deadline-first (EDF) scheduler (RMP), pp. 293–296.
DATE-2016-KoppaetzkyMEHN: RT level timing modeling for aging prediction (NK, MM, RE, DH, WN), pp. 297–300.
DATE-2016-TasicDJMBP: Fast time-domain simulation for reliable fault detection (BT, JJD, RJ, EJWtM, TGJB, RP), pp. 301–306.
DATE-2016-SchoenmakerMST: Holistic coupled field and circuit simulation (WS, PM, CS, CT), pp. 307–312.
DATE-2016-BanagaayaFSMWGB: Model Order Reduction for nanoelectronics coupled problems with many inputs (NB, LF, WS, PM, AW, RG, PB), pp. 313–318.
DATE-2016-PutekMPMGSDW: Shape optimization of a power MOS device under uncertainties (PP, PM, RP, EJWtM, MG, WS, FD, AW), pp. 319–324.
DATE-2016-GuillenSS: Practical evaluation of code injection in encrypted firmware updates (OMG, DS, GS), pp. 325–330.
DATE-2016-LeeLHHP: Integration of ROP/JOP monitoring IPs in an ARM-based SoC (YL, JL, IH, DH, YP), pp. 331–336.
DATE-2016-SubramanyanMKMF: Verifying information flow properties of firmware using symbolic execution (PS, SM, HK, AM, JMF), pp. 337–342.
DATE-2016-PagliariPM: Low-overhead adaptive constrast enhancement and power reduction for OLEDs (DJP, MP, EM), pp. 343–348.
DATE-2016-GomezSMBT: Dynamic energy burst scaling for transiently powered systems (AG0, LS, MM, LB, LT), pp. 349–354.
DATE-2016-OleticBMFB: Low-power multichannel spectro-temporal feature extraction circuit for audio pattern wake-up (DO, VB, MM, NF, LB), pp. 355–360.
DATE-2016-GuptaMVAA: 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications (NG, AM, AV, AA, CA), pp. 361–366.
DATE-2016-YinSNH: Design of latches and flip-flops using emerging tunneling devices (XY, BS, MTN, XSH), pp. 367–372.
DATE-2016-ImaniPR: MASC: Ultra-low energy multiple-access single-charge TCAM for approximate computing (MI, SP, TSR), pp. 373–378.
DATE-2016-PathaniaVSMH: Distributed fair scheduling for many-cores (AP, VV, MS0, TM, JH), pp. 379–384.
DATE-2016-LampkaF: Keep it slow and in time: Online DVFS with hard real-time workloads (KL, BF), pp. 385–390.
DATE-2016-DiSWX: Exploiting process variation for retention induced refresh minimization on flash memory (YD, LS, KW0, CJX), pp. 391–396.
DATE-2016-PassosGRCF: Accurate synthesis of integrated RF passive components using surrogate models (FP, RGE, ER, RCL, FVF), pp. 397–402.
DATE-2016-MukherjeePSCH: Implementation and quality testing for compact models implemented in Verilog-A (AM, AP, MS, DC, ZH), pp. 403–408.
DATE-2016-WangGTL: Multi-harmonic nonlinear modeling of low-power PWM DC-DC converters operating in CCM and DCM (YW, DG, DAT, PL0), pp. 409–414.
DATE-2016-HerrmannU: Availability and interpretability of optimal control for criticality estimation in vehicle active safety (SH, WU), pp. 415–420.
DATE-2016-AscoliTCSW: Fading memory effects in a memristor for Cellular Nanoscale Network applications (AA, RT, LOC, JPS, RSW), pp. 421–425.
DATE-2016-VentraT: Digital Memcomputing Machines (MDV, FLT), p. 426.
DATE-2016-GaillardonASLWC: The Programmable Logic-in-Memory (PLiM) computer (PEG, LGA, AS, EL, RW, AC, GDM), pp. 427–432.
DATE-2016-LiuYZH: Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits (DL, CY, XZ, DEH), pp. 433–438.
DATE-2016-El-BazeRM: A fully-digital EM pulse detector (DEB, JBR, PM), pp. 439–444.
DATE-2016-AnaniadisPHBML: On the development of a new countermeasure based on a laser attack RTL fault model (CA, AP, DH, VB, PM, RL), pp. 445–450.
DATE-2016-ZhangLGG: Multi-story power distribution networks for GPUs (QZ, LL, MG, PG), pp. 451–456.
DATE-2016-ShafaeiP: Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques (AS, MP), pp. 457–462.
DATE-2016-KimHCST: Learning-based dynamic reliability management for dark silicon processor considering EM effects (TK0, XH0, HBC, VS, SXDT), pp. 463–468.
DATE-2016-XiaLTGYHCYCW0Y: MNSIM: Simulation platform for memristor-based neuromorphic computing system (LX, BL, TT, PG, XY, WH, PYC, SY, YC0, YW0, YX0, HY), pp. 469–474.
DATE-2016-PandaSR: Conditional Deep Learning for energy-efficient and enhanced pattern recognition (PP, AS, KR0), pp. 475–480.
DATE-2016-ZhangS: Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics (SZ, NRS), pp. 481–486.
DATE-2016-VentrouxS: A new parallel SystemC kernel leveraging manycore architectures (NV, TS), pp. 487–492.
DATE-2016-WeinstockLAPH: SystemC-link: Parallel SystemC simulation using time-decoupled segments (JHW, RL, GA, DP, AH0), pp. 493–498.
DATE-2016-GilR: Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation (LG, MR), pp. 499–504.
DATE-2016-DimakosSSMF: Built-in test of millimeter-Wave circuits based on non-intrusive sensors (AD, HGDS, AS, SM, EdF), pp. 505–510.
DATE-2016-KimLCKKDC: Adaptive delay monitoring for wide voltage-range operation (JK, GL, KC, YK, WK, KTD, JYC), pp. 511–516.
DATE-2016-HossainINA: Analytical design optimization of sub-ranging ADC based on stochastic comparator (MMH, TI, TN, KA), pp. 517–522.
DATE-2016-StuhringEF: Analyzing the impact of injected sensor data on an Advanced Driver Assistance System using the OP2TIMUS prototyping platform (AS, GE, SBF), pp. 523–526.
DATE-2016-FernSKC: Hardware Trojans in incompletely specified on-chip bus systems (NF, IS, ÇKK, KTC), pp. 527–530.
DATE-2016-SozzoDTMSB: Workload-aware power optimization strategy for asymmetric multiprocessors (EDS, GCD, EMGT, AM, MDS, CB), pp. 531–534.
DATE-2016-DasMA: The slowdown or race-to-idle question: Workload-aware energy optimization of SMT multicore platforms under process variation (AD0, GVM, BMAH), pp. 535–538.
DATE-2016-TrompoukiK: Towards general purpose computations on low-end mobile GPUs (MMT, LK), pp. 539–542.
DATE-2016-AvvaruZSLKP: Estimating delay differences of arbiter PUFs using silicon data (SVSA, CZ, SS, YL, CHK, KKP), pp. 543–546.
DATE-2016-LacrucheBDRK: On the use of Forward Body Biasing to decrease the repeatability of laser-induced faults (ML, NBB, JMD, JBR, EK), pp. 547–550.
DATE-2016-YechangunjaSKTM: Sequential analysis driven reset optimization to improve power, area and routability (SY, RS, MK, NT, AM, AR, JL, MM, KTD, JYC, SP), pp. 551–554.
DATE-2016-LiuN: Efficient global optimization of MEMS based on surrogate model assisted evolutionary algorithm (BL0, AN), pp. 555–558.
DATE-2016-RomenskaM: Efficient monitoring of loose-ordering properties for SystemC/TLM (YR, FM), pp. 559–562.
DATE-2016-NaveenS: Testable design of repeaterless low swing on-chip interconnect (KN, DKS), pp. 563–566.
DATE-2016-YenYS: All-digital hybrid-control buck converter for Integrated Voltage Regulator applications (TTY, BY, VSS0), pp. 567–570.
DATE-2016-Casale-RossiMDM: Panel: Looking backwards and forwards (MCR, GDM, AD, EM, DR, JS), pp. 571–575.
DATE-2016-SantenAPMH: Aging-aware voltage scaling (VMvS, HA, NP, SM, JH), pp. 576–581.
DATE-2016-LiAP: RECORD: Reducing register traffic for checkpointing in embedded processors (TL0, JAA, SP), pp. 582–587.
DATE-2016-SchlaferHSWLWD: Error resilience and energy efficiency: An LDPC decoder design study (PS, CHH, CS, CW, YL0, NW, LD), pp. 588–593.
DATE-2016-KokolisMRSS: Runtime interval optimization and dependable performance for application-level checkpointing (AK, AM, DR, CS, DS), pp. 594–599.
DATE-2016-BjornsethDN: A systematic approach to automated construction of power emulation models (BAB, AD, LN), pp. 600–605.
DATE-2016-DanesePZ: Automatic generation of power state machines through dynamic mining of temporal assertions (AD, GP, IZ), pp. 606–611.
DATE-2016-JainVR: Approximation through logic isolation for the design of quality configurable circuits (SJ, SV, AR), pp. 612–617.
DATE-2016-EskesenPP: Architecture synthesis for cost-constrained fault-tolerant flow-based biochips (MCE, PP, SP), pp. 618–623.
DATE-2016-LiTLHS: Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations (ML, TMT, BL0, TYH, US), pp. 624–629.
DATE-2016-IbrahimCS: Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochips (MI0, KC, KS), pp. 630–635.
DATE-2016-AminifarTEP: Self-triggered controllers and hard real-time guarantees (AA, PT, PE, ZP), pp. 636–641.
DATE-2016-XueRB: A spatio-temporal fractal model for a CPS approach to brain-machine-body interfaces (YX, SR, PB), pp. 642–647.
DATE-2016-AllenARMTP: Modular code generation for emulating the electrical conduction system of the human heart (NA, SA, PSR, AM, MT, NDP), pp. 648–653.
DATE-2016-ValenciaHGHG: Resource utilization and Quality-of-Control trade-off for a composable platform (JV, EPvH, DG, WPMHH, KG), pp. 654–659.
DATE-2016-AlmuribKL: Inexact designs for approximate low power addition by cell replacement (HAFA, TNK, FL), pp. 660–665.
DATE-2016-BanerjeeR: A general approach for highly defect tolerant Parallel Prefix Adder design (SB, WR), pp. 666–671.
DATE-2016-OmanaFM: Inverters' self-checking monitors for reliable photovoltaic systems (MO, AF, CM), pp. 672–677.
DATE-2016-MarazakisGFCTMB: EUROSERVER: Share-anything scale-out micro-server design (MM, JG, DF, PMC, JT, EM, AB, PS, JM, YD, ID), pp. 678–683.
DATE-2016-PalomarRYGPTUCF: Energy minimization at all layers of the data center: The ParaDIME project (OP, SKR, GY, JRTG, PP, ET, OSU, AC, PF, AS, YH, MK, CF, TK, MS, JS, DM), pp. 684–689.
DATE-2016-KatrinisSPZTKHR: Rack-scale disaggregated cloud data centers: The dReDBox project vision (KK, DS, DNP, GZ, DT, IK, KH, DR, CP, FE, SLB, QC, MN, DR, HK, TB), pp. 690–695.
DATE-2016-MavroidisPLNKGS: ECOSCALE: Reconfigurable computing and runtime system for future exascale systems (IM, IP, LL, DSN, DK, JG, IS, VP, MC, MP), pp. 696–701.
DATE-2016-FlichAAABCFHKMM: Enabling HPC for QoS-sensitive applications: The MANGO approach (JF, GA, PA, DAA, CB, AC, WF, YH, MK, BM, GM, HM, EP, FR, RT, DZ), pp. 702–707.
DATE-2016-SilvanoABBBBCCC: Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach (CS, GA, AB, ARB, LB, JB, RC, JMPC, CC, JM, GP, MP, PP, ER, NS, KS), pp. 708–713.
DATE-2016-AnneseCDV: A digital processor architecture for combined EEG/EMG falling risk prediction (VFA, MC, DD, DDV), pp. 714–719.
DATE-2016-HuangCY: Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analytics (HH, YC, HY0), pp. 720–725.
DATE-2016-SopicMRA: Touch-based system for beat-to-beat impedance cardiogram acquisition and hemodynamic parameters estimation (DS, SM, FJR, DA), pp. 726–731.
DATE-2016-BortolottiMBFB: Quantifying the benefits of compressed sensing on a WBSN-based real-time biosignal monitor (DB, BM, AB, EF, LB), pp. 732–737.
DATE-2016-EstibalsDMD: System level synthesis for virtual memory enabled hardware threads (NE, GD, AHEM, SD), pp. 738–743.
DATE-2016-MataiLAK: Composable, parameterizable templates for high-level synthesis (JM, DL, AA, RK), pp. 744–749.
DATE-2016-BarroisPS: Leveraging power spectral density for scalable system-level accuracy evaluation (BB, KP, OS), pp. 750–755.
DATE-2016-ZhangXLC: Leader: Accelerating ReRAM-based main memory by leveraging access latency discrepancy in crossbar arrays (HZ, NX, FL0, ZC), pp. 756–761.
DATE-2016-WangMEWLC: Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache (XW, MM, EE, WW, HL0, YC), pp. 762–767.
DATE-2016-LiWHTLCF: Exploiting more parallelism from write operations on PCM (ZL0, FW0, YH0, WT, JL, YC, DF0), pp. 768–773.
DATE-2016-MarcellinoH: Dynamic partitioning strategy to enhance symbolic execution (BAM, MSH), pp. 774–779.
DATE-2016-GuZCGD: Quantitative timing analysis of UML activity diagrams using statistical model checking (FG, XZ, MC, DG, RD), pp. 780–785.
DATE-2016-RamanathanPHCJ: Integrating symbolic and statistical methods for testing intelligent systems: Applications to machine learning and computer vision (AR, LLP, FH, DC, SKJ0), pp. 786–791.
DATE-2016-EbrahimiGBN: Path selection and sensor insertion flow for age monitoring in FPGAs (ME, ZG, EB, ZN), pp. 792–797.
DATE-2016-SahooKV: Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults (SSS, AK0, BV), pp. 798–803.
DATE-2016-BolchiniCM: Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis (CB, LC, AM), pp. 804–809.
DATE-2016-VenkataramanSK: A flexible inexact TMR technique for SRAM-based FPGAs (SV, RS, AK0), pp. 810–813.
DATE-2016-FawazN: Accurate verification of RC power grids (MF, FNN), pp. 814–817.
DATE-2016-IzosimovABT: Security-aware development of cyber-physical systems illustrated with automotive case study (VI, AA, OB, MT), pp. 818–821.
DATE-2016-PinxtenGBWS: Online heuristic for the Multi-Objective Generalized traveling salesman problem (JvP, MG, TB, UW, LJS), pp. 822–825.
DATE-2016-ZhuC: Towards low overhead control flow checking using regular structured control (ZZ, JCS), pp. 826–829.
DATE-2016-ChadjiminasSKMT: Emulation-based hierarchical fault-injection framework for coarse-to-fine vulnerability analysis of hardware-accelerated approximate algorithms (IC, IS, CK, MKM, TT), pp. 830–833.
DATE-2016-Leupers: Technology Transfer in computing systems: The TETRACOM approach (RL), pp. 834–837.
DATE-2016-DuchVGBA: Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices (LD, PGDV, SG, AB, DA), pp. 838–841.
DATE-2016-HezarjaribiFG: A machine learning approach for medication adherence monitoring using body-worn sensors (NH, RF, HG), pp. 842–845.
DATE-2016-AiPR: Requirements-centric closed-loop validation of implantable cardiac devices (WA, NDP, PSR), pp. 846–849.
DATE-2016-LiuCHGC: Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications (NL0, KSC, WGH, BHG, JSC), pp. 850–853.
DATE-2016-HaghbayanMRLT: A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era (MHH, AM, AMR, PL, HT), pp. 854–857.
DATE-2016-GaoP: Automotive V2X on phones: Enabling next-generation mobile ITS apps (JHG0, LSP), pp. 858–863.
DATE-2016-FursinLP: Collective Knowledge: Towards R&D sustainability (GF, AL, EP), pp. 864–869.
DATE-2016-Schoeberl: Lessons learned from the EU project T-CREST (MS), pp. 870–875.
DATE-2016-NurmiL: MULTI-POS: Marie Curie network in multi-technology positioning (JN, ESL), pp. 876–881.
DATE-2016-KuperSKGBC: Program transformations in the POLCA project (JK, LS, KK, CWG, DRB, MC), pp. 882–887.
DATE-2016-KeramidasAVSWRG: Computation and communication challenges to deploy robots in assisted living environments (GK, CPA, NSV, FS, PW, JR, DG, MH, SK, TG, VK, VM), pp. 888–893.
DATE-2016-WachmannSZTCEGH: ATHENIS_3D: Automotive tested high-voltage and embedded non-volatile integrated SoC platform with 3D technology (EW, SS, CZ, PT, JC, TE, SG, CH, JS, PC, DMT, LF, LF), pp. 894–899.
DATE-2016-MaAA: Run time interpretation for creating custom accelerators (SM, ZA, DA0), pp. 900–905.
DATE-2016-TrainitiDMBS: A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems (EMGT, GCD, AM, CB, MDS), pp. 906–911.
DATE-2016-LoschBKPP: Performance-centric scheduling with task migration for a heterogeneous compute node in the data center (AL, TB, TK, CP, MP), pp. 912–917.
DATE-2016-MengAGK: Adaptive Threshold Non-Pareto Elimination: Re-thinking machine learning for system level design space exploration on FPGAs (PM, AA, QG, RK), pp. 918–923.
DATE-2016-SelyuninNBNG: Monitoring of MTL specifications with IBM's spiking-neuron model (KS, TN, EB, DN, RG), pp. 924–929.
DATE-2016-IqtedarHSH: Formal probabilistic analysis of distributed resource management schemes in on-chip systems (SI, OH, MS0, JH), pp. 930–935.
DATE-2016-SalkhordehA: An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture (RS, HA), pp. 936–941.
DATE-2016-ZhangJJ: Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead (ZZ, LJ, ZJ), pp. 942–947.
DATE-2016-ShirinzadehSGD: Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs (SS, MS, PEG, RD), pp. 948–953.
DATE-2016-SpasicLS: Exploiting resource-constrained parallelism in hard real-time streaming applications (JS, DL, TPS), pp. 954–959.
DATE-2016-DoLC: Transaction Parameterized Dataflow: A model for context-dependent streaming applications (XD, SL, AC0), pp. 960–965.
DATE-2016-HarrisH: GLAsT: Learning formal grammars to translate natural language specifications into hardware assertions (CBH, IGH), pp. 966–971.
DATE-2016-ScheiblerEB: Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs (KS, DE, BB0), pp. 972–977.
DATE-2016-WangLKC: Pre-bond testing of the silicon interposer in 2.5D ICs (RW0, ZL, SK, KC), pp. 978–983.
DATE-2016-KinseherZPL: Improving SRAM test quality by leveraging self-timed circuits (JK, LBZ, IP, AL), pp. 984–989.
DATE-2016-PiessensV: Software security: Vulnerabilities and countermeasures for two attacker models (FP, IV), pp. 990–999.
DATE-2016-DuOLSLG: OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction (GD, YO, XL, PS, ZL, MG), pp. 1000–1005.
DATE-2016-RosaMLC: MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architectures (TRdR, TM, RL, FC), pp. 1006–1011.
DATE-2016-KostrzewaSE: Slack-based resource arbitration for real-time Networks-on-Chip (AK, SS, RE), pp. 1012–1017.
DATE-2016-ZandrahimiADC: Challenges of using on-chip performance monitors for process and environmental variation compensation (MZ, ZAA, PD, AC), pp. 1018–1019.
DATE-2016-SivadasanCBHA: Study of workload impact on BTI HCI induced aging of digital circuits (AS, FC, SAB, VH, LA), pp. 1020–1021.
DATE-2016-BecharaCGSLSDL: Fast prototyping platform for navigation systems with sensors fusion (CB, KBC, MG, RS, ML, LS, TD, YL), pp. 1022–1023.
DATE-2016-KuoAR: Precision timed industrial automation systems (MMYK, SA, PSR), pp. 1024–1025.
DATE-2016-HamedSES: AUTOSAR-based communication coprocessor for automotive ECUs (AH, MS, MWEK, AS), pp. 1026–1027.
DATE-2016-GuntherHLA: Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing (DG0, TH, RL, GA), pp. 1028–1029.
DATE-2016-SoekenAGM: Optimizing Majority-Inverter Graphs with functional hashing (MS, LGA, PEG, GDM), pp. 1030–1035.
DATE-2016-ChengJJ: Resource-aware functional ECO patch generation (ACC, IHRJ, JYJ), pp. 1036–1041.
DATE-2016-WuC: Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits (GW0, CCNC), pp. 1042–1047.
DATE-2016-Sayed-AhmedGKSD: Formal verification of integer multipliers by combining Gröbner basis with logic reduction (AARSA, DG, UK, MS, RD), pp. 1048–1053.
DATE-2016-AdlerMV: Root-cause analysis for memory-locked errors (JA, DM, AGV), pp. 1054–1059.
DATE-2016-TarawnehMY: Formal verification of clock domain crossing using gate-level models of metastable flip-flops (GT, AM, AY), pp. 1060–1065.
DATE-2016-SerranoMBQ: Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptions (MAS, AM, MB, EQ), pp. 1066–1071.
DATE-2016-MelaniMCCT: Speed optimization for tasks with two resources (AM, RM0, DC, MC, LT), pp. 1072–1077.
DATE-2016-HuangC: Self-suspension real-time tasks under fixed-relative-deadline fixed-priority scheduling (WHH, JJC), pp. 1078–1083.
DATE-2016-LoLH: Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC) (WHL, KzL, TH), pp. 1084–1089.
DATE-2016-ChengHCHK: Minimizing peak temperature for pipelined hard real-time systems (LC0, KH0, GC0, BH, AK), pp. 1090–1095.
DATE-2016-Sahu: Thermal aware scheduling and mapping of multiphase applications onto chip multiprocessor (AS), pp. 1096–1101.
DATE-2016-BarkeFG0HHHLNNO: Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis (EB, AF, GG, CG0, LH, SH, EH, HSLL, WN, GN, MO, CR, FS), pp. 1102–1111.
DATE-2016-ZengA: A q-gram birthmarking approach to predicting reusable hardware (KZ, PMA), pp. 1112–1115.
DATE-2016-JaliliS: Captopril: Reducing the pressure of bit flips on hot locations in non-volatile main memories (MJ0, HSA), pp. 1116–1119.
DATE-2016-MoestlE: Handling complex dependencies in system design (MM, RE), pp. 1120–1123.
DATE-2016-KarputkinR: A synthesis-agnostic behavioral fault model for high gate-level fault coverage (AK, JR), pp. 1124–1127.
DATE-2016-TrockF: Recursive hierarchical DFT methodology with multi-level clock control and scan pattern retargeting (DT, RF), pp. 1128–1131.
DATE-2016-LaufenbergRVBKR: Combining graph-based guidance with error effect simulation for efficient safety analysis (JL, SR0, AV, OB0, TK, WR), pp. 1132–1135.
DATE-2016-BoratenK: Packet security with path sensitization for NoCs (TB, AKK), pp. 1136–1139.
DATE-2016-WilleKHWO: Synthesis of approximate coders for on-chip interconnects using reversible logic (RW, OK, SH, MW, AGO), pp. 1140–1143.
DATE-2016-DattaWSGCMN: Design-synthesis co-optimisation using skewed and tapered gates (AD, JDW, AS, SG, YHC, KM, CN), pp. 1144–1147.
DATE-2016-ZieglerLGONC: A synthesis-parameter tuning system for autonomous design-space exploration (MMZ, HYL, GG, BO, RN, LPC), pp. 1148–1151.
DATE-2016-MukherjeeSKM: Unbounded safety verification for hardware using software analyzers (RM, PS, DK, TM), pp. 1152–1155.
DATE-2016-IrfanCGRS: Verilog2SMV: A tool for word-level verification (AI, AC, AG, MR, RS), pp. 1156–1159.
DATE-2016-LeHGD: Towards formal verification of real-world SystemC TLM peripheral models - a case study (HML0, VH, DG, RD), pp. 1160–1163.
DATE-2016-WangLL: Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage (YW0, HL, XL0), pp. 1164–1167.
DATE-2016-WangKC: A low overhead error confinement method based on application statistical characteristics (ZW0, GK, AC), pp. 1168–1171.
DATE-2016-ClercqKC0MBPSV: SOFIA: Software and control flow integrity architecture (RdC, RDK, BC, BY0, PM, KDB, BP, BDS, IV), pp. 1172–1177.
DATE-2016-Francillon: Trust, but verify: Why and how to establish trust in embedded devices (AF), pp. 1178–1182.
DATE-2016-PaschouPND: CrossOver: Clock domain crossing under virtual-channel flow control (MP, AP, CN, GD), pp. 1183–1188.
DATE-2016-Abdel-KhalekB: Correct runtime operation for NoCs through adaptive-region protection (RAK, VB), pp. 1189–1194.
DATE-2016-RezaeiMAD: Fault-tolerant 3-D network-on-chip design using dynamic link sharing (SHSR, MM, RYA, MD), pp. 1195–1200.
DATE-2016-ContiPMRB: Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms (FC0, DP, AM, DR, LB), pp. 1201–1206.
DATE-2016-PalominoSSH: Thermal optimization using adaptive approximate computing for video coding (DP0, MS0, AAS, JH), pp. 1207–1212.
DATE-2016-PlankHHD: High performance Time-of-Flight and color sensor fusion with image-guided depth super resolution (HP, GH, TH, ND), pp. 1213–1218.
DATE-2016-SchollSW: Saturated min-sum decoding: An “afterburner” for LDPC decoder hardware (SS, PS, NW), pp. 1219–1224.
DATE-2016-YuZZWD: Utilizing macromodels in floating random walk based capacitance extraction (WY, BZ, CZ, HW, LD), pp. 1225–1230.
DATE-2016-MartinsVS: Variability and statistical analysis flow for dynamic linear systems with large number of inputs (ALM, JFV, LMS), pp. 1231–1236.
DATE-2016-GolanbariKET: Variation-aware near threshold circuit synthesis (MSG, SK, ME, MBT), pp. 1237–1242.
DATE-2016-LeeAC: Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic (JL, JHA, KC), pp. 1243–1248.
DATE-2016-AlvesDSC: Large vector extensions inside the HMC (MAZA, MD, PCS, LC), pp. 1249–1254.
DATE-2016-LiuJLHA: minFlash: A minimalistic clustered flash array (ML, SWJ, SL, JH, A), pp. 1255–1260.
DATE-2016-CesariniMB: An optimized task-based runtime system for resource-constrained parallel accelerators (DC, AM, LB), pp. 1261–1266.
DATE-2016-BombieriBF: A fine-grained performance model for GPU architectures (NB, FB, FF), pp. 1267–1272.
DATE-2016-LiSKZCC: Critical points based register-concurrency autotuning for GPUs (AL, SLS, AK0, EZZ, DGCM, HC), pp. 1273–1278.
DATE-2016-LotfiRYEG: Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration (AL, AR, AY, HE, RKG0), pp. 1279–1284.
DATE-2016-WenMLCPG: A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations (WW, MM, HL0, YC, YP, NG0), pp. 1285–1290.
DATE-2016-WangTC: Thermal-aware TSV repair for electromigration in 3D ICs (SW, MBT, KC), pp. 1291–1296.
DATE-2016-CasperGGGKMS: Electrothermal simulation of bonding wire degradation under uncertain geometries (TC, HDG, RG, TG, TK, PM, SS), pp. 1297–1302.
DATE-2016-WaidnerK: Security in industrie 4.0 - challenges and solutions for the fourth industrial revolution (MW, MK), pp. 1303–1308.
DATE-2016-CoskunGJJKKMRSZ: Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems (AKC, AG, WJ0, AJ, ABK, JK, YM, JR, VS, TZ), pp. 1309–1314.
DATE-2016-MondalGKD: Adaptive multi-voltage scaling in wireless NoC for high performance low power applications (HKM, SHG, RK, SD), pp. 1315–1320.
DATE-2016-CataniaMMPP: Energy efficient transceiver in wireless Network on Chip architectures (VC, AM, SM, MP, DP), pp. 1321–1326.
DATE-2016-ImaniRR: Resistive configurable associative memory for approximate computing (MI, AR, TSR), pp. 1327–1332.
DATE-2016-PahlevanVA: Exploiting CPU-load and data correlations in multi-objective VM placement for geo-distributed data centers (AP, PGDV, DA), pp. 1333–1338.
DATE-2016-NabavinejadG: Energy efficiency in cloud-based MapReduce applications through better performance estimation (SMN, MG), pp. 1339–1344.
DATE-2016-HilburgZRMA: Unsupervised power modeling of co-allocated workloads for energy efficiency in data centers (JCSH, MZ, JLRM, JMM, JLA), pp. 1345–1350.
DATE-2016-FarahmandiM: Automated test generation for Debugging arithmetic circuits (FF, PM0), pp. 1351–1356.
DATE-2016-HassanP: MCXplore: An automated framework for validating memory controller designs (MH, HDP), pp. 1357–1362.
DATE-2016-BhattacharjeeCB: EAST: Efficient Assertion Simulation techniques (DB, SC, AB), pp. 1363–1368.
DATE-2016-BeigMohammadiA: Combinational trace signal selection with improved state restoration for post-silicon debug (SB, BA), pp. 1369–1374.
DATE-2016-MoreauBSWL: Practical way halting by speculatively accessing halt tags (DM, AB, MS, DBW, PLE), pp. 1375–1380.
DATE-2016-TziantzioulisGF: Lazy Pipelines: Enhancing quality in approximate computing (GT, AMG, SMF, NH, SOM, SP0), pp. 1381–1386.
DATE-2016-PopoffSSGGB: High-efficiency logarithmic number unit design based on an improved cotransformation scheme (YP, FS, MS, MG, FKG, LB), pp. 1387–1392.
DATE-2016-RahmanLC: Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array (AR, JL, KC), pp. 1393–1398.
DATE-2016-SunAHHN: Energy efficient video fusion with heterogeneous CPU-FPGA devices (PS, AA, IH, PRH, JLNY), pp. 1399–1404.
DATE-2016-NikitakisP: Highly efficient reconfigurable parallel graph cuts for embedded vision (AN, IP), pp. 1405–1410.
DATE-2016-SaifDEAN: Pareto front analog layout placement using Satisfiability Modulo Theories (SMS, MD, MWEK, HMA, SMN), pp. 1411–1416.
DATE-2016-PengYYZZ: Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data (BP, FY0, CY, XZ0, DZ), pp. 1417–1422.
DATE-2016-WangCO: PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation (YW0, CC, MO), pp. 1423–1428.
DATE-2016-DasDPC: Reliability and performance trade-offs for 3D NoC-enabled multicore chips (SD, JRD, PPP, KC), pp. 1429–1432.
DATE-2016-YaoL: Memory-access aware DVFS for network-on-chip in CMPs (YY0, ZL), pp. 1433–1436.
DATE-2016-SaniCC: A dynamically reconfigurable ECC decoder architecture (AS, PC, CC), pp. 1437–1440.
DATE-2016-AkhlaghiRG: Resistive Bloom filters: From approximate membership to approximate computing with bounded errors (VA, AR, RKG0), pp. 1441–1444.
DATE-2016-SatriaGZTKYRC: Real-time system-level implementation of a telepresence robot using an embedded GPU platform (MTS, STG, WZ, KPT, AK, PY, KR, DC), pp. 1445–1448.
DATE-2016-YitbarekYDA: Exploring specialized near-memory processing for data intensive operations (SFY, TY, RD, TMA), pp. 1449–1452.
DATE-2016-LatifisPDCLMC: Matlab to C compilation targeting Application Specific Instruction Set Processors (IL, KP, GD, HC, CL, KM, FC), pp. 1453–1456.
DATE-2016-ZhangLS: Sampling-based buffer insertion for post-silicon yield improvement under process variability (GLZ, BL0, US), pp. 1457–1460.
DATE-2016-BasuJCR: PRADA: Combating voltage noise in the NoC power supply through flow-control and routing algorithms (PB, RJS, KC, SR), pp. 1461–1464.
DATE-2016-KangPLBM: A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache (KK, SP, JBL, LB, GDM), pp. 1465–1468.
DATE-2016-KhanSGSH: Power-efficient load-balancing on heterogeneous computing platforms (MUKK, MS0, AG, TS, JH), pp. 1469–1472.
DATE-2016-NassarKZ: Topaz: Mining high-level safety properties from logic simulation traces (AN, FJK, SRZ), pp. 1473–1476.
DATE-2016-FarahmandiMR: Exploiting transaction level models for observability-aware post-silicon test generation (FF, PM0, SR), pp. 1477–1480.
DATE-2016-ZendeganiKFASP: SEERAD: A high speed yet energy-efficient rounding-based approximate divider (RZ, MK, AF, AAK, SS, MP), pp. 1481–1484.
DATE-2016-PanicHARQC: Improving performance guarantees in wormhole mesh NoC designs (MP, CH, JA, AR0, EQ, FJC), pp. 1485–1488.
DATE-2016-HoangSC: A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systems (TTH, AS, AAC), pp. 1489–1492.
DATE-2016-HorreinGLLA: Ouessant: Flexible integration of dedicated coprocessors in Systems on Chip (PHH, PDG, EL, AL, MA), pp. 1493–1496.
DATE-2016-NikitakisPMD: A novel background subtraction scheme for in-camera acceleration in thermal imagery (AN, IP, KM, ADD), pp. 1497–1500.
DATE-2016-Sanchez-ElezPSM: Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA (MSE, IP, FS, HM), pp. 1501–1504.
DATE-2016-Morales-Villanueva: Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAs (AMV, RK, AGR), pp. 1505–1508.
DATE-2016-LiJD: Analog circuit topological feature extraction with unsupervised learning of new sub-structures (HL, FJ, AD), pp. 1509–1512.
DATE-2016-NevesMLH: Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach (DN, RM0, NL0, NH), pp. 1513–1516.
DATE-2016-AysuGMPWS: A design method for remote integrity checking of complex PCBs (AA, SG, HM, CP, LW, PS), pp. 1517–1522.
DATE-2016-KastnerHA: Quantifying hardware security using joint information flow analysis (RK, WH0, AA), pp. 1523–1528.
DATE-2016-RegazzoniI: Instruction Set Extensions for secure applications (FR0, PI), pp. 1529–1534.
DATE-2016-ObengNB: Hardware security through chain assurance (YO, CN, DB), pp. 1535–1537.
DATE-2016-BiSYSJ: Leverage Emerging Technologies For DPA-Resilient Block Cipher Design (YB, KS, JSY, FXS, YJ), pp. 1538–1543.
DATE-2016-ChenHJNY: Using emerging technologies for hardware security beyond PUFs (AC, XSH, YJ, MTN, XY), pp. 1544–1549.
DATE-2016-AndersonHY: Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy (JHA, YHA, SY), pp. 1550–1555.
DATE-2016-MorenoKF: Efficient program tracing and monitoring through power consumption - with a little help from the compiler (CM0, SK, SF), pp. 1556–1561.
DATE-2016-ZhongLLLLS: FLIC: Fast, lightweight checkpointing for mobile virtualization using NVRAM (KZ, DL, LL0, LL, YL, ZS), pp. 1562–1567.
DATE-2016-LeeCF: PAIS: Parallelization aware instruction scheduling for improving soft-error reliability of GPU-based systems (HL, HC, MAAF), pp. 1568–1573.
DATE-2016-SchulzB: Accelerating source-level timing simulation (SS, OB0), pp. 1574–1579.
DATE-2016-ChenXWY: Sparsity-oriented sparse solver design for circuit simulation (XC0, LX, YW0, HY), pp. 1580–1585.
DATE-2016-FraccaroliLVQF: Integration of mixed-signal components into virtual platforms for holistic simulation of smart systems (EF, ML, SV, DQ, FF), pp. 1586–1591.
DATE-2016-OkudaT: Decision tree generation for decoding irregular instructions (KO, HT), pp. 1592–1597.
DATE-2016-SouzaCRB: A reconfigurable heterogeneous multicore with a homogeneous ISA (JDS, LC, MBR, ACSB), pp. 1598–1603.
DATE-2016-PeemenSLJMC: The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision (MP, RS, SL, BHHJ, BM, HC), pp. 1604–1609.
DATE-2016-TeimouriTS: Improving scalability of CMPs with dense ACCs coverage (NT, HT, GS), pp. 1610–1615.
DATE-2016-NurvitadhiMWVM: Hardware accelerator for analytics of sparse data (EN, AKM, YW, GV, DM), pp. 1616–1621.
DATE-2016-CilardoA: Securing the cloud with reconfigurable computing: An FPGA accelerator for homomorphic encryption (AC, DA), pp. 1622–1627.
DATE-2016-JainMF: Throughput oriented FPGA overlays using DSP blocks (AKJ, DLM, SAF), pp. 1628–1633.
DATE-2016-GuoSBBZW: Run-time phase prediction for a reconfigurable VLIW processor (QG, ALS, AB, ACSB, XZ, SW), pp. 1634–1639.
DATE-2016-VerbeekYEB: ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects (FV, PMY, AE, NB), pp. 1640–1645.
DATE-2016-AhrendtsHE: Guarantees for runnable entities with heterogeneous real-time requirements (LA, ZAHH, RE), pp. 1646–1651.
DATE-2016-YangHCLRX: Validating scheduling transformation for behavioral synthesis (ZY, KH, KC, LL, SR, FX), pp. 1652–1657.

Luca Fanucci, Jürgen TeichProceedings of the 20th Conference and Exhibition on Design, Automation and Test in EuropeDATE, 2016.

Contents (307 items)

Luca Fanucci, Jürgen Teich
Proceedings of the 20th Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2016.