Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration
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Atieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Rajesh K. Gupta 0001
Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration
DATE, 2016.

DATE 2016
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@inproceedings{DATE-2016-LotfiRYEG,
	author        = "Atieh Lotfi and Abbas Rahimi and Amir Yazdanbakhsh and Hadi Esmaeilzadeh and Rajesh K. Gupta 0001",
	booktitle     = "{Proceedings of the 20th Conference and Exhibition on Design, Automation and Test in Europe}",
	ee            = "http://ieeexplore.ieee.org/document/7459507/",
	isbn          = "978-3-9815-3707-9",
	pages         = "1279--1284",
	publisher     = "{IEEE}",
	title         = "{Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration}",
	year          = 2016,
}


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