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Travelled to:
2 × Germany
3 × France
3 × USA
Collaborated with:
L.Benini R.K.Gupta A.Marongiu A.Ghofrani K.Cheng I.Loi M.R.Kakoee D.Cesarini P.Burgio M.A.Lastras-Montaño A.Yazdanbakhsh D.Mahajan B.Thwaites J.Park A.Nagendrakumar S.Sethuraman K.Ramkrishnan N.Ravindran R.Jariwala H.Esmaeilzadeh K.Bazargan
Talks about:
cluster (3) variat (3) memori (3) energi (3) effici (3) architectur (2) processor (2) approxim (2) memrist (2) hardwar (2)

Person: Abbas Rahimi

DBLP DBLP: Rahimi:Abbas

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
DATE 20112011

Wrote 10 papers:

DAC-2015-RahimiCMGB #clustering #embedded #hardware #memory management #scheduling #variability
Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters (AR, DC, AM, RKG, LB), p. 6.
DATE-2015-RahimiGCBG #approximate #energy #memory management
Approximate associative memristive memory for energy-efficient GPUs (AR, AG, KTC, LB, RKG), pp. 1497–1502.
DATE-2015-YazdanbakhshMTP #approximate #design #hardware #named
Axilog: language support for approximate hardware design (AY, DM, BT, JP, AN, SS, KR, NR, RJ, AR, HE, KB), pp. 812–817.
DAC-2014-RahimiGLCBG #architecture #collaboration #compilation #energy
Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing (AR, AG, MALM, KTC, LB, RKG), p. 6.
DATE-2014-RahimiBG #energy #fault
Temporal memoization for energy-efficient timing error recovery in GPGPUs (AR, LB, RKG), pp. 1–6.
DAC-2013-RahimiBG #architecture
Aging-aware compiler-directed VLIW assignment for GPGPU architectures (AR, LB, RKG), p. 6.
DATE-2013-RahimiBG #adaptation #approach
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging (AR, LB, RKG), pp. 1695–1700.
DATE-2013-RahimiMBGB #clustering
Variation-tolerant OpenMP tasking on tightly-coupled processor clusters (AR, AM, PB, RKG, LB), pp. 541–546.
DATE-2012-RahimiBG #analysis
Analysis of instruction-level vulnerability to dynamic voltage and temperature variations (AR, LB, RKG), pp. 1102–1105.
DATE-2011-RahimiLKB #clustering #network
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters (AR, IL, MRK, LB), pp. 491–496.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.