Logic Synthesis and Verification of the CPU and Caches of a Mainframe System
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Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System
DATE, 1994.

EDAC 1994
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@inproceedings{EDAC-1994-NguyenTDTV,
	author        = "Huy Nam Nguyen and J. P. Tual and L. Ducousso and Michel Thill and P. Vallet",
	booktitle     = "{Proceedings of the European Conference on Design Automation (EDAC), European Test Conference (ETC) and the European Event in ASIC Design (EUROASIC)}",
	isbn          = "0-8186-5410-4",
	pages         = "60--64",
	publisher     = "{IEEE Computer Society}",
	title         = "{Logic Synthesis and Verification of the CPU and Caches of a Mainframe System}",
	year          = 1994,
}

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