BibSLEIGH — synthesis tag

synthesis

synthesis

Tag #synthesis

1336 papers:

POPL-2020-AnSMS #relational #using: Augmented example-based synthesis using relational perturbation properties (SA, RS, SM, RS), p. 24.
POPL-2020-BansalNS #coordination #linear #source code #specification: Synthesis of coordination programs from linear temporal specifications (SB, KSN, YS), p. 27.
POPL-2020-GuoJJZWJP #abstraction #refinement: Program synthesis by type-guided abstraction refinement (ZG, MJ, DJ, JZ, ZW, RJ, NP), p. 28.
POPL-2020-RaghothamanMZNS #datalog #source code: Provenance-guided synthesis of Datalog programs (MR, JM, DZ, MN, BS), p. 27.
FM-2019-CeskaHJK #probability #sketching: Counterexample-Driven Synthesis for Probabilistic Program Sketches (MC0, CH, SJ, JPK), pp. 101–120.
FM-2019-LutebergetJS #capacity #layout #specification: Synthesis of Railway Signaling Layout from Local Capacity Specifications (BL, CJ, MS), pp. 121–137.
IFM-2019-BenesBGPS #algebra #constraints #parametricity #using: Accelerating Parameter Synthesis Using Semi-algebraic Constraints (NB, LB, MG, SP, DS), pp. 27–45.
FDG-2019-WangCYPTA #game studies #learning: Goal-based progression synthesis in a korean learning game (SW, BC, SY, JYP, NT, EA), p. 9.
ICML-2019-KenterWCCV #named #network #speech: CHiVE: Varying Prosody in Speech Synthesis with a Linguistically Driven Dynamic Hierarchical Conditional Variational Network (TK, VW, CaC, RC, JV), pp. 3331–3340.
ICML-2019-MarafiotiPHM #generative: Adversarial Generation of Time-Frequency Features with application in audio synthesis (AM, NP, NH, PM), pp. 4352–4362.
ICML-2019-YoungBN #generative #learning #modelling: Learning Neurosymbolic Generative Models via Program Synthesis (HY, OB, MN), pp. 7144–7153.
KDD-2019-HuangLK00M0 #ranking: Contextual Fact Ranking and Its Applications in Table Synthesis and Compression (SH, JL, FK, XW0, YW0, DM, CY0), pp. 285–293.
MoDELS-2019-PhilippSE #analysis #architecture #modelling: Model-Based Resource Analysis and Synthesis of Service-Oriented Automotive Software Architectures (PO, SK, ES), pp. 128–138.
MoDELS-2019-SantosSSN #contract #design #named: CONDEnSe: Contract Based Design Synthesis (CARdS, AHS, TS, MN), pp. 250–260.
OOPSLA-2019-BavishiLFSS #generative #named: AutoPandas: neural-backed generators for program synthesis (RB, CL, RF, KS, IS), p. 27.
OOPSLA-2019-MarianoRXNQFS #algebra #library #specification: Program synthesis with algebraic library specifications (BM, JR, SX, TN, XQ, JSF, ASL), p. 25.
OOPSLA-2019-MiltnerGLLRSTU #on the #on the fly: On the fly synthesis of edit suggestions (AM, SG, VL, AL, AR, GS, AT0, AU), p. 29.
PLATEAU-2019-Crichton: Human-Centric Program Synthesis (WC), p. 5.
PLDI-2019-IyerJPRR #machine learning: Synthesis and machine learning for heterogeneous extraction (ASI, MJ, SP, AR, SKR), pp. 301–315.
PLDI-2019-KnothWP0: Resource-guided program synthesis (TK, DW, NP, JH0), pp. 253–268.
PLDI-2019-ZhuXMJ #framework #induction #learning: An inductive synthesis framework for verifiable reinforcement learning (HZ0, ZX, SM, SJ), pp. 686–701.
POPL-2019-HoushmandL #analysis #coordination #named #replication: Hamsaz: replication coordination analysis and synthesis (FH, ML), p. 32.
POPL-2019-PolikarpovaS #source code: Structuring the synthesis of heap-manipulating programs (NP, IS), p. 30.
POPL-2019-SaadCSRM #automation #modelling #probability #source code: Bayesian synthesis of probabilistic programs for automatic data modeling (FAS, MFCT, US, MCR, VKM), p. 32.
POPL-2019-ShiSL #component #named: FrAngel: component-based synthesis with control structures (KS, JS, PL), p. 29.
ASE-2019-Sharma #adaptation #automation #source code #using: Automatically Repairing Binary Programs Using Adapter Synthesis (VS), pp. 1238–1241.
ESEC-FSE-2019-BavishiYP #automation #data-driven #named #static analysis: Phoenix: automated data-driven synthesis of repairs for static analysis violations (RB, HY, MRP), pp. 613–624.
ESEC-FSE-2019-ChenMF #multi #specification: Maximal multi-layer specification synthesis (YC, RM, YF), pp. 602–612.
SLE-2019-SousaSF #editing #integration #interactive #modelling #specification: Operationalizing the integration of user interaction specifications in the synthesis of modeling editors (VS, ES, KF), pp. 42–54.
ASPLOS-2019-PhothilimthanaE #data flow #gpu #kernel: Swizzle Inventor: Data Movement Synthesis for GPU Kernels (PMP, ASE, AW0, AJ, BH, HB, SJK, VG, ET, RB), pp. 65–78.
CASE-2019-AhlbergD #logic #metric #multi: Human-in-the-Loop Control Synthesis for Multi-Agent Systems under Hard and Soft Metric Interval Temporal Logic Specifications* (SA, DVD), pp. 788–793.
CASE-2019-FarooquiF #learning #modelling #using: Synthesis of Supervisors for Unknown Plant Models Using Active Learning (AF, MF), pp. 502–508.
CASE-2019-GoordenF: No synthesis needed, we are alright already (MG, MF), pp. 195–202.
CASE-2019-ThuijsmanHTRS #automaton #finite: Computational Effort of BDD-based Supervisor Synthesis of Extended Finite Automata (ST, DH, RJMT, MAR, RRHS), pp. 486–493.
CADE-2019-PeuterS #invariant #on the #parametricity: On Invariant Synthesis for Parametric Systems (DP, VSS), pp. 385–405.
CAV-2019-Busatto-GastonM #approach #automaton #robust: Robust Controller Synthesis in Timed Büchi Automata: A Symbolic Approach (DBG, BM, PAR, OS), pp. 572–590.
CAV-2019-DrewsAD #constraints #performance #probability: Efficient Synthesis with Probabilistic Constraints (SD, AA, LD), pp. 278–296.
CAV-2019-ElfarWP #game studies #using: Security-Aware Synthesis Using Delayed-Action Games (ME, YW0, MP), pp. 180–199.
CAV-2019-FedyukovichPMG #invariant #quantifier: Quantified Invariants via Syntax-Guided Synthesis (GF, SP, KM, AG), pp. 259–277.
CAV-2019-Finkbeiner0PS #logic: Temporal Stream Logic: Synthesis Beyond the Bools (BF, FK0, RP, MS), pp. 609–629.
CAV-2019-HuBCDR #proving: Proving Unrealizability for Syntax-Guided Synthesis (QH, JB, JC, LD, TWR), pp. 335–352.
CAV-2019-KangLT #automation #framework #platform: Automated Synthesis of Secure Platform Mappings (EK, SL, ST), pp. 219–237.
CAV-2019-KimAS #flexibility #pipes and filters #robust: Flexible Computational Pipelines for Robust Abstraction-Based Control Synthesis (ESK, MA, SAS), pp. 591–608.
CAV-2019-PadhiMN0 #theory and practice: Overfitting in Synthesis: Theory and Practice (SP, TDM, AVN, RS0), pp. 315–334.
CAV-2019-SotoHSZ #automaton #hybrid #linear: Membership-Based Synthesis of Linear Hybrid Automata (MGS, TAH, CS0, LZ), pp. 297–314.
CAV-2019-Rabe #functional #incremental #quantifier: Incremental Determinization for Quantifier Elimination and Functional Synthesis (MNR), pp. 84–94.
CAV-2019-ReynoldsBNBT #named #performance: cvc4sy: Smart and Fast Term Enumeration for Syntax-Guided Synthesis (AR, HB, AN, CWB, CT), pp. 74–83.
VMCAI-2019-FedyukovichGG #effectiveness #functional #lazy evaluation: Lazy but Effective Functional Synthesis (GF, AG, AG), pp. 92–113.
VMCAI-2019-HamzaK #string: Minimal Synthesis of String to String Functions from Examples (JH, VK), pp. 48–69.
VMCAI-2019-SmithA #equivalence #reduction: Program Synthesis with Equivalence Reduction (CS, AA), pp. 24–47.
FM-2018-0001BFLMR #automaton #energy #nondeterminism #robust #using: Optimal and Robust Controller Synthesis - Using Energy Timed Automata with Uncertainty (GB0, PB, UF, KGL, NM, PAR), pp. 203–221.
IFM-2018-SchmidtKL #formal method #generative #modelling #using: Repair and Generation of Formal Models Using Synthesis (JS, SK, ML), pp. 346–366.
SEFM-2018-TonderG #architecture: Cross-Architecture Lifter Synthesis (RvT, CLG), pp. 155–170.
ICML-2018-KalchbrennerESN #performance: Efficient Neural Audio Synthesis (NK, EE, KS, SN, NC, EL, FS, AvdO, SD, KK), pp. 2415–2424.
ICML-2018-OordLBSVKDLCSCG #parallel #performance #speech: Parallel WaveNet: Fast High-Fidelity Speech Synthesis (AvdO, YL, IB, KS, OV, KK, GvdD, EL, LCC, FS, NC, DG, SN, SD, EE, NK, HZ, AG, HK, TW, DB, DH), pp. 3915–3923.
ICML-2018-PuMSK: Selecting Representative Examples for Program Synthesis (YP, ZM, ASL, LPK), pp. 4158–4167.
ICML-2018-Skerry-RyanBXWS #speech #towards: Towards End-to-End Prosody Transfer for Expressive Speech Synthesis with Tacotron (RJSR, EB, YX, YW, DS, JS, RJW, RC, RAS), pp. 4700–4709.
ICML-2018-SunNSL: Neural Program Synthesis from Diverse Demonstration Videos (SHS, HN, SS, JJL), pp. 4797–4806.
ICML-2018-WangSZRBSXJRS #modelling #speech: Style Tokens: Unsupervised Style Modeling, Control and Transfer in End-to-End Speech Synthesis (YW, DS, YZ, RJSR, EB, JS, YX, YJ, FR, RAS), pp. 5167–5176.
ICPR-2018-Gong0LL #semantics: Dynamic Facial Expression Synthesis Driven by Deformable Semantic Parts (NG, YY0, YL, DL), pp. 2929–2934.
ICPR-2018-LiuMXP #image #network #semantics: Semantic Image Synthesis via Conditional Cycle-Generative Adversarial Networks (XL, GM, SX, CP), pp. 988–993.
ICPR-2018-LuoKW #generative #image #network: Traffic Sign Image Synthesis with Generative Adversarial Networks (HL, QK, FW), pp. 2540–2545.
MoDELS-2018-EderBVIK #architecture #automation #deployment #distributed #framework #hardware: From Deployment to Platform Exploration: Automatic Synthesis of Distributed Automotive Hardware Architectures (JE, AB, SV, AI, MK), pp. 438–446.
ECOOP-2018-GuM00CL #automation #execution #online: Automating Object Transformations for Dynamic Software Updating via Online Execution Synthesis (TG, XM, CX0, YJ0, CC, JL0), p. 28.
OOPSLA-2018-BielikFV #android #layout #relational #robust: Robust relational layout synthesis from examples for Android (PB, MF, MTV), p. 29.
OOPSLA-2018-WangWD #relational: Relational program synthesis (YW, XW, ID), p. 27.
PLDI-2018-FengMBD #learning #using: Program synthesis using conflict-driven learning (YF, RM, OB, ID), pp. 420–435.
PLDI-2018-LeeHAN #modelling #probability #search-based #using: Accelerating search-based program synthesis using learned probabilistic models (WL, KH, RA, MN), pp. 436–449.
POPL-2018-FarzanK #game studies #linear: Strategy synthesis for linear arithmetic games (AF, ZK), p. 30.
POPL-2018-KincaidCBR #invariant #reasoning: Non-linear reasoning for invariant synthesis (ZK, JC, JB, TWR), p. 33.
POPL-2018-TaLKC #automation #logic: Automated lemma synthesis in symbolic-heap separation logic (QTT, TCL, SCK, WNC), p. 29.
POPL-2018-WangDS #abstraction #refinement #using: Program synthesis using abstraction refinement (XW0, ID, RS), p. 30.
SAS-2018-Piskac #verification: New Applications of Software Synthesis: Verification of Configuration Files and Firewall Repair (RP), pp. 71–76.
ESEC-FSE-2018-RoyPDH #debugging #fault #tool support: Bug synthesis: challenging bug-finding tools with deep faults (SR, AP, BDG, YH), pp. 224–234.
ESEC-FSE-2018-SiLZAKN #datalog #source code: Syntax-guided synthesis of Datalog programs (XS, WL, RZ, AA, PK, MN), pp. 515–527.
ICSE-2018-LoncaricET #data type: Generalized data structure synthesis (CL, MDE, ET), pp. 958–968.
CAV-2018-AbateDKKP #induction #modulo theories: Counterexample Guided Inductive Synthesis Modulo Theories (AA, CD, PK, DK, EP), pp. 270–288.
CAV-2018-AkshayCGKS #functional #question #what: What's Hard About Boolean Functional Synthesis? (SA, SC, SG, SK, SS), pp. 251–269.
CAV-2018-AlbarghouthiH #constraints #proving: Constraint-Based Synthesis of Coupling Proofs (AA, JH), pp. 327–346.
CAV-2018-BansalNS #source code #specification: Synthesis of Asynchronous Reactive Programs from Temporal Specifications (SB, KSN, YS), pp. 367–385.
CAV-2018-FanMM0 #linear #specification: Controller Synthesis Made Real: Reach-Avoid Specifications and Linear Dynamics (CF, UM, SM, MV0), pp. 347–366.
CAV-2018-HuD: Syntax-Guided Synthesis with Quantitative Syntactic Objectives (QH, LD), pp. 386–403.
CAV-2018-MeyerSL #exclamation #named: Strix: Explicit Reactive Synthesis Strikes Back! (PJM, SS, ML), pp. 578–586.
CAV-2018-WangADM #abstraction #learning: Learning Abstractions for Program Synthesis (XW0, GA, ID, KLM), pp. 407–426.
CSL-2018-MadhusudanMS0 #decidability #higher-order #logic: A Decidable Fragment of Second Order Logic With Applications to Synthesis (PM, UM, SS, MV0), p. 19.
IJCAR-2018-HoAKMTN #monad: Proof-Producing Synthesis of CakeML with I/O and Local State from Monadic HOL Functions (SH, OA, RK, MOM, YKT, MN), pp. 646–662.
VMCAI-2018-PelegIS #interactive: Abstraction-Based Interaction Model for Synthesis (HP, SI, SS), pp. 382–405.
ECSA-2017-CamaraGS #product line #trade-off #verification: Synthesis and Quantitative Verification of Tradeoff Spaces for Families of Software Systems (JC, DG, BRS), pp. 3–21.
ICSA-2017-CalinescuCGKP #design #markov #parametricity #robust: Designing Robust Software Systems through Parametric Markov Chain Synthesis (RC, MC0, SG, MK, NP), pp. 131–140.
DLT-2017-Bruyere #approach #game studies: Computer Aided Synthesis: A Game-Theoretic Approach (VB), pp. 3–35.
FSCD-2017-PradicR #approach: A Curry-Howard Approach to Church's Synthesis (PP, CR), p. 16.
FDG-2017-ButlerSZ #generative: Program synthesis as a generative method (EB, KS, AZ), p. 10.
ICML-2017-EngelRRDNES: Neural Audio Synthesis of Musical Notes with WaveNet Autoencoders (JHE, CR, AR, SD, MN0, DE, KS), pp. 1068–1077.
ICML-2017-OdenaOS #classification #image: Conditional Image Synthesis with Auxiliary Classifier GANs (AO, CO, JS), pp. 2642–2651.
ECOOP-2017-MayerHK #recursion #string: Proactive Synthesis of Recursive Tree-to-String Functions from Examples (MM, JH, VK), p. 30.
OOPSLA-2017-QiuS: Natural synthesis of provably-correct data-structure manipulations (XQ, ASL), p. 28.
OOPSLA-2017-SrinivasanVR: Model-assisted machine-code synthesis (VS, AV, TWR), p. 26.
OOPSLA-2017-WangDS #automaton #finite #using: Synthesis of data completion scripts using finite tree automata (XW0, ID, RS), p. 26.
OOPSLA-2017-Yaghmazadeh0DD #named #natural language #query: SQLizer: query synthesis from natural language (NY, YW0, ID, TD), p. 26.
PLDI-2017-BeckettMMPW #network: Network configuration synthesis with abstract topologies (RB, RM, TDM, JP, DW), pp. 437–451.
PLDI-2017-FarzanN #divide and conquer #parallel: Synthesis of divide and conquer parallelism for loops (AF, VN), pp. 540–555.
PLDI-2017-FedyukovichAB #parallel #source code: Gradual synthesis for static parallelization of single-pass array-processing programs (GF, MBSA, RB), pp. 572–585.
PLDI-2017-FengMGDC #component: Component-based synthesis of table consolidation and transformation tasks from examples (YF, RM, JVG, ID, SC), pp. 422–436.
POPL-2017-FengM0DR #api #component: Component-based synthesis for complex APIs (YF, RM, YW0, ID, TWR), pp. 599–612.
ASE-2017-AbateBCCCDKKP #automation #named #physics: DSSynth: an automated digital controller synthesis tool for physical plants (AA, IB, DC, LCC, LCC, CD, PK, DK, EP), pp. 919–924.
ASE-2017-LeungL #ide #named #parsing: Parsimony: an IDE for example-guided synthesis of lexers and parsers (AL, SL), pp. 815–825.
ESEC-FSE-2017-LeCLGV #named #programming #semantics: S3: syntax- and semantic-guided repair synthesis via programming by examples (XBDL, DHC, DL0, CLG, WV), pp. 593–604.
ICSE-2017-XiongWYZH00 #precise #program repair: Precise condition synthesis for program repair (YX, JW, RY, JZ, SH, GH0, LZ0), pp. 416–426.
ASPLOS-2017-LustigWPG #automation #memory management #testing: Automated Synthesis of Comprehensive Memory Model Litmus Test Suites (DL, AW, AP, OG), pp. 661–675.
CASE-2017-ChoiPR #algorithm #automation #multi #scalability: Automated synthesis of scalable algorithms for inferring non-local properties to assist in multi-robot teaming (TC, TPP, AWR), pp. 1522–1527.
CASE-2017-WareS #abstraction #parallel: Time optimal synthesis based upon sequential abstraction and maximizing parallelism (SW, RS), pp. 926–931.
CAV-2017-AbateBCCDKKP #automation #physics: Automated Formal Synthesis of Digital Controllers for State-Space Physical Plants (AA, IB, DC, LCC, CD, PK, DK, EP), pp. 462–482.
CAV-2017-BenesBDPS #named #parallel #parametricity: Pithya: A Parallel Tool for Parameter Synthesis of Piecewise Multi-affine Dynamical Systems (NB, LB, MD, SP, DS), pp. 591–598.
CAV-2017-ChasinsP #data-driven #probability #source code: Data-Driven Synthesis of Full Probabilistic Programs (SC, PMP), pp. 279–304.
CAV-2017-Drachsler-Cohen: Synthesis with Abstract Examples (DDC, SS, EY), pp. 254–278.
CAV-2017-AlmagorKRV: Quantitative Assume Guarantee Synthesis (SA, OK, JOR, YV), pp. 353–374.
CAV-2017-CardelliCFKLPW #network: Syntax-Guided Optimal Synthesis for Chemical Reaction Networks (LC, MC0, MF, MZK, LL, NP, MW), pp. 375–395.
CAV-2017-El-HassanyTVV: Network-Wide Configuration Synthesis (AEH, PT, LV, MTV), pp. 261–281.
CAV-2017-FaymonvilleFT #bound #framework #named: BoSy: An Experimentation Framework for Bounded Synthesis (PF, BF, LT), pp. 325–332.
CAV-2017-GasconTCM #component #proving: Look for the Proof to Find the Program: Decorated-Component-Based Program Synthesis (AG, AT0, BC, UM), pp. 86–103.
CAV-2017-KhalimovB #bound: Bounded Synthesis for Streett, Rabin, and CTL* (AK, RB), pp. 333–352.
CAV-2017-McClurgHC #network #source code: Synchronization Synthesis for Network Programs (JM, HH, PC), pp. 301–321.
ICSME-2016-LeLG #empirical #program repair #semantics: Empirical Study on Synthesis Engines for Semantics-Based Program Repair (XBDL, DL0, CLG), pp. 423–427.
FM-2016-AstefanoaeiBBCR #composition #parametricity: Compositional Parameter Synthesis (LA, SB, MB, CHC, HR), pp. 60–68.
FSCD-2016-BenkeSC #first-order #functional #logic #source code: Synthesis of Functional Programs with Help of First-Order Intuitionistic Logic (MB, AS, DWC), p. 16.
IFM-2016-KorenciakRF: Extension of PRISM by Synthesis of Optimal Timeouts in Fixed-Delay CTMC (LK, VR, AF), pp. 130–138.
SEFM-2016-BezdekBBC #automaton #ltl #parametricity: LTL Parameter Synthesis of Parametric Timed Automata (PB, NB, JB, IC), pp. 172–187.
CIKM-2016-ShaabaniASS #named #tool support: MIST: Missing Person Intelligence Synthesis Toolkit (ES, HA, PS, JEKS), pp. 1843–1867.
ICML-2016-ReedAYLSL #generative #image: Generative Adversarial Text to Image Synthesis (SER, ZA, XY, LL, BS, HL), pp. 1060–1069.
ICML-2016-UlyanovLVL #image #network: Texture Networks: Feed-forward Synthesis of Textures and Stylized Images (DU, VL, AV, VSL), pp. 1349–1357.
ICPR-2016-LiuGX #constraints #network: Texture synthesis through convolutional neural networks and spectrum constraints (GL0, YG, GSX), pp. 3234–3239.
ICPR-2016-TairaTO #learning #robust: Robust feature matching by learning descriptor covariance with viewpoint synthesis (HT, AT, MO), pp. 1953–1958.
BX-2016-SemerathDHV #co-evolution #logic #modelling #satisfiability #using: Change Propagation of View Models by Logic Synthesis using SAT solvers (OS, CD, ÁH0, DV), pp. 40–44.
MoDELS-2016-Kosiuczenko #contract #on the #protocol #state machine: On the synthesis of protocol state machines from contracts (PK), pp. 76–85.
OOPSLA-2016-SamakTR #concurrent: Directed synthesis of failing concurrent executions (MS, OT, MKR), pp. 430–446.
OOPSLA-2016-SrinivasanSR: Speeding up machine-code synthesis (VS, TS, TWR), pp. 165–180.
OOPSLA-2016-SurendranS #automation #parallel: Automatic parallelization of pure method calls via conditional future synthesis (RS, VS), pp. 20–38.
LOPSTR-2016-Alpuente0V #contract #framework: Symbolic Abstract Contract Synthesis in a Rewriting Framework (MA, DP0, AV), pp. 187–202.
PLDI-2016-AchourSR #programmable: Configuration synthesis for programmable analog devices with Arco (SA, RS, MCR), pp. 177–193.
PLDI-2016-HeuleS0A #automation #learning #set: Stratified synthesis: automatically learning the x86-64 instruction set (SH, ES, RS0, AA), pp. 237–250.
PLDI-2016-LoncaricTE #performance: Fast synthesis of fast collections (CL, ET, MDE), pp. 355–368.
PLDI-2016-PolikarpovaKS #polymorphism #refinement: Program synthesis from polymorphic refinement types (NP, IK, ASL), pp. 522–538.
PLDI-2016-SmithA #pipes and filters: MapReduce program synthesis (CS, AA), pp. 326–340.
POPL-2016-AlbarghouthiDG #specification: Maximal specification synthesis (AA, ID, AG), pp. 789–801.
POPL-2016-BornholtTGC #optimisation #sketching: Optimizing synthesis with metasketches (JB, ET, DG, LC), pp. 775–788.
POPL-2016-FrankleOWZ: Example-directed synthesis: a type-theoretic interpretation (JF, PMO, DW, SZ), pp. 802–815.
POPL-2016-Murray #hybrid: Synthesis of reactive controllers for hybrid systems (keynote) (RMM), p. 3.
SAS-2016-KojimaKS #invariant #performance: Generalized Homogeneous Polynomials for Efficient Template-Based Nonlinear Invariant Synthesis (KK, MK, KS), pp. 278–299.
ASE-2016-GuSMLS #automation #fault #runtime: Automatic runtime recovery via error handler synthesis (TG, CS, XM, JL, ZS), pp. 684–695.
FSE-2016-Alexandru #network #using: Guided code synthesis using deep neural networks (CVA), pp. 1068–1070.
FSE-2016-Loncaric #data type: Data structure synthesis (CL), pp. 1073–1075.
ICSE-2016-ChenHLLTWW #verification: PAC learning-based verification and model synthesis (YFC, CH, OL, TJL, MHT, BYW, FW), pp. 714–724.
ICSE-2016-DesaiGHJKMRR #natural language #using: Program synthesis using natural language (AD, SG, VH, NJ, AK, MM, SR, SR), pp. 345–356.
ICSE-2016-MechtaevYR #analysis #multi #named #scalability: Angelix: scalable multiline program patch synthesis via symbolic analysis (SM, JY, AR), pp. 691–701.
ICSE-2016-OmariSY: Cross-supervised synthesis of web-crawlers (AO, SS, EY), pp. 368–379.
ICSE-2016-RaghothamanWH #code search #named #what: SWIM: synthesizing what i mean: code search and idiomatic snippet synthesis (MR, YW, YH), pp. 357–367.
CASE-2016-KussPHDH #architecture #industrial #overview: Manufacturing knowledge for industrial robot systems: Review and synthesis of model architecture (AK, JRDP, RH, TD, MH), pp. 348–354.
CASE-2016-MavrommatiM #automation #policy: Automatic synthesis of control alphabet policies (AM, TDM), pp. 313–320.
CC-2016-NgY #concurrent #detection #graph: Static deadlock detection for concurrent go by global session graph synthesis (NN, NY), pp. 174–184.
CAV-2016-BloemBJ #distributed #self: Synthesis of Self-Stabilising and Byzantine-Resilient Distributed Systems (RB, NBS, SJ), pp. 157–176.
CAV-2016-ChengHR #specification: Structural Synthesis for GXW Specifications (CHC, YH, HR), pp. 95–117.
CAV-2016-FinkbeinerK #bound: Bounded Cycle Synthesis (BF, FK0), pp. 118–135.
CAV-2016-KlenzeBH #flexibility #performance #smt: Fast, Flexible, and Minimal CTL Synthesis via SMT (TK, SB, AJH), pp. 136–156.
CAV-2016-AlurMT #composition #multi: Compositional Synthesis of Reactive Controllers for Multi-agent Systems (RA, SM, UT), pp. 251–269.
CAV-2016-EhlersR #named: Slugs: Extensible GR(1) Synthesis (RE, VR), pp. 333–339.
CAV-2016-EldibWW #encryption: Synthesis of Fault-Attack Countermeasures for Cryptographic Circuits (HE, MW, CW0), pp. 343–363.
CAV-2016-FriedTV #functional: BDD-Based Boolean Functional Synthesis (DF, LMT, MYV), pp. 402–421.
CAV-2016-JordanSS #named: Soufflé: On Synthesis of Program Analyzers (HJ, BS, PS), pp. 422–430.
CAV-2016-LeggNR #bound #satisfiability: A SAT-Based Counterexample Guided Method for Unbounded Synthesis (AL, NN, LR), pp. 364–382.
CSL-2016-AlmagorK #probability: High-Quality Synthesis Against Stochastic Environments (SA, OK), p. 17.
CSL-2016-Muscholl #automation #distributed: Automated Synthesis: Going Distributed (AM), p. 2.
IJCAR-2016-GanDXZKC #polynomial: Interpolant Synthesis for Quadratic Polynomial Inequalities and Combination with EUF (TG, LD, BX, NZ, DK, MC), pp. 195–212.
VMCAI-2016-CrescenzoT #automaton #composition #problem: A General Modular Synthesis Problem for Pushdown Systems (IDC, SLT), pp. 495–513.
VMCAI-2016-DelahayeLP #markov #parametricity: Parameter Synthesis for Parametric Interval Markov Chains (BD, DL, LP), pp. 372–390.
DocEng-2015-VernicaV #adaptation #framework #layout #named #web: AERO: An Extensible Framework for Adaptive Web Layout Synthesis (RV, NDV), pp. 187–190.
VLDB-2015-HeCMPS #named #using: DPT: Differentially Private Trajectory Synthesis Using Hierarchical Reference Systems (XH, GC, AM, CMP, DS), pp. 1154–1165.
ICALP-v1-2015-KariKMPS #np-hard #set: Binary Pattern Tile Set Synthesis Is NP-hard (LK, SK, PÉM, MJP, SS), pp. 1022–1034.
ICALP-v2-2015-Chatterjee0V #complexity #component #probability: The Complexity of Synthesis from Probabilistic Components (KC, LD, MYV), pp. 108–120.
ICALP-v2-2015-Muscholl #automation #distributed: Automated Synthesis of Distributed Controllers (AM), pp. 11–27.
LATA-2015-AutiliIMST #automation #specification: Automated Synthesis of Application-Layer Connectors from Automata-Based Specifications (MA, PI, FM, RS, MT), pp. 3–24.
FM-2015-DangDP #logic #parametricity #specification: Parameter Synthesis Through Temporal Logic Specifications (TD, TD, CP), pp. 213–230.
TLCA-2015-BessaiDDCdR #composition #mixin: Mixin Composition Synthesis Based on Intersection Types (JB, AD, BD, TCC, Ud, JR), pp. 76–91.
ICFP-2015-Bodik: Program synthesis: opportunities for the next decade (RB), p. 1.
HIMI-IKD-2015-PiconeP #architecture: A New Information Architecture: A Synthesis of Structure, Flow, and Dialectic (RARP, BP), pp. 320–331.
SPLC-2015-BecanBGA #feature model #modelling: Synthesis of attributed feature models from product descriptions (GB, RB, AG, MA), pp. 1–10.
SPLC-2015-HeinemanHDR #framework #migration #object-oriented #product line #towards: Towards migrating object-oriented frameworks to enable synthesis of product line members (GTH, AH, BD, JR), pp. 56–60.
SPLC-2015-SteffenLM #constraints #product line: User-level synthesis: treating product lines as systems of constraints (BS, ALL, TMS), pp. 427–431.
Onward-2015-BarmanBCTBC #interactive #tool support #towards: Toward tool support for interactive synthesis (SB, RB, SC, ET, AB, DC), pp. 121–136.
OOPSLA-2015-HottelierB #constraints #layout #relational: Synthesis of layout engines from relational constraints (TH, RB), pp. 74–88.
OOPSLA-2015-PolozovG #framework #induction #named: FlashMeta: a framework for inductive program synthesis (OP, SG), pp. 107–126.
PLDI-2015-GonnordMR #ranking #using: Synthesis of ranking functions using extremal counterexamples (LG, DM, GR), pp. 608–618.
PLDI-2015-LeungSL #interactive #parsing: Interactive parser synthesis by example (AL, JS, SL), pp. 565–574.
PLDI-2015-McClurgHCF #network #performance: Efficient synthesis of network updates (JM, HH, PC, NF), pp. 196–207.
PLDI-2015-NoriORV #performance #probability #source code: Efficient synthesis of probabilistic programs (AVN, SO, SKR, DV), pp. 208–217.
PLDI-2015-OseraZ: Type-and-example-directed program synthesis (PMO, SZ), pp. 619–630.
PLDI-2015-SrinivasanR #semantics: Synthesis of machine code from semantics (VS, TWR), pp. 596–607.
POPL-2015-CochranDLMV: Program Boosting: Program Synthesis via Crowd-Sourcing (RAC, LD, BL, DM, MV), pp. 677–688.
POPL-2015-DelawarePGC #data type #deduction #named #proving: Fiat: Deductive Synthesis of Abstract Data Types in a Proof Assistant (BD, CPC, JG, AC), pp. 689–700.
ASE-2015-GerasimouTC #modelling #probability #re-engineering #search-based: Search-Based Synthesis of Probabilistic Models for Quality-of-Service Software Engineering (T) (SG, GT, RC), pp. 319–330.
ESEC-FSE-2015-LongR #program repair #staged: Staged program repair with condition synthesis (FL, MR), pp. 166–178.
ESEC-FSE-2015-MaozR #ltl #specification: GR(1) synthesis for LTL specification patterns (SM, JOR), pp. 96–106.
ICSE-v2-2015-GulwaniMNP #live programming #named #programming: StriSynth: Synthesis for Live Programming (SG, MM, FN, RP), pp. 701–704.
ICSE-v2-2015-GveroK #interactive #query #using: Interactive Synthesis Using Free-Form Queries (TG, VK), pp. 689–692.
SAC-2015-Khenfri #approach #architecture #optimisation: A holistic optimization approach for the synthesis of AUTOSAR E/E architecture (FK), pp. 1960–1961.
GPCE-2015-ByalikCT #automation #named #platform #programming: Native-2-native: automated cross-platform code synthesis from web-based programming resources (AB, SC, ET), pp. 99–108.
CASE-2015-ChengHL #automation #petri net #robust #using: Robust supervisor synthesis for automated manufacturing systems using Petri nets (YC, HH, YL), pp. 1029–1035.
CASE-2015-HuangHCC #performance: Efficient grasp synthesis and control strategy for robot hand-arm system (MBH, HPH, CCC, CAC), pp. 1256–1257.
CASE-2015-LuoZHZ #modelling: Discrete-event controller synthesis based on state space models (JL, QZ, YSH, MZ), pp. 87–92.
CASE-2015-MarkovskiH #framework #manycore #question: Is multicore supervisory controller synthesis in the Ramadge-Wonham framework feasible? (JM, HH), pp. 521–525.
CASE-2015-WareS #using: Synthesis time optimal accepting traces using language projection and pruning (SW, RS), pp. 1363–1368.
DAC-2015-BadrTG #hybrid: Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias (YB, AT, PG), p. 6.
DAC-2015-CampbellLMC #debugging #detection #fault #hybrid #using #validation: Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles (KAC, DL, SM, DC), p. 6.
DAC-2015-CampbellVPC #detection #fault #low cost: High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths (KAC, PV, DZP, DC), p. 6.
DAC-2015-LiLSH #approximate #optimisation #precise: Joint precision optimization and high level synthesis for approximate computing (CL, WL, SSS, JH), p. 6.
DAC-2015-SonghoriHSK #logic #nearest neighbour #privacy #using: Compacting privacy-preserving k-nearest neighbor search using logic synthesis (EMS, SUH, ARS, FK), p. 6.
DAC-2015-SumbulVZFP #design #in memory: A synthesis methodology for application-specific logic-in-memory designs (HES, KV, QZ, FF, LP), p. 6.
DAC-2015-TatsuokaWOHZOLT #design: Physically aware high level synthesis design flow (MT, RW, TO, TH, QZ, RO, XL, TT), p. 6.
DAC-2015-TenaceCMP #logic: One-pass logic synthesis for graphene-based Pass-XNOR logic circuits (VT, AC, EM, MP), p. 6.
DAC-2015-TsengLHS: Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping (TMT, BL, TYH, US), p. 6.
DAC-2015-ZhaoTDZ #pipes and filters: Area-efficient pipelining for FPGA-targeted high-level synthesis (RZ, MT, SD, ZZ), p. 6.
DATE-2015-BiewerAGSH #approach #coordination #realtime: A symbolic system synthesis approach for hard real-time systems based on coordinated SMT-solving (AB, BA, JG, TS, CH), pp. 357–362.
DATE-2015-BurnsSY #modelling #verification: GALS synthesis and verification for xMAS models (FPB, DS, AY), pp. 1419–1424.
DATE-2015-FernandoWNKC #agile #algorithm #design #using: (AS)2: accelerator synthesis using algorithmic skeletons for rapid design space exploration (SF, MW, CN, AK, HC), pp. 305–308.
DATE-2015-HadjisCSHTA #multi: Profiling-driven multi-cycling in FPGA high-level synthesis (SH, AC, RS, YHA, HT, JA), pp. 31–36.
DATE-2015-JiaoMD #reasoning: Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications (FJ, SM, AD), pp. 1144–1149.
DATE-2015-KhanhSKA #dependence #design: Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis (PNK, AKS, AK, KMMA), pp. 157–162.
DATE-2015-ZhaoQ #design #probability: A general design of stochastic circuit and its synthesis (ZZ, WQ), pp. 1467–1472.
FASE-2015-BrennerGS #distributed #on the fly #specification: On-the-Fly Synthesis of Scarcely Synchronizing Distributed Controllers from Scenario-Based Specifications (CB, JG, WS), pp. 51–65.
FoSSaCS-2015-Mamouras #hoare #logic #nondeterminism: Synthesis of Strategies and the Hoare Logic of Angelic Nondeterminism (KM), pp. 25–40.
TACAS-2015-AlurMT #refinement #specification: Pattern-Based Refinement of Assume-Guarantee Specifications in Reactive Synthesis (RA, SM, UT), pp. 501–516.
TACAS-2015-BassetKTW #game studies #multi #probability: Strategy Synthesis for Stochastic Games with Multiple Long-Run Objectives (NB, MZK, UT, CW), pp. 256–271.
TACAS-2015-BloemCJK #concurrent #source code: Assume-Guarantee Synthesis for Concurrent Reactive Programs with Partial Information (RB, KC, SJ, RK), pp. 517–532.
TACAS-2015-BloemKKW #runtime: Shield Synthesis: — Runtime Enforcement for Reactive Systems (RB, BK, RK, CW), pp. 533–548.
TACAS-2015-BrazdilCFK #multi #named: MultiGain: A Controller Synthesis Tool for MDPs with Multiple Mean-Payoff Objectives (TB, KC, VF, AK), pp. 181–187.
CADE-2015-TiwariGD #using: Program Synthesis Using Dual Interpretation (AT, AG, BD), pp. 482–497.
CAV-2015-DehnertJJCVBKA #named #parametricity #probability: PROPhESY: A PRObabilistic ParamEter SYnthesis Tool (CD, SJ, NJ, FC, MV, HB, JPK, EÁ), pp. 214–231.
CAV-2015-FinkbeinerGO #distributed #named: Adam: Causality-Based Synthesis of Distributed Systems (BF, MG, ERO), pp. 433–439.
CAV-2015-AlurCR #unification: Synthesis Through Unification (RA, PC, AR), pp. 163–179.
CAV-2015-CernyCHRRST #scheduling #using: From Non-preemptive to Preemptive Scheduling Using Synchronization Synthesis (PC, EMC, TAH, AR, LR, RS, TT), pp. 180–197.
CAV-2015-JeonQSF #adaptation #parallel: Adaptive Concretization for Parallel Program Synthesis (JJ, XQ, ASL, JSF), pp. 377–394.
CAV-2015-ReynoldsDKTB #quantifier #smt: Counterexample-Guided Quantifier Instantiation for Synthesis in SMT (AR, MD, VK, CT, CWB), pp. 198–216.
VMCAI-2015-AdjeG #automation #invariant #linear #polynomial #source code: Automatic Synthesis of Piecewise Linear Quadratic Invariants for Programs (AA, PLG), pp. 99–116.
ECSA-2014-XuL #architecture #co-evolution: Co-evolving Pattern Synthesis and Class Responsibility Assignment in Architectural Synthesis (YX, PL), pp. 74–81.
LATA-2014-BerardC #revisited: Channel Synthesis Revisited (BB, OC), pp. 149–160.
FM-2014-DammF #automation #composition #distributed: Automatic Compositional Synthesis of Distributed Systems (WD, BF), pp. 179–193.
FM-2014-LinH #composition #concurrent #learning #model checking: Compositional Synthesis of Concurrent Systems through Causal Model Checking and Learning (SWL, PAH), pp. 416–431.
ICGT-2014-KreowskiKLL #evaluation #generative #graph transformation: Graph Transformation Meets Reversible Circuits: Generation, Evaluation, and Synthesis (HJK, SK, AL, ML), pp. 237–252.
CSCW-2014-AndreKD #category theory #clustering: Crowd synthesis: extracting categories and clusters from complex data (PA, AK, SPD), pp. 989–998.
ICEIS-v2-2014-PfisterHN #agile #concurrent #design #diagrams #framework #metamodelling #modelling #towards #visual notation: A Framework for Concurrent Design of Metamodels and Diagrams — Towards an Agile Method for the Synthesis of Domain Specific Graphical Modeling Languages (FP, MH, CN), pp. 298–306.
ICPR-2014-GeXYS #image #using: Image Completion Using Global Patch Matching and Optimal Seam Synthesis (SG, KX, RY, ZS), pp. 871–876.
ICPR-2014-HouHW #modelling #video: Cloud Model-Based Dynamic Texture Synthesis for Video Coding (ZH, RH, ZW), pp. 838–842.
ICPR-2014-MoeiniMF14a #2d #3d #image #invariant #re-engineering #recognition: Pose-Invariant Facial Expression Recognition Based on 3D Face Reconstruction and Synthesis from a Single 2D Image (AM, HM, KF), pp. 1746–1751.
SEKE-2014-XuL #approach #architecture #automation #using: Automated Software Architectural Synthesis using Patterns: A Cooperative Coevolution Approach (YX, PL), pp. 174–180.
OOPSLA-2014-SamakR #concurrent #detection #parallel #thread: Multithreaded test synthesis for deadlock detection (MS, MKR), pp. 473–489.
LOPSTR-2014-Balaniuk #induction: Drill and Join: A Method for Exact Inductive Program Synthesis (RB), pp. 219–237.
LOPSTR-2014-TahatE #hybrid #protocol #self #verification: A Hybrid Method for the Verification and Synthesis of Parameterized Self-Stabilizing Protocols (AT, AE), pp. 201–218.
PLDI-2014-PerelmanGGP #testing: Test-driven synthesis (DP, SG, DG, PP), p. 43.
POPL-2014-ChaudhuriCS #proving #using: Bridging boolean and quantitative synthesis using smoothed proof search (SC, MC, ASL), pp. 207–220.
SAS-2014-MeshmanDVY #memory management #refinement: Synthesis of Memory Fences via Refinement Propagation (YM, AMD, MTV, EY), pp. 237–252.
ASE-2014-CosmoLTZZEA #automation #deployment: Automated synthesis and deployment of cloud applications (RDC, ML, RT, SZ, JZ, AE, AA), pp. 211–222.
FSE-2014-GoffiGMPT #search-based #sequence: Search-based synthesis of equivalent method sequences (AG, AG, AM, MP, PT), pp. 366–376.
FSE-2014-JiangZZZLSSGS #embedded #modelling #multi #named #tool support #validation: Tsmart-GalsBlock: a toolkit for modeling, validation, and synthesis of multi-clocked embedded systems (YJ, HZ, HZ, XZ, HL, CS, XS, MG, JGS), pp. 711–714.
ICSE-2014-GalensonRBHS #interactive #named: CodeHint: dynamic and interactive synthesis of code snippets (JG, PR, RB, BH, KS), pp. 653–663.
ICSE-2014-KaleeswaranTKO #automation #named: MintHint: automated synthesis of repair hints (SK, VT, AK, AO), pp. 266–276.
CASE-2014-ZhaoUH #divide and conquer #flexibility: A divide-and-conquer method for the synthesis of non-blocking supervisors for flexible manufacturing systems (MZ, MU, YH), pp. 455–460.
DAC-2014-ChuangLJ #hybrid: Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits (CCC, YHL, JHRJ), p. 6.
DAC-2014-CuiMSW #detection #hardware #runtime: High-Level Synthesis for Run-Time Hardware Trojan Detection and Recovery (XC, KM, LS, KW), p. 6.
DAC-2014-DaiTHZ #pipes and filters: Flushing-Enabled Loop Pipelining for High-Level Synthesis (SD, MT, KH, ZZ), p. 6.
DAC-2014-ElbayoumiCKSHE #algorithm #named #parallel: TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis (ME, MC, VNK, AS, MSH, MYE), p. 6.
DAC-2014-GuglielmoPC #composition #design: A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs (GDG, CP, LPC), p. 6.
DAC-2014-KeszoczeWHD: Exact One-pass Synthesis of Digital Microfluidic Biochips (OK, RW, TYH, RD), p. 6.
DAC-2014-LinWC #data mining #design #logic #mining #named #power management: C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs (CHL, LW, DC), p. 6.
DAC-2014-ShiBSBC #online #trade-off: Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs (KS, DB, EAS, SB, GAC), p. 6.
DAC-2014-WangOC #optimisation #performance #polynomial: Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization (YW, MO, CC), p. 6.
DAC-2014-YangHCLRX #behaviour #certification #framework #scalability: Scalable Certification Framework for Behavioral Synthesis Front-End (ZY, KH, KC, LL, SR, FX), p. 6.
DATE-2014-ChenCH #array #configuration management #constraints: Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints (YHC, JYC, JDH), pp. 1–4.
DATE-2014-CilardoFGM #communication #manycore #scheduling: Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems (AC, EF, LG, AM), pp. 1–4.
DATE-2014-DimitrakopoulosSPTMC #hardware #parallel #thread: Hardware primitives for the synthesis of multithreaded elastic systems (GD, IS, AP, KT, PMM, JC), pp. 1–4.
DATE-2014-EckerVZG #approach #metamodelling: The metamodeling approach to system level synthesis (WE, MV, LZ, AG), pp. 1–2.
DATE-2014-FerentD #comparison #mining #novel #using: Novel circuit topology synthesis method using circuit feature mining and symbolic comparison (CF, AD), pp. 1–4.
DATE-2014-HaoRX #behaviour #equivalence #pipes and filters: Equivalence checking for function pipelining in behavioral synthesis (KH, SR, FX), pp. 1–6.
DATE-2014-KauerSGCA #distributed #embedded #fault tolerance #verification: Fault-tolerant control synthesis and verification of distributed embedded systems (MK, DS, DG, SC, AMA), pp. 1–6.
DATE-2014-LiuCHWCDN #array: Width minimization in the Single-Electron Transistor array synthesis (CWL, CEC, CYH, CYW, YCC, SD, VN), pp. 1–4.
DATE-2014-Matsunaga #algorithm #generative #parallel: Synthesis algorithm of parallel index generation units (YM), pp. 1–6.
DATE-2014-MeeusS #automation #reuse: Automating data reuse in High-Level Synthesis (WM, DS), pp. 1–4.
DATE-2014-NepalLBR #approximate #automation #behaviour #named: ABACUS: A technique for automated behavioral synthesis of approximate computing circuits (KN, YL, RIB, SR), pp. 1–6.
DATE-2014-ParkKK #design #multi: Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs (KP, GK, TK), pp. 1–4.
DATE-2014-PuEMG #logic #power management #scalability: Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling (YP, JDE, MM, JPdG), pp. 1–2.
DATE-2014-RanjanRVRR #approximate #named: ASLAN: Synthesis of approximate sequential circuits (AR, AR, SV, KR, AR), pp. 1–6.
OSDI-2014-RyzhykWKLRSV: User-Guided Device Driver Synthesis (LR, AW, JK, AL, AR, MS, MV), pp. 661–676.
ESOP-2014-DudderMR #composition #staged: Staged Composition Synthesis (BD, MM, JR), pp. 67–86.
FoSSaCS-2014-AlmagorK: Latticed-LTL Synthesis in the Presence of Noisy Inputs (SA, OK), pp. 226–241.
TACAS-2014-DragerFKPU #probability: Permissive Controller Synthesis for Probabilistic Systems (KD, VF, MZK, DP, MU), pp. 531–546.
TACAS-2014-HuangM #semantics #specification: Symbolic Synthesis for Epistemic Specifications with Observational Semantics (XH, RvdM), pp. 455–469.
TACAS-2014-LiSSS: Synthesis for Human-in-the-Loop Control Systems (WL, DS, SSS, SAS), pp. 470–484.
CAV-2014-BozianuDF #specification: Safraless Synthesis for Epistemic Temporal Specifications (RB, CD, EF), pp. 441–456.
CAV-2014-CernyHRRT #concurrent: Regression-Free Synthesis for Concurrency (PC, TAH, AR, LR, TT), pp. 568–584.
CAV-2014-DilligDC #memory management #safety: Optimal Guard Synthesis for Memory Safety (TD, ID, SC), pp. 491–507.
CAV-2014-EldibW: Synthesis of Masking Countermeasures against Side Channel Attacks (HE, CW), pp. 114–130.
LICS-CSL-2014-Velner #multi #robust: Finite-memory strategy synthesis for robust multidimensional mean-payoff objectives (YV), p. 10.
VMCAI-2014-BloemKS #safety #satisfiability #specification: SAT-Based Synthesis Methods for Safety Specs (RB, RK, MS), pp. 1–20.
VMCAI-2014-EhlersSK #identifier: Synthesis with Identifiers (RE, SAS, HKG), pp. 415–433.
VMCAI-2014-LeikeT #polynomial #source code: Synthesis for Polynomial Lasso Programs (JL, AT), pp. 434–452.
VMCAI-2014-LopesM #compilation #optimisation: Weakest Precondition Synthesis for Compiler Optimizations (NPL, JM), pp. 203–221.
VMCAI-2014-SinghSXKS #composition #modelling #sketching #using: Modular Synthesis of Sketches Using Models (RS, RS, ZX, RK, ASL), pp. 395–414.
ICDAR-2013-DingsAE13a #approach #modelling: An Approach for Arabic Handwriting Synthesis Based on Active Shape Models (LD, AAH, ME), pp. 1260–1264.
SIGMOD-2013-KlonatosNSKK #algorithm #automation: Automatic synthesis of out-of-core algorithms (YK, AN, AS, CK, VK), pp. 133–144.
VLDB-2013-BellareCMMRS #framework #knowledge base #multitenancy #named #platform #scalability: WOO: A Scalable and Multi-tenant Platform for Continuous Knowledge Base Synthesis (KB, CC, AM, PM, MR, AS), pp. 1114–1125.
ICALP-v2-2013-DenielouY #automaton #communication #multi: Multiparty Compatibility in Communicating Automata: Characterisation and Synthesis of Global Session Types (PMD, NY), pp. 174–186.
SEFM-2013-BennaceurCIJ #automation #behaviour #ontology #reasoning: Automated Mediator Synthesis: Combining Behavioural and Ontological Reasoning (AB, CC, MI, BJ), pp. 274–288.
MLDM-2013-KokkulaM #classification #detection #topic: Classification and Outlier Detection Based on Topic Based Pattern Synthesis (SK, NMM), pp. 99–114.
SEKE-2013-MaghrabyR: Argumentation Understood as Program Synthesis (AM, DR), pp. 681–684.
MoDELS-2013-GreenyerK #composition #specification: Compositional Synthesis of Controllers from Scenario-Based Assume-Guarantee Specifications (JG, EK), pp. 774–789.
OOPSLA-2013-KneussKKS #recursion: Synthesis modulo recursive functions (EK, IK, VK, PS), pp. 407–426.
OOPSLA-2013-RaychevSSV #refactoring: Refactoring with synthesis (VR, MS, MS, MTV), pp. 339–354.
PLDI-2013-CheungSM #optimisation #query: Optimizing database-backed applications with query synthesis (AC, ASL, SM), pp. 3–14.
POPL-2013-KoksalPSBFP #biology #modelling: Synthesis of biological models from mutation experiments (ASK, YP, SS, RB, JF, NP), pp. 469–482.
SAS-2013-RaychevVY #automation #concurrent: Automatic Synthesis of Deterministic Concurrency (VR, MTV, EY), pp. 283–303.
ESEC-FSE-2013-MaozRR #component #modelling: Synthesis of component and connector models from crosscutting structural views (SM, JOR, BR), pp. 444–454.
ICSE-2013-BrabermanDPSU #modelling: Controller synthesis: from modelling to enactment (VAB, ND, NP, DS, SU), pp. 1347–1350.
ICSE-2013-InverardiT #automation #composition #protocol: Automatic synthesis of modular connectors via composition of protocol mediation patterns (PI, MT), pp. 3–12.
ICSE-2013-LetierH #automaton #modelling #requirements: Requirements modelling by synthesis of deontic input-output automata (EL, WH), pp. 592–601.
ICSE-2013-TanA00DC #composition: Dynamic synthesis of local time requirement for service composition (THT, ÉA, JS, YL, JSD, MC), pp. 542–551.
CASE-2013-HuZL #automation #performance #petri net #using: Supervisor synthesis and performance improvement for automated manufacturing systems by using Petri nets (HH, MZ, YL), pp. 1139–1144.
CASE-2013-JiangSCBG: Moving trajectories and controller synthesis for an assistive device for arm rehabilitation (LJ, RS, MHMC, LEB, GG), pp. 268–273.
CASE-2013-LinG #detection #framework #network #optimisation: Synthesis and optimization of a Bayesian belief network based observation platform for anomaly detection under partial and unreliable observations (WCL, HEG), pp. 51–58.
CASE-2013-Markovski #analysis: Synthesis and analysis of supervisory controllers for time-abstracted discrete-event systems (JM), pp. 1075–1082.
DAC-2013-AlleMD #analysis #dependence #pipes and filters #runtime: Runtime dependency analysis for loop pipelining in high-level synthesis (MA, AM, SD), p. 10.
DAC-2013-AmaruGM #composition #logic #named: BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition (LGA, PEG, GDM), p. 6.
DAC-2013-BombieriLFC #c++: A method to abstract RTL IP blocks into C++ code and enable high-level synthesis (NB, HYL, FF, LPC), p. 9.
DAC-2013-LiuC #on the: On learning-based methods for design-space exploration with high-level synthesis (HYL, LPC), p. 7.
DAC-2013-NacciRBSBA #algorithm #implementation: A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices (AAN, VR, FB, DS, IB, DA), p. 6.
DAC-2013-RoyCPP #parallel #towards #trade-off: Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures (SR, MRC, RP, DZP), p. 8.
DAC-2013-TuJ #feedback: Synthesis of feedback decoders for initialized encoders (KHT, JHRJ), p. 6.
DAC-2013-TurakhiaRGM #architecture #multi #named: HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors (YT, BR, SG, DM), p. 7.
DAC-2013-WangLZZC #array #clustering #memory management #multi: Memory partitioning for multidimensional arrays in high-level synthesis (YW, PL, PZ, CZ, JC), p. 8.
DAC-2013-YangRHX #behaviour #design #equivalence #implementation #optimisation: Handling design and implementation optimizations in equivalence checking for behavioral synthesis (ZY, SR, KH, FX), p. 6.
DATE-2013-AliasDP #kernel #optimisation: Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA (CA, AD, AP), pp. 575–580.
DATE-2013-AmaruGM #canonical #logic #novel: Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits (LGA, PEG, GDM), pp. 1014–1017.
DATE-2013-BarrioHMMM #multi: Multispeculative additive trees in high-level synthesis (AADB, RH, SOM, JMM, MCM), pp. 188–193.
DATE-2013-CanisAB #multi #reduction: Multi-pumping for resource reduction in FPGA high-level synthesis (AC, JHA, SDB), pp. 194–197.
DATE-2013-CastellanaF #analysis #independence #liveness #scheduling: Scheduling independent liveness analysis for register binding in high level synthesis (VGC, FF), pp. 1571–1574.
DATE-2013-ChenLSCCAN #embedded #modelling: High-level modeling and synthesis for embedded FPGAs (XC, SL, JS, TC, AC, GA, TGN), pp. 1565–1570.
DATE-2013-ChiangTWHCDN #array #configuration management #on the #order #using: On reconfigurable single-electron transistor arrays synthesis using reordering techniques (CEC, LFT, CYW, CYH, YCC, SD, VN), pp. 1807–1812.
DATE-2013-HeLLHY #streaming: Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications (XH, SL, YL, XSH, HY), pp. 992–995.
DATE-2013-KloosM: Supervisor synthesis for controller upgrades (JK, RM), pp. 1105–1110.
DATE-2013-KondratyevLMW #evaluation: Share with care: a quantitative evaluation of sharing approaches in high-level synthesis (AK, LL, MM, YW), pp. 1547–1552.
DATE-2013-RenPRKWEK #performance: Intuitive ECO synthesis for high performance circuits (HR, RP, LNR, SK, CW, JE, JK), pp. 1002–1007.
DATE-2013-ShafaeiSP #logic: Reversible logic synthesis of k-input, m-output lookup tables (AS, MS, MP), pp. 1235–1240.
DATE-2013-TodorovMRS #approach #clustering: A spectral clustering approach to application-specific network-on-chip synthesis (VT, DMG, HR, US), pp. 1783–1788.
DATE-2013-XydisPZS #architecture #compilation #framework #metamodelling #parametricity: A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization (SX, GP, VZ, CS), pp. 659–664.
DATE-2013-ZhaoOX #process: Profit maximization through process variation aware high level synthesis with speed binning (MZ, AO, CJX), pp. 176–181.
PPoPP-2013-BartheCKGM #relational #verification: From relational verification to SIMD loop synthesis (GB, JMC, SG, CK, MM), pp. 123–134.
PPoPP-2013-MeyerovichTAB #attribute grammar #parallel: Parallel schedule synthesis for attribute grammars (LAM, MET, EA, RB), pp. 187–196.
FASE-2013-AutiliRSIT #modelling #process: A Model-Based Synthesis Process for Choreography Realizability Enforcement (MA, DDR, ADS, PI, MT), pp. 37–52.
TACAS-2013-BohyBFR #ltl #specification: Synthesis from LTL Specifications with Mean-Payoff Objectives (AB, VB, EF, JFR), pp. 169–184.
TACAS-2013-JovanovicLR #automaton #integer #parametricity: Integer Parameter Synthesis for Timed Automata (AJ, DL, OHR), pp. 401–415.
TACAS-2013-LiDDMS #abduction #composition #proving: Synthesis of Circular Compositional Program Proofs via Abduction (BL, ID, TD, KLM, MS), pp. 370–384.
CAV-2013-AlbarghouthiGK #recursion: Recursive Program Synthesis (AA, SG, ZK), pp. 934–950.
CAV-2013-AndreLSDL #concurrent #named #parametricity #realtime: PSyHCoS: Parameter Synthesis for Hierarchical Concurrent Real-Time Systems (ÉA, YL, JS, JSD, SWL), pp. 984–989.
CAV-2013-BraibantC #hardware #verification: Formal Verification of Hardware Synthesis (TB, AC), pp. 213–228.
CAV-2013-CernyHRRT #concurrent #performance #semantics: Efficient Synthesis for Concurrency by Semantics-Preserving Transformations (PC, TAH, AR, LR, TT), pp. 951–967.
CAV-2013-ChatterjeeGK #automaton #ltl #model checking #probability: Automata with Generalized Rabin Pairs for Probabilistic Model Checking and LTL Synthesis (KC, AG, JK), pp. 559–575.
CAV-2013-KhalimovJB: PARTY Parameterized Synthesis of Token Rings (AK, SJ, RB), pp. 928–933.
LICS-2013-Hales #logic: Arbitrary Action Model Logic and Action Model Synthesis (JH), pp. 253–262.
VMCAI-2013-JacobsKS #reduction: Reductions for Synthesis Procedures (SJ, VK, PS), pp. 88–107.
VMCAI-2013-KhalimovJB #performance #towards: Towards Efficient Parameterized Synthesis (AK, SJ, RB), pp. 108–127.
VMCAI-2013-Yahav: Abstraction-Guided Synthesis (EY), p. 27.
AFL-J-2011-BenattarBLMRS12 #finite #transducer: Channel Synthesis for Finite Transducers (GB, BB, DL, JM, OHR, MS), pp. 1241–1260.
ICFP-2012-MyreenO #higher-order #logic #ml: Proof-producing synthesis of ML from higher-order logic (MOM, SO), pp. 115–126.
CHI-2012-DraxlerSSBR #social #tool support: Supporting the social context of technology appropriation: on a synthesis of sharing tools and tool knowledge (SD, GS, MS, AB, DR), pp. 2835–2844.
CIKM-2012-CheungSM #recommendation #social #using: Using program synthesis for social recommendations (AC, ASL, SM), pp. 1732–1736.
ICPR-2012-ChangDZDW #representation #sketching #using: Smoothness-constrained face photo-sketch synthesis using sparse representation (LC, XD, MZ, FD, ZW), pp. 3025–3029.
ICPR-2012-HouHWH #video: Improvements of dynamic texture synthesis for video coding (ZH, RH, ZW, ZH), pp. 3148–3151.
ICPR-2012-HsinSK #algorithm #performance: A fast wavelet-packet-based algorithm for texture synthesis (HCH, TYS, LTK), pp. 3124–3127.
ICPR-2012-IshikawaTKI #3d: 3-D recovery of a non-rigid object from a single camera view by piecewise recovery and synthesis (SI, JKT, HK, SI), pp. 1443–1446.
ICPR-2012-LuSOS #image: Head pose-free appearance-based gaze sensing via eye image synthesis (FL, YS, TO, YS), pp. 1008–1011.
SEKE-2012-BagheriSS #named #trade-off: Spacemaker: Practical Formal Synthesis of Tradeoff Spaces for Object-Relational Mapping (HB, KJS, SHS), pp. 688–693.
SEKE-2012-LobatoMNAM #risk management: Synthesizing Evidence on Risk Management: A Narrative Synthesis of two Mapping Studies (LLL, IdCM, PAdMSN, ESdA, SRdLM), pp. 641–646.
MoDELS-2012-MaozS #semantics: Assume-Guarantee Scenarios: Semantics and Synthesis (SM, YS), pp. 335–351.
SPLC-2012-AndersenCSW #feature model #modelling #performance: Efficient synthesis of feature models (NA, KC, SS, AW), pp. 106–115.
PEPM-2012-Voigtlander #bidirectional #induction: Ideas for connecting inductive program synthesis and bidirectionalization (JV), pp. 39–42.
PLDI-2012-GodefroidT #automation #encoding: Automated synthesis of symbolic instruction encodings from I/O samples (PG, AT), pp. 441–452.
PLDI-2012-HawkinsAFRS #concurrent #data transformation #representation: Concurrent data representation synthesis (PH, AA, KF, MCR, MS), pp. 417–428.
PLDI-2012-LiuNPVY #memory management #modelling: Dynamic synthesis for relaxed memory models (FL, NN, NP, MTV, EY), pp. 429–440.
PPDP-2012-BacciCFV #automation #first-order #source code #specification: Automatic synthesis of specifications for first order curry programs (GB, MC, MAF, AV), pp. 25–34.
ICSE-2012-DIppolito #challenge #re-engineering: Synthesis of event-based controllers: A software engineering challenge (ND), pp. 1547–1550.
ICSE-2012-GhezziM #behaviour #specification #validation: Behavioral validation of JFSL specifications through model synthesis (CG, AM), pp. 936–946.
SAC-2012-ManciniFP #combinator #constraints #database #problem #relational: Combinatorial problem solving over relational databases: view synthesis through constraint-based local search (TM, PF, JP), pp. 80–87.
GPCE-2012-BagheriS #architecture #framework #named #platform: Pol: specification-driven synthesis of architectural code frameworks for platform-based applications (HB, KJS), pp. 93–102.
CASE-2012-KwonSY #pipes and filters: A linkage type mechanical clutch synthesis for pipeline inspection robot (YSK, JTS, BJY), pp. 618–623.
CASE-2012-MohajeraniMF #composition: Transition removal for compositional supervisor synthesis (SM, RM, MF), pp. 694–699.
DAC-2012-BobbaMLM #physics: Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.
DAC-2012-ChanSSM #hardware #specification: Specification and synthesis of hardware checkpointing and rollback mechanisms (CC, DSN, DS, SM), pp. 1226–1232.
DAC-2012-ChenH #3d: Clock tree synthesis with methodology of re-use in 3D IC (FWC, TH), pp. 1094–1099.
DAC-2012-CongL #architecture #metric #optimisation: A metric for layout-friendly microarchitecture optimization in high-level synthesis (JC, BL), pp. 1239–1244.
DAC-2012-CongZZ #memory management #optimisation: Optimizing memory hierarchy allocation with loop transformations for high-level synthesis (JC, PZ, YZ), pp. 1233–1238.
DAC-2012-HuCG: Library-aware resonant clock synthesis (LARCS) (XH, WJC, MRG), pp. 145–150.
DAC-2012-LearyCC #architecture #memory management: System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC (GL, WC, KSC), pp. 672–677.
DAC-2012-LinK #comprehension #logic #search-based: Application of logic synthesis to the understanding and cure of genetic diseases (PCKL, SPK), pp. 734–740.
DAC-2012-LiuARVG #component #multi #performance: Efficient multi-objective synthesis for microwave components based on computational intelligence techniques (BL, HA, SR, GAEV, GGEG), pp. 542–548.
DAC-2012-MiddendorfBH #hardware #recursion: Hardware synthesis of recursive functions through partial stream rewriting (LM, CB, CH), pp. 1207–1215.
DAC-2012-Seshia #deduction #induction #named #verification: Sciduction: combining induction, deduction, and structure for verification and synthesis (SAS), pp. 356–365.
DAC-2012-VenkataramaniSKRR #approximate #logic #named: SALSA: systematic logic synthesis of approximate circuits (SV, AS, VJK, KR, AR), pp. 796–801.
DATE-2012-ChenSZX #3d #named #physics: 3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs (YC, GS, QZ, YX), pp. 1185–1190.
DATE-2012-KondratyevLMW #trade-off: Exploiting area/delay tradeoffs in high-level synthesis (AK, LL, MM, YW), pp. 1024–1029.
DATE-2012-LiuPC #composition #design: Compositional system-level design exploration with planning of high-level synthesis (HYL, MP, LPC), pp. 641–646.
DATE-2012-LuoCH #approach #fault: A cyberphysical synthesis approach for error recovery in digital microfluidic biochips (YL, KC, TYH), pp. 1239–1244.
DATE-2012-Mancini #kernel #memory management: Enhancing non-linear kernels by an optimized memory hierarchy in a High Level Synthesis flow (SM, FR), pp. 1130–1133.
DATE-2012-MeissnerMLH #framework #graph #morphism #performance #testing: Fast isomorphism testing for a graph-based analog circuit synthesis framework (MM, OM, LL, LH), pp. 757–762.
DATE-2012-WilleDOO #automation #design #power management #using: Automatic design of low-power encoders using reversible circuit synthesis (RW, RD, CO, AGO), pp. 1036–1041.
PPoPP-2012-AliasDP #kernel #optimisation: Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA (CA, AD, AP), pp. 285–286.
TACAS-2012-FinkbeinerP: Template-Based Controller Synthesis for Timed Systems (BF, HJP), pp. 392–406.
TACAS-2012-JacobsB: Parameterized Synthesis (SJ, RB), pp. 362–376.
TACAS-2012-YehWH #design #framework #named #open source #towards #verification: QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification (HHY, CYW, CY(H), pp. 377–391.
CAV-2012-BohyBFJR #ltl: Acacia+, a Tool for LTL Synthesis (AB, VB, EF, NJ, JFR), pp. 652–657.
CAV-2012-BrazdilCKN #game studies #multi #performance: Efficient Controller Synthesis for Consumption Games with Multiple Resource Types (TB, KC, AK, PN), pp. 23–38.
CAV-2012-ChengGRBK #automation #industrial #named: MGSyn: Automatic Synthesis for Industrial Automation (CHC, MG, HR, CB, AK), pp. 658–664.
CAV-2012-Ehlers #ltl: ACTL ∩ LTL Synthesis (RE), pp. 39–54.
CAV-2012-Thomas #challenge: Synthesis and Some of Its Challenges (WT), p. 1.
ICLP-2012-BacciCFV #automation #functional #logic #specification: The additional difficulties for the automatic synthesis of specifications posed by logic features in functional-logic languages (GB, MC, MAF, AV), pp. 144–153.
IJCAR-2012-SpielmannK #bound: Synthesis for Unbounded Bit-Vector Arithmetic (AS, VK), pp. 499–513.
VMCAI-2012-FinkbeinerJ #lazy evaluation: Lazy Synthesis (BF, SJ), pp. 219–234.
VMCAI-2012-KleinPP #effectiveness #specification: Effective Synthesis of Asynchronous Systems from GR(1) Specifications (UK, NP, AP), pp. 283–298.
CBSE-2011-BordeC #component #embedded #realtime #towards: Towards verified synthesis of ProCom, a component model for real-time embedded systems (EB, JC), pp. 129–138.
AFL-2011-BenattarBLMRS #finite #transducer: Channel Synthesis for Finite Transducers (GB, BB, DL, JM, OHR, MS), pp. 79–92.
CIAA-2011-ChengJBK #on the: On the Hardness of Priority Synthesis (CHC, BJ, CB, AK), pp. 110–117.
SFM-2011-GiannakopoulouP: Context Synthesis (DG, CSP), pp. 191–216.
SFM-2011-InverardiST: Application-Layer Connector Synthesis (PI, RS, MT), pp. 148–190.
SFM-2011-IssarnyBB #middleware #state of the art: Middleware-Layer Connector Synthesis: Beyond State of the Art in Middleware Interoperability (VI, AB, YDB), pp. 217–255.
ICFP-2011-GhicaSS #compilation #geometry #hardware #recursion: Geometry of synthesis iv: compiling affine recursion into static hardware (DRG, AIS, SS), pp. 221–233.
HCI-DDA-2011-ChangZDWH #multi #sketching: Face Sketch Synthesis via Multivariate Output Regression (LC, MZ, XD, ZW, YH), pp. 555–561.
CAiSE-2011-AwadGTW #approach #process: An Iterative Approach for Business Process Template Synthesis from Compliance Rules (AA, RG, JT, MW), pp. 406–421.
OOPSLA-2011-PuBS #algorithm #first-order #programming: Synthesis of first-order dynamic programming algorithms (YP, RB, SS), pp. 83–98.
OOPSLA-2011-YessenovXS #data-driven #framework #object-oriented: Data-driven synthesis for object-oriented frameworks (KY, ZX, ASL), pp. 65–82.
PLDI-2011-GulwaniJTV #source code: Synthesis of loop-free programs (SG, SJ, AT, RV), pp. 62–73.
PLDI-2011-HawkinsAFRS #data transformation #representation: Data representation synthesis (PH, AA, KF, MCR, MS), pp. 38–49.
PLDI-2011-SrivastavaGCF #induction: Path-based inductive synthesis for program inversion (SS, SG, SC, JSF), pp. 492–503.
POPL-2011-GhicaS #geometry #resource management #type inference: Geometry of synthesis III: resource management through type inference (DRG, AS), pp. 345–356.
PPDP-2011-Rybalchenko #automation #tool support #towards #verification: Towards automatic synthesis of software verification tools (AR), pp. 3–4.
ICSE-2011-Bagheri #approach #architecture #formal method #platform: A formal approach to software synthesis for architectural platforms (HB), pp. 1143–1145.
ICSE-2011-DIppolitoBPU #behaviour #modelling: Synthesis of live behaviour models for fallible domains (ND, VAB, NP, SU), pp. 211–220.
ICSE-2011-YuAB: Patching vulnerabilities with sanitization synthesis (FY, MA, TB), pp. 251–260.
CASE-2011-MohajeraniMF #composition #nondeterminism: Nondeterminism avoidance in compositional synthesis of discrete event systems (SM, RM, MF), pp. 19–24.
DAC-2011-DensmoreHKSAWV #biology #design: Joint DAC/IWBDA special session design and synthesis of biological circuits (DD, MH, SK, XS, AA, EW, CV), pp. 114–115.
DAC-2011-HuG #distributed #grid: Distributed Resonant clOCK grid Synthesis (ROCKS) (XH, MRG), pp. 516–521.
DAC-2011-PatilBC #architecture #contract: Enforcing architectural contracts in high-level synthesis (NAP, AB, DC), pp. 824–829.
DAC-2011-PuggelliWKS #logic #question #robust #tool support: Are logic synthesis tools robust? (AP, TW, AK, ALSV), pp. 633–638.
DAC-2011-RahmanATS #library #physics #reduction: Power reduction via separate synthesis and physical libraries (MR, RA, HT, CS), pp. 627–632.
DAC-2011-ReimannLGHT #constraints #realtime #string: Symbolic system synthesis in the presence of stringent real-time constraints (FR, ML, MG, CH, JT), pp. 393–398.
DAC-2011-RyzhenkoB #geometry #layout #physics: Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries (NR, SB), pp. 83–88.
DAC-2011-TangWHH #incremental #logic #multi: Interpolation-based incremental ECO synthesis for multi-error logic rectification (KFT, CAW, PKH, CY(H), pp. 146–151.
DAC-2011-ThieleSYB #analysis #embedded #multi: Thermal-aware system analysis and software synthesis for embedded multi-processors (LT, LS, HY, IB), pp. 268–273.
DATE-2011-ChiuSH #constraints #pipes and filters #precedence #realtime #streaming: Pipeline schedule synthesis for real-time streaming tasks with inter/intra-instance precedence constraints (YSC, CSS, SHH), pp. 1321–1326.
DATE-2011-FalkZHT #algorithm #clustering #data flow #embedded #performance #rule-based: A rule-based static dataflow clustering algorithm for efficient embedded software synthesis (JF, CZ, CH, JT), pp. 521–526.
DATE-2011-KeezerG: Two methods for 24 Gbps test signal synthesis (DCK, CEG), pp. 579–582.
DATE-2011-KondratyevLMW #pipes and filters: Realistic performance-constrained pipelining in high-level synthesis (AK, LL, MM, YW), pp. 1382–1387.
DATE-2011-Micheli #design #logic #physics #question: Logic synthesis and physical design: Quo vadis? (GDM), p. 50.
DATE-2011-MiteaMHJ #automation #constraints: Automated constraint-driven topology synthesis for analog circuits (OM, MM, LH, PJ), pp. 1662–1665.
DATE-2011-SinhaP #representation #state machine: Abstract state machines as an intermediate representation for high-level synthesis (RS, HDP), pp. 1406–1411.
DATE-2011-VissersNN #interface #realtime #tool support #using: Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools (KAV, SN, JN), pp. 848–850.
DATE-2011-WelpK #approach #markov #process: An approach for dynamic selection of synthesis transformations based on Markov Decision Processes (TW, AK), pp. 1533–1536.
DATE-2011-ZukoskiCM #logic: Reliability-driven don’t care assignment for logic synthesis (AZ, MRC, KM), pp. 1560–1565.
ESOP-2011-BrauerK #quantifier: Transfer Function Synthesis without Quantifier Elimination (JB, AK), pp. 97–115.
FoSSaCS-2011-VelnerR #problem: Church Synthesis Problem for Noisy Input (YV, AR), pp. 275–289.
TACAS-2011-ChatterjeeHJS #named: QUASY: Quantitative Synthesis Tool (KC, TAH, BJ, RS), pp. 267–271.
TACAS-2011-Ehlers #bound #named: Unbeast: Symbolic Bounded Synthesis (RE), pp. 272–275.
CAV-2011-CernyCHRS #concurrent #source code: Quantitative Synthesis for Concurrent Programs (PC, KC, TAH, AR, RS), pp. 243–259.
CAV-2011-GveroKP #interactive: Interactive Synthesis of Code Snippets (TG, VK, RP), pp. 418–423.
CAV-2011-KatzPS #distributed: Synthesis of Distributed Control through Knowledge Accumulation (GK, DP, SS), pp. 510–525.
CAV-2011-PeterEM #automaton #named #verification: Synthia: Verification and Synthesis for Timed Automata (HJP, RE, RM), pp. 649–655.
CSL-2011-JenkinsORW #metric #problem: The Church Synthesis Problem with Metric (MJ, JO, AR, JW), pp. 307–321.
CSL-2011-LustigNV #component #probability: Synthesis from Probabilistic Components (YL, SN, MYV), pp. 412–427.
ICLP-2011-Herranz-NievaM #logic programming #object-oriented #source code #specification: Synthesis of Logic Programs from Object-Oriented Formal Specifications (ÁHN, JM), pp. 95–105.
VMCAI-2011-ChengRKB #embedded #fault tolerance #game studies #theory and practice #using: Synthesis of Fault-Tolerant Embedded Systems Using Games: From Theory to Practice (CHC, HR, AK, CB), pp. 118–133.
ITiCSE-2010-ShoufanLR #framework #platform #visualisation: A platform for visualizing digital circuit synthesis with VHDL (AS, ZL, GR), pp. 294–298.
ICPR-2010-ChangZHD #representation #sketching: Face Sketch Synthesis via Sparse Representation (LC, MZ, YH, XD), pp. 2146–2149.
ICPR-2010-DOrazioLM #generative #multi #video: Panoramic Video Generation by Multi View Data Synthesis (TD, ML, NM), pp. 4105–4108.
KEOD-2010-KorukhovaF #approach #reasoning: A Case-based Reasoning Approach to Program Synthesis (YK, NF), pp. 335–338.
SEKE-2010-ZhangHZJM #automation #eclipse #execution #towards: Towards Automated Synthesis of Executable Eclipse Tutorials (NZ, GH, YZ, NJ, HM), pp. 591–598.
ICMT-2010-CabotCGL #graph transformation #ocl: Synthesis of OCL Pre-conditions for Graph Transformation Rules (JC, RC, EG, JdL), pp. 45–60.
OOPSLA-2010-ItzhakyGIS #induction: A simple inductive synthesis methodology and its applications (SI, SG, NI, MS), pp. 36–46.
LOPSTR-2010-SchumannCL #analysis: Analysis of Air Traffic Track Data with the AutoBayes Synthesis System (JS, KC, AL), pp. 21–36.
PLDI-2010-KuncakMPS #functional: Complete functional synthesis (VK, MM, RP, PS), pp. 316–329.
POPL-2010-SrivastavaGF #verification: From program verification to program synthesis (SS, SG, JSF), pp. 313–326.
POPL-2010-VechevYY: Abstraction-guided synthesis of synchronization (MTV, EY, GY), pp. 327–338.
PPDP-2010-Gulwani: Dimensions in program synthesis (SG), pp. 13–24.
FSE-2010-DIppolitoBPU #behaviour #modelling: Synthesis of live behaviour models (ND, VAB, NP, SU), pp. 77–86.
FSE-2010-Shokry #behaviour #towards #using: Towards behavior elaboration and synthesis using modes (HS), pp. 349–352.
ICSE-2010-JhaGST #component: Oracle-guided component-based program synthesis (SJ, SG, SAS, AT), pp. 215–224.
DAC-2010-ChenDC: Clock tree synthesis under aggressive buffer insertion (YYC, CD, DC), pp. 86–89.
DAC-2010-GajskiAS #question #what: What input-language is the best choice for high level synthesis (HLS)? (DG, TMA, SS), pp. 857–858.
DAC-2010-GolubitskyFM: Synthesis of the optimal 4-bit reversible circuits (OG, SMF, DM), pp. 653–656.
DAC-2010-KimK #3d #design #testing: Clock tree synthesis with pre-bond testability for 3D stacked IC designs (TYK, TK), pp. 723–728.
DAC-2010-NurvitadhiHLK #automation #parallel #pipes and filters #specification #thread #transaction: Automatic multithreaded pipeline synthesis from transactional datapath specifications (EN, JCH, SLL, TK), pp. 314–319.
DAC-2010-Potkonjak #tool support #using: Synthesis of trustable ICs using untrusted CAD tools (MP), pp. 633–634.
DAC-2010-SeomunSS #implementation #power management: Synthesis and implementation of active mode power gating circuits (JS, IS, YS), pp. 487–492.
DAC-2010-ShihC #independence #performance: Fast timing-model independent buffered clock-tree synthesis (XWS, YWC), pp. 80–85.
DATE-2010-BarrioMMHM #functional #using: Using Speculative Functional Units in high level synthesis (AADB, MCM, JMM, RH, SOM), pp. 1779–1784.
DATE-2010-CongHJ #algorithm #behaviour #pattern matching #pattern recognition #recognition: A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis (JC, HH, WJ), pp. 1255–1260.
DATE-2010-CongLX #behaviour #coordination #optimisation: Coordinated resource optimization in behavioral synthesis (JC, BL, JX), pp. 1267–1272.
DATE-2010-EconomakosXKS #component #configuration management: Construction of dual mode components for reconfiguration aware high-level synthesis (GE, SX, IK, DS), pp. 1357–1360.
DATE-2010-HaoXRY #behaviour #equivalence #optimisation: Optimizing equivalence checking for behavioral synthesis (KH, FX, SR, JY), pp. 1500–1505.
DATE-2010-JunYC #library #multi #network: Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network (MJ, SY, EYC), pp. 1390–1395.
DATE-2010-LarsenLNP #analysis #realtime #using: Scenario-based analysis and synthesis of real-time systems using uppaal (KGL, SL, BN, SP), pp. 447–452.
DATE-2010-LiZHH #logic #optimisation: Reversible logic synthesis through ant colony optimization (ML, YZ, MSH, CH), pp. 307–310.
DATE-2010-MartinelloMRR #approach #logic #multi #named: KL-Cuts: A new approach for logic synthesis targeting multiple output blocks (OM, FSM, RPR, AIR), pp. 777–782.
DATE-2010-MischkallaH0 #modelling #simulation #uml: Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems (FM, DH, WM), pp. 1201–1206.
DATE-2010-MishraJ #optimisation #power management #using: Low-power FinFET circuit synthesis using surface orientation optimization (PM, NKJ), pp. 311–314.
DATE-2010-ShinG #approximate #fault #logic: Approximate logic synthesis for error tolerant applications (DS, SKG), pp. 957–960.
LCTES-2010-DelavalMR #composition #contract: Contracts for modular discrete controller synthesis (GD, HM, ÉR), pp. 57–66.
TACAS-2010-AvnitSP #automation #named #protocol: ACS: Automatic Converter Synthesis for SoC Bus Protocols (KA, AS, JP), pp. 343–348.
TACAS-2010-CookKRW #ranking: Ranking Function Synthesis for Bit-Vector Relations (BC, DK, PR, CMW), pp. 236–250.
TACAS-2010-FismanKL: Rational Synthesis (DF, OK, YL), pp. 190–204.
CAV-2010-BloemCGHKRSS #analysis #named #requirements: RATSY — A New Requirements Analysis Tool with Synthesis (RB, AC, KG, GH, RK, MR, VS, RS), pp. 425–429.
CAV-2010-BouajjaniDERS #bound #invariant #source code: Invariant Synthesis for Programs Manipulating Lists with Unbounded Data (AB, CD, CE, AR, MS), pp. 72–88.
CAV-2010-Donze #hybrid #parametricity #verification: Breach, A Toolbox for Verification and Parameter Synthesis of Hybrid Systems (AD), pp. 167–170.
CAV-2010-Ehlers #bound: Symbolic Bounded Synthesis (RE), pp. 365–379.
CAV-2010-KuncakMPS #functional #named: Comfusy: A Tool for Complete Functional Synthesis (VK, MM, RP, PS), pp. 430–433.
CAV-2010-MariMST #feedback #hybrid #linear: Synthesis of Quantized Feedback Control Software for Discrete Time Linear Hybrid Systems (FM, IM, IS, ET), pp. 180–195.
CAV-2010-MazoDT #embedded #named: PESSOA: A Tool for Embedded Controller Synthesis (MMJ, AD, PT), pp. 566–569.
IJCAR-2010-Aderhold #automation #axiom #higher-order #induction #recursion #source code: Automated Synthesis of Induction Axioms for Programs with Second-Order Recursion (MA), pp. 263–277.
WICSA-ECSA-2009-KeulerW #architecture #design: Interaction-sensitive synthesis of architectural tactics in connector designs (TK, CW), pp. 321–324.
JCDL-2009-YuWZ #library: Style-consistency calligraphy synthesis system in digital library (KY, JW, YZ), pp. 145–152.
IFM-2009-Cook #bound #hardware: Taming the Unbounded for Hardware Synthesis (BC), p. 39.
SFM-2009-MarconiP #composition #web #web service: Synthesis and Composition of Web Services (AM, MP), pp. 89–157.
TLCA-2009-FioreH #deduction #equation: Mathematical Synthesis of Equational Deduction Systems (MPF, CKH), pp. 1–2.
DHM-2009-KawaguchiEK #assessment #design: Database-Driven Grasp Synthesis and Ergonomic Assessment for Handheld Product Design (KK, YE, SK), pp. 642–652.
HCI-NT-2009-LeeP #evaluation #speech: Interpretation of User Evaluation for Emotional Speech Synthesis System (HJL, JCP), pp. 295–303.
SAS-2009-Bodik #algorithm #source code: Algorithmic Program Synthesis with Partial Programs and Decision Procedures (RB), p. 1.
ESEC-FSE-2009-BertolinoIPT #automation #behaviour #composition #protocol: Automatic synthesis of behavior protocols for composable web-services (AB, PI, PP, MT), pp. 141–150.
ICSE-2009-DamasLRL #behaviour #modelling #process: Analyzing critical process models through behavior model synthesis (CD, BL, FR, AvL), pp. 441–451.
ICSE-2009-HenklerGHSAEHLSG #behaviour #realtime: Synthesis of timed behavior from scenarios in the Fujaba Real-Time Tool Suite (SH, JG, MH, WS, KA, TE, CH, RL, AS, HG), pp. 615–618.
GPCE-2009-NedunuriC #performance #problem #source code: Synthesis of fast programs for maximum segment sum problems (SN, WRC), pp. 117–126.
SLE-2009-KalninaKCS #visual notation: Graphical Template Language for Transformation Synthesis (EK, AK, EC, AS), pp. 244–253.
CASE-2009-JohnsonM #animation #automation #optimisation #using: Automated trajectory synthesis from animation data using trajectory optimization (ERJ, TDM), pp. 274–279.
CASE-2009-PintoKX #embedded #network: Synthesis of wireless time-triggered embedded networks for networked control systems (AP, RK, SX), pp. 397–402.
DAC-2009-BawiecN #logic: Boolean logic function synthesis for generalised threshold gate circuits (MAB, MN), pp. 83–86.
DAC-2009-ChouCK: Handling don’t-care conditions in high-level synthesis and application for reducing initialized registers (HZC, KHC, SYK), pp. 412–415.
DAC-2009-SamiiEPC #embedded #multi #quality: Quality-driven synthesis of embedded multi-mode control systems (SS, PE, ZP, AC), pp. 864–869.
DAC-2009-SeiculescuMBM: NoC topology synthesis for supporting shutdown of voltage islands in SoCs (CS, SM, LB, GDM), pp. 822–825.
DAC-2009-ShinPS #using: Register allocation for high-level synthesis using dual supply voltages (IS, SP, YS), pp. 937–942.
DAC-2009-WangCSC #graph #power management #using: Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (RW, NCC, BS, CKC), pp. 166–171.
DAC-2009-WilleD #logic #scalability: BDD-based synthesis of reversible logic for large functions (RW, RD), pp. 270–275.
DATE-2009-BobbaZPAM #design #logic #standard: Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis (SB, JZ, AP, DA, GDM), pp. 616–621.
DATE-2009-GopalakrishnanK #algebra #polynomial: Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis (SG, PK), pp. 1452–1457.
DATE-2009-GrabBCCFLS #layout: Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.
DATE-2009-HaastregtK #automation #c #hardware #network #process #streaming: Automated synthesis of streaming C applications to process networks in hardware (SvH, BK), pp. 890–893.
DATE-2009-JamaaMM #library #logic #multi #novel: Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis (MHBJ, KM, GDM), pp. 622–627.
DATE-2009-KeinertDHHT #algorithm #image #modelling #multi #optimisation: Model-based synthesis and optimization of static multi-rate image processing algorithms (JK, HD, FH, CH, JT), pp. 135–140.
DATE-2009-KravetsM #logic #using: Sequential logic synthesis using symbolic bi-decomposition (VNK, AM), pp. 1458–1463.
DATE-2009-LoiAB #configuration management #interface #network: Synthesis of low-overhead configurable source routing tables for network interfaces (IL, FA, LB), pp. 262–267.
DATE-2009-LukasiewyczSGHT #architecture #communication: Combined system synthesis and communication architecture exploration for MPSoCs (ML, MS, MG, CH, JT), pp. 472–477.
DATE-2009-PaikSS #named #performance: HLS-l: High-level synthesis of high performance latch-based circuits (SP, IS, YS), pp. 1112–1117.
DATE-2009-Perry #design #modelling #quality: Model Based Design needs high level synthesis — A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design (SP), pp. 1202–1207.
DATE-2009-SamiiCEP #distributed #embedded #scheduling: Integrated scheduling and synthesis of control applications on distributed embedded systems (SS, AC, PE, ZP), pp. 57–62.
DATE-2009-SchallenbergNHHO #configuration management #framework #modelling: OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems (AS, WN, AH, PAH, FO), pp. 970–975.
DATE-2009-SeiculescuMBM #3d #network: SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips (CS, SM, LB, GDM), pp. 9–14.
SOSP-2009-RyzhykCKSH #automation: Automatic device driver synthesis with termite (LR, PC, IK, ELS, GH), pp. 73–86.
FASE-2009-KuglerPP #requirements: Controller Synthesis from LSC Requirements (HK, CP, AP), pp. 79–93.
FoSSaCS-2009-LustigV #component #library: Synthesis from Component Libraries (YL, MYV), pp. 395–409.
FoSSaCS-2009-Thomas #problem: Facets of Synthesis: Revisiting Church’s Problem (WT), pp. 1–14.
TACAS-2009-KuglerS #composition #sequence chart #specification: Compositional Synthesis of Reactive Systems from Live Sequence Chart Specifications (HK, IS), pp. 77–91.
CAV-2009-BloemCHJ #quality: Better Quality in Synthesis through Quantitative Objectives (RB, KC, TAH, BJ), pp. 140–156.
LICS-2009-Ghica #game studies #hardware #program analysis #semantics: Applications of Game Semantics: From Program Analysis to Hardware Synthesis (DRG), pp. 17–26.
CBSE-2008-ArbabM #interactive #specification: Synthesis of Connectors from Scenario-Based Interaction Specifications (FA, SM), pp. 114–129.
WICSA-2008-CuiSM #architecture #automation #design #towards: Towards Automated Solution Synthesis and Rationale Capture in Decision-Centric Architecture Design (XC, YS, HM), pp. 221–230.
DRR-2008-HottaF #recognition: Line-touching character recognition based on dynamic reference feature synthesis (YH, KF), p. 68150.
ICALP-B-2008-BrazdilFK #branch #markov #process #verification: Controller Synthesis and Verification for Markov Decision Processes with Qualitative Branching Time Objectives (TB, VF, AK), pp. 148–159.
EDOC-2008-KavimandanKG #automation #enterprise #model transformation #using #workflow: Automated Context-Sensitive Dialog Synthesis for Enterprise Workflows Using Templatized Model Transformations (AK, RK, ASG), pp. 159–168.
ICPR-2008-SugimotoO #array #image #using: Virtual focusing image synthesis for user-specified image region using camera array (SS, MO), pp. 1–4.
PEPM-2008-Bodik #sketching: Software synthesis with sketching (RB), pp. 1–2.
FSE-2008-NejatiSCUZ #composition #evolution #towards: Towards compositional synthesis of evolving systems (SN, MS, MC, SU, PZ), pp. 285–296.
SAC-2008-TarauL: Revisiting exact combinational circuit synthesis (PT, BL), pp. 1758–1759.
DAC-2008-CzajkowskiB #composition #linear #logic: Functionally linear decomposition and synthesis of logic circuits for FPGAs (TSC, SDB), pp. 18–23.
DAC-2008-DasV #adaptation: Topology synthesis of analog circuits based on adaptively generated building blocks (AD, RV), pp. 44–49.
DAC-2008-FraerKM #paradigm: A new paradigm for synthesis and propagation of clock gating conditions (RF, GK, MKM), pp. 658–663.
DAC-2008-Hurst #automation #logic: Automatic synthesis of clock gating logic with controlled netlist perturbation (APH), pp. 654–657.
DAC-2008-PuriJBGLM: Custom is from Venus and synthesis from Mars (RP, WHJ, SB, TG, JL, RKM), p. 992.
DAC-2008-QianR #logic #polynomial #probability #robust: The synthesis of robust polynomial arithmetic with stochastic logic (WQ, MDR), pp. 648–653.
DAC-2008-RajaramP #design #robust: Robust chip-level clock tree synthesis for SOC designs (AR, DZP), pp. 720–723.
DATE-2008-CruzBCM #embedded #modelling #named #realtime: ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis (FC, RSB, LCC, PRMM), pp. 1510–1515.
DATE-2008-DongZ #integration #logic #standard: Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration (MD, LZ), pp. 268–271.
DATE-2008-DubrovaTT #analysis #feedback #on the: On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers (ED, MT, HT), pp. 1286–1291.
DATE-2008-ElesIPP #embedded #fault tolerance: Synthesis of Fault-Tolerant Embedded Systems (PE, VI, PP, ZP), pp. 1117–1122.
DATE-2008-GruttnerONCF #modelling #refinement: SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder (KG, FO, WN, FCB, AMF), pp. 128–133.
DATE-2008-HashemiG #algorithm #approximate #pipes and filters: Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis (MH, SG), pp. 746–751.
DATE-2008-MokhovY #configuration management #graph #partial order: Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis (AM, AY), pp. 1142–1147.
DATE-2008-Parandeh-AfsharBI #integer #linear #programming: Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming (HPA, PB, PI), pp. 1256–1261.
DATE-2008-PradhanV #performance #using: Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches (AP, RV), pp. 523–526.
DATE-2008-WangH #multi: Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology (XW, LH), pp. 800–803.
DATE-2008-WangSX #framework: A Variation Aware High Level Synthesis Framework (FW, GS, YX), pp. 1063–1068.
DATE-2008-WilleLDG #logic #quantifier: Quantified Synthesis of Reversible Logic (RW, HML, GWD, DG), pp. 1015–1020.
FoSSaCS-2008-BonsangueRS #algebra #automaton #logic: Coalgebraic Logic and Synthesis of Mealy Machines (MMB, JJMMR, AS), pp. 231–245.
TACAS-2008-FinkbeinerPS #composition #model checking #named: RESY: Requirement Synthesis for Compositional Model Checking (BF, HJP, SS), pp. 463–466.
CAV-2008-KunduLG #validation: Validating High-Level Synthesis (SK, SL, RG), pp. 459–472.
HT-2007-KehoeP #speech #topic: Transforming DITA topics for speech synthesis output (AK, IJP), pp. 147–148.
ICDAR-2007-JinZ #using: Synthesis of Chinese Character Using Affine Transformation (LJ, XZ), pp. 218–222.
ICDAR-2007-RabasseGF: A Method for the Synthesis of Dynamic Biometric Signature Data (CR, RMG, MCF), pp. 168–172.
ICDAR-2007-SilvaL #documentation: Color Document Synthesis as a Compression Strategy (JMS, RL), pp. 466–470.
CIG-2007-YauTA #co-evolution #evolution: Pareto Evolution and Co-Evolution in Cognitive Neural Agents Synthesis for Tic-Tac-Toe (YJY, JT, PA), pp. 304–311.
AGTIVE-2007-BauerDTW #analysis #constraints #ocl #verification: Verification and Synthesis of OCL Constraints Via Topology Analysis (JB, WD, TT, BW), pp. 361–376.
DHM-2007-LiLY #assessment #design: Design and Realization of Synthesis Assessment System for Cockpit Ergonomics (YL, KL, XY), pp. 915–922.
HCI-MIE-2007-LeeP07a #behaviour #generative #speech: Customized Message Generation and Speech Synthesis in Response to Characteristic Behavioral Patterns of Children (HJL, JCP), pp. 114–123.
LOPSTR-2007-Poernomo #communication #process: Synthesis of Data Views for Communicating Processes (IP), pp. 185–200.
PLDI-2007-GuoVA #analysis #induction #recursion: Shape analysis with inductive recursion synthesis (BG, NV, DIA), pp. 256–265.
POPL-2007-Batory #implementation: From implementation to theory in product synthesis (DSB), pp. 135–136.
POPL-2007-Ghica #approach #design #geometry: Geometry of synthesis: a structured approach to VLSI design (DRG), pp. 363–375.
ASE-2007-VainRKE #nondeterminism: Synthesis of test purpose directed reactive planning tester for nondeterministic systems (JV, KR, AK, JPE), pp. 363–372.
ICSE-2007-AutiliINT #automation #component #distributed #named: SYNTHESIS: A Tool for Automatically Assembling Correct and Distributed Component-Based Systems (MA, PI, AN, MT), pp. 784–787.
ICSE-2007-UchitelBC #behaviour: Behaviour Model Synthesis from Properties and Scenarios (SU, GB, MC), pp. 34–43.
CC-2007-Batory #development #modelling #refactoring: Program Refactoring, Program Synthesis, and Model-Driven Development (DSB), pp. 156–171.
DAC-2007-ChengCW07a #named: DDBDD: Delay-Driven BDD Synthesis for FPGAs (LC, DC, MDFW), pp. 910–915.
DAC-2007-KumarKS: NBTI-Aware Synthesis of Digital Circuits (SVK, CHK, SSS), pp. 370–375.
DAC-2007-LeungT #energy: Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands (LFL, CYT), pp. 128–131.
DAC-2007-LimKK #architecture #communication #distributed: Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture (KHL, YK, TK), pp. 765–770.
DAC-2007-MangHH #distributed #effectiveness #physics: Techniques for Effective Distributed Physical Synthesis (FYCM, WH, PHH), pp. 859–864.
DAC-2007-XuC: Integrated Droplet Routing in the Synthesis of Microfluidic Biochips (TX, KC), pp. 948–953.
DATE-2007-BloemGJPPW #automation #case study #hardware #interactive #specification: Interactive presentation: Automatic hardware synthesis from specifications: a case study (RB, SJG, BJ, NP, AP, MW), pp. 1188–1193.
DATE-2007-ButtSRPS #optimisation: System level clock tree synthesis for power optimization (SAB, SS, JR, AP, ES), pp. 1677–1682.
DATE-2007-EeckelaertSGSS #performance: An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection (TE, RS, GGEG, MS, WMCS), pp. 81–86.
DATE-2007-GhoshBR #adaptation #scheduling #using: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling (SG, SB, KR), pp. 1532–1537.
DATE-2007-GlassLSHT #interactive: Interactive presentation: Reliability-aware system synthesis (MG, ML, TS, CH, JT), pp. 409–414.
DATE-2007-KurraSP: The impact of loop unrolling on controller delay in high level synthesis (SK, NKS, PRP), pp. 391–396.
DATE-2007-MavroidisP #hardware #performance: Efficient testbench code synthesis for a hardware emulator system (IM, IP), pp. 888–893.
DATE-2007-MolinaRMH #multi #optimisation: Area optimization of multi-cycle operators in high-level synthesis (MCM, RRS, JMM, RH), pp. 449–454.
DATE-2007-VermaI #automation #scalability: Automatic synthesis of compressor trees: reevaluating large counters (AKV, PI), pp. 443–448.
DATE-2007-WangY #fault #testing: High-level test synthesis for delay fault testability (SJW, THY), pp. 45–50.
DATE-2007-ZhengNPGV #distributed #modelling #realtime: Synthesis of task and message activation models in real-time distributed automotive systems (WZ, MDN, CP, PG, ALSV), pp. 93–98.
LCTES-2007-ChoAG #interface #manycore #modelling #transaction: Interface synthesis for heterogeneous multi-core systems from transaction level models (HC, SA, DG), pp. 140–142.
FASE-2007-HennickerK #state machine: Activity-Driven Synthesis of State Machines (RH, AK), pp. 87–101.
FoSSaCS-2007-Chatterjee #game studies #probability: Optimal Strategy Synthesis in Stochastic Müller Games (KC), pp. 138–152.
TACAS-2007-BolligKKL #design #game studies #learning #modelling: Replaying Play In and Play Out: Synthesis of Design Models from Scenarios by Learning (BB, JPK, CK, ML), pp. 435–450.
TACAS-2007-ChatterjeeH: Assume-Guarantee Synthesis (KC, TAH), pp. 261–275.
TACAS-2007-TivoliFGG #adaptation #component #realtime: Adaptor Synthesis for Real-Time Components (MT, PF, AG, GG), pp. 185–200.
CAV-2007-BeyerHS #algorithm #interface: Algorithms for Interface Synthesis (DB, TAH, VS), pp. 4–19.
CAV-2007-JobstmannGWB #named: Anzu: A Tool for Property Synthesis (BJ, SJG, MW, RB), pp. 258–262.
ICLP-2007-TarauL #framework #logic programming: A Logic Programming Framework for Combinational Circuit Synthesis (PT, BL), pp. 180–194.
SAT-2007-EenMS #logic #satisfiability: Applying Logic Synthesis for Speeding Up SAT (NE, AM, NS), pp. 272–286.
VMCAI-2007-BeyerHMR #invariant: Invariant Synthesis for Combined Theories (DB, TAH, RM, AR), pp. 378–394.
CIAA-2006-YangXSP #hybrid #quantum: Universality of Hybrid Quantum Gates and Synthesis Without Ancilla Qudits (GY, FX, XS, MAP), pp. 279–280.
IFL-2006-RuffJ #array: Functional-Based Synthesis of a Systolic Array for GCD Computation (LR, TJ), pp. 37–54.
ICEIS-HCI-2006-LiSB #correlation #hybrid #recognition #sketching #using: Face Recognition from Sketches Using Advanced Correlation Filters Using Hybrid Eigenanalysis for Face Synthesis (YhL, MS, VB), pp. 11–18.
ICEIS-J-2006-HaddadMR06a #semantics: A Formal Semantics and a Client Synthesis for a BPEL Service (SH, PM, SR), pp. 388–401.
ICEIS-SAIC-2006-HaddadMR #semantics #web #web service: Client Synthesis for Web Services by Way of a Timed Semantics (SH, PM, SR), pp. 19–26.
ICPR-v1-2006-LeeE #analysis #modelling: Nonlinear Shape and Appearance Models for Facial Expression Analysis and Synthesis (CSL, AME), pp. 497–502.
ICPR-v2-2006-JiangL #3d #image: Synthesis of Stereoscopic 3D Videos by Limited Resources of Range Images (XJ, ML), pp. 1220–1224.
ICPR-v3-2006-ZhangGL #automation #recognition: Automatic Texture Synthesis for Face Recognition from Single Views (XZ, YG, MKHL), pp. 1151–1154.
ICPR-v4-2006-FilipHC #performance: Fast Synthesis of Dynamic Colour Textures (JF, MH, DC), pp. 25–28.
MoDELS-2006-MullerFFHSGJ #analysis #modelling #syntax: Model-Driven Analysis and Synthesis of Concrete Syntax (PAM, FF, FF, MH, RS, SG, JMJ), pp. 98–110.
MoDELS-2006-SchattkowskyHE #design #process #uml #using: Using UML Activities for System-on-Chip Design and Synthesis (TS, JHH, GE), pp. 737–752.
MoDELS-2006-MullerFFHSGJ #analysis #modelling #syntax: Model-Driven Analysis and Synthesis of Concrete Syntax (PAM, FF, FF, MH, RS, SG, JMJ), pp. 98–110.
MoDELS-2006-SchattkowskyHE #design #process #uml #using: Using UML Activities for System-on-Chip Design and Synthesis (TS, JHH, GE), pp. 737–752.
LOPSTR-2006-ScheweF: Synthesis of Asynchronous Systems (SS, BF), pp. 127–142.
LOPSTR-2006-WinwoodKC #automation #monitoring #on the: On the Automated Synthesis of Proof-Carrying Temporal Reference Monitors (SW, GK, MMTC), pp. 111–126.
RE-2006-AxenathGKF #evaluation: Systematic Requirements-Driven Evaluation and Synthesis of Alternative Principle Solutions for Advanced Mechatronic Systems (BA, HG, FK, UF), pp. 156–165.
ASE-2006-FalbRA #automation #design #interactive #specification #user interface #using: Using communicative acts in interaction design specifications for automated synthesis of user interfaces (JF, TR, EA), pp. 261–264.
FSE-2006-DamasLL #state machine: Scenarios, goals, and state machines: a win-win partnership for model synthesis (CD, BL, AvL), pp. 197–207.
SAC-2006-DelavalR #domain-specific language #generative: A domain-specific language for task handlers generation, applying discrete controller synthesis (GD, ÉR), pp. 901–905.
DAC-2006-AksoyCFM #constraints #integer #linear #optimisation #programming #satisfiability #using: Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming (LA, EACdC, PFF, JM), pp. 669–674.
DAC-2006-CortadellaKG #architecture: Synthesis of synchronous elastic architectures (JC, MK, BG), pp. 657–662.
DAC-2006-HuZCGC #communication #latency #power management: Communication latency aware low power NoC synthesis (YH, YZ, HC, RLG, CKC), pp. 574–579.
DAC-2006-MishchenkoCB #fresh look #logic: DAG-aware AIG rewriting a fresh look at combinational logic synthesis (AM, SC, RKB), pp. 532–535.
DAC-2006-NieuwoudtRM #named #optimisation: SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers (AN, TR, YM), pp. 879–884.
DAC-2006-PandeyG #communication #constraints #scalability #statistics: Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint (SP, MG), pp. 663–668.
DAC-2006-SovianiHE #pipes and filters: Synthesis of high-performance packet processing pipelines (CS, IH, SAE), pp. 679–682.
DATE-2006-AbdollahiP #analysis #diagrams #quantum #using: Analysis and synthesis of quantum circuits by using quantum decision diagrams (AA, MP), pp. 317–322.
DATE-2006-BanerjeeRMB #fine-grained #logic #power management #using: Low power synthesis of dynamic logic circuits using fine-grained clock gating (NB, KR, HMM, SB), pp. 862–867.
DATE-2006-GianniniNBCCDB #design #power management: A synthesis tool for power-efficient base-band filter design (VG, PN, FDB, JC, BC, SD, AB), pp. 162–163.
DATE-2006-HeJ #configuration management #framework #named: RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics (CH, MFJ), pp. 1179–1184.
DATE-2006-HsuCK #constraints #energy #multi #realtime: Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint (HRH, JJC, TWK), pp. 1061–1066.
DATE-2006-IzosimovPEP #distributed #embedded #fault tolerance #performance #trade-off: Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems (VI, PP, PE, ZP), pp. 706–711.
DATE-2006-KastnerGHBKBS #communication #layout #optimisation: Layout driven data communication optimization for high level synthesis (RK, WG, XH, FB, AK, PB, MS), pp. 1185–1190.
DATE-2006-LeupersKKP #configuration management #design #embedded #set: A design flow for configurable embedded processors based on optimized instruction set extension synthesis (RL, KK, SK, MP), pp. 581–586.
DATE-2006-LiuH #logic: Crosstalk-aware domino logic synthesis (YYL, TH), pp. 1312–1317.
DATE-2006-ManolacheEP #communication #optimisation: Buffer space optimisation with communication synthesis and traffic shaping for NoCs (SM, PE, ZP), pp. 718–723.
DATE-2006-MartensE #top-down: Top-down heterogeneous synthesis of analog and mixed-signal systems (EM, GGEG), pp. 275–280.
DATE-2006-PanditKMP #hardware #higher-order: High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count (SP, SK, CAM, AP), pp. 1203–1204.
DATE-2006-SuHC: Droplet routing in the synthesis of digital microfluidic biochips (FS, WLH, KC), pp. 323–328.
DATE-2006-YangGZSD #adaptation #analysis #design: Adaptive chip-package thermal analysis for synthesis and design (YY, Z(G, CZ, LS, RPD), pp. 844–849.
DATE-2006-YangV #analysis #evaluation #performance: Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis (HY, RV), pp. 283–284.
DATE-DF-2006-DasMDC: Synthesis of system verilog assertions (SD, RM, PD, PPC), pp. 70–75.
DATE-DF-2006-FanucciCSKWSALM #design #image #linear: ASIP design and synthesis for non linear filtering in image processing (LF, MC, SS, DK, EMW, OS, GA, RL, HM), pp. 233–238.
DATE-DF-2006-HuttonYSBCCP #verification: A methodology for FPGA to structured-ASIC synthesis and verification (MH, RY, JS, GB, SC, KKC, HKP), pp. 64–69.
CAV-2006-KupfermanPV #composition: Safraless Compositional Synthesis (OK, NP, MYV), pp. 31–44.
CAV-2006-RosuB #linear #logic #ltl #monitoring: Allen Linear (Interval) Temporal Logic — Translation to LTL and Monitor Synthesis (GR, SB), pp. 263–277.
CSL-2006-Rabinovich #parametricity #problem: Church Synthesis Problem with Parameters (AMR), pp. 546–561.
FATES-RV-2006-SatpathyML #modelling #testing: Synthesis of Scenario Based Test Cases from B Models (MS, QAM, JL), pp. 133–147.
VMCAI-2006-PitermanPS #design: Synthesis of Reactive(1) Designs (NP, AP, YS), pp. 364–380.
CBSE-2005-GuH #component #implementation #modelling #realtime #scheduling: Real-Time Scheduling Techniques for Implementation Synthesis from Component-Based Software Models (ZG, ZH), pp. 235–250.
WICSA-2005-TivoliG #adaptation #architecture #component: Adaptor Synthesis for Protocol-Enhanced Component Based Architectures (MT, DG), pp. 276–277.
ICDAR-2005-Lin #documentation #layout: Active Document Layout Synthesis (XL), pp. 86–90.
ICDAR-2005-ZhengD: Handwriting Matching and Its Application to Handwriting Synthesis (YZ, DSD), pp. 861–865.
JCDL-2005-Blake #approach: Information synthesis: a new approach to explore secondary information in scientific literature (CB), pp. 56–64.
CSMR-2005-HuseliusA #realtime: Model Synthesis for Real-Time Systems (JH, JA), pp. 52–60.
FM-2005-SunD #distributed #process #specification: Synthesis of Distributed Processes from Scenario-Based Specifications (JS, JSD), pp. 415–431.
PADL-2005-Karczmarczuk #framework #functional: Functional Framework for Sound Synthesis (JK), pp. 7–21.
POPL-2005-AlurCMN #interface #java #specification: Synthesis of interface specifications for Java classes (RA, PC, PM, WN), pp. 98–109.
ASE-2005-FalbPRJAK #automation #specification #user interface #using: Using communicative acts in high-level specifications of user interfaces for their automated synthesis (JF, RP, TR, HJ, EA, HK), pp. 429–430.
ASE-2005-InverardiMTA #adaptation #approach #automation #component #distributed: Synthesis of correct and distributed adaptors for component-based systems: an automatic approach (PI, LM, MT, MA), pp. 405–409.
SAC-2005-DoxseeG #automation #c++ #specification: Synthesis of C++ software for automated teller from CSPm specifications (SD, WBG), pp. 1565–1566.
CASE-2005-ZhuD #design #layout: Grasp synthesis and fixture layout design in discrete domain (XZ, HD), pp. 73–78.
DAC-2005-AbdollahiP #canonical #logic #performance #verification: A new canonical form for fast boolean matching in logic synthesis and verification (AA, MP), pp. 379–384.
DAC-2005-BhuniaBCMR #approach #novel #power management #reduction #using: A novel synthesis approach for active leakage power reduction using dynamic supply gating (SB, NB, QC, HMM, KR), pp. 479–484.
DAC-2005-GielenME #modelling #performance: Performance space modeling for hierarchical synthesis of analog integrated circuits (GGEG, TM, TE), pp. 881–886.
DAC-2005-MukherjeeMM #resource management: Temperature-aware resource allocation and binding in high-level synthesis (RM, SOM, GM), pp. 196–201.
DAC-2005-PasrichaDBB #architecture #automation #communication: Floorplan-aware automated synthesis of bus-based communication architectures (SP, NDD, EB, MBR), pp. 565–570.
DAC-2005-RenG #framework #optimisation: A unified optimization framework for equalization filter synthesis (JR, MRG), pp. 638–643.
DAC-2005-SinghMB #incremental #physics: Incremental retiming for FPGA physical synthesis (DPS, VM, SDB), pp. 433–438.
DAC-2005-SuC05a: Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips (FS, KC), pp. 825–830.
DAC-2005-TangZB #library #optimisation #power management: Leakage power optimization with dual-Vth library in high-level synthesis (XT, HZ, PB), pp. 202–207.
DATE-2005-BadaouiV #multi #performance: Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis (RFB, RV), pp. 138–143.
DATE-2005-BomelMB #latency: Synchronization Processor Synthesis for Latency Insensitive Systems (PB, EM, EB), pp. 896–897.
DATE-2005-Dean #concurrent #integration #realtime #thread: Software Thread Integration and Synthesis for Real-Time Applications (AGD), pp. 68–69.
DATE-2005-Edwards #challenge #hardware: The Challenges of Hardware Synthesis from C-Like Languages (SAE), pp. 66–67.
DATE-2005-EeckelaertMG #multi #performance #using: Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces (TE, TM, GGEG), pp. 1070–1075.
DATE-2005-GadkariR #automation #monitoring #specification #using #visual notation: Automated Synthesis of Assertion Monitors using Visual Specifications (AAG, SR), pp. 390–395.
DATE-2005-MannionHCV #network #programmable: System Synthesis for Networks of Programmable Blocks (RM, HH, SC, FV), pp. 888–893.
DATE-2005-OgrasM #approach #architecture #communication #composition #energy #using: Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach (ÜYO, RM), pp. 352–357.
DATE-2005-Ruiz-SautuaMMH #behaviour #performance: Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis (RRS, MCM, JMM, RH), pp. 1252–1257.
DATE-2005-StergiouACRBM #abstract syntax tree #design #library #network #pipes and filters: ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips (SS, FA, SC, LR, DB, GDM), pp. 1188–1193.
DATE-2005-TangWD #complexity #power management: MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption (HT, YW, AD), pp. 264–269.
DATE-2005-TosunMAKX: Reliability-Centric High-Level Synthesis (ST, NM, EA, MTK, YX), pp. 1258–1263.
DATE-2005-YangHSP #logic #multi #quantum #using: Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory (GY, WNNH, XS, MAP), pp. 434–435.
TACAS-2005-HardingRS #algorithm #game studies #ltl: A New Algorithm for Strategy Synthesis in LTL Games (AH, MR, PYS), pp. 477–492.
LICS-2005-FinkbeinerS #distributed: Uniform Distributed Synthesis (BF, SS), pp. 321–330.
LICS-2005-Leroux #diagrams #polynomial: A Polynomial Time Presburger Criterion and Synthesis for Number Decision Diagrams (JL), pp. 147–156.
SAT-2005-LingSB #logic #quantifier #satisfiability #using: FPGA Logic Synthesis Using Quantified Boolean Satisfiability (ACL, DPS, SDB), pp. 444–450.
ICEIS-v5-2004-RaouzaiouKK: Emotion Synthesis in Virtual Environments (AR, KK, SDK), pp. 44–52.
ICPR-v1-2004-FilipH #bidirectional: Non-linear Reflectance Model for Bidirectional Texture Function Synthesis (JF, MH), pp. 80–83.
ICPR-v4-2004-AbboudD #recognition: Appearance Factorization based Facial Expression Recognition and Synthesis (BA, FD), pp. 163–166.
ICPR-v4-2004-CuiWHTS #image: An Iris Image Synthesis Method Based on PCA and Super-Resolution (JC, YW, JH, TT, ZS), pp. 471–474.
ICPR-v4-2004-ViswanathMB #classification #nearest neighbour #pattern matching #pattern recognition #performance #recognition: A Pattern Synthesis Technique with an Efficient Nearest Neighbor Classifier for Binary Pattern Recognition (PV, MNM, SB), pp. 416–419.
LOPSTR-2004-Colon #constraints #imperative #source code #theorem proving: Schema-Guided Synthesis of Imperative Programs by Constraint Solving (MC), pp. 166–181.
LOPSTR-2004-KulkarniBE #automation #fault tolerance #source code #verification: Mechanical Verification of Automatic Synthesis of Fault-Tolerant Programs (SSK, BB, AE), pp. 36–52.
LOPSTR-2004-WellsY #graph #proving: Graph-Based Proof Counting and Enumeration with Applications for Program Fragment Synthesis (JBW, BY), pp. 262–277.
PDCL-2004-BasinDFHN #logic #source code: Synthesis of Programs in Computational Logic (DAB, YD, PF, AH, JFN), pp. 30–65.
FSE-2004-UchitelCKM #architecture: System architecture: the context for scenario-based model synthesis (SU, RC, JK, JM), pp. 33–42.
ICSE-2004-ZiadiHJ #algebra #approach #statechart: Revisiting Statechart Synthesis with an Algebraic Approach (TZ, LH, JMJ), pp. 242–251.
SAC-2004-WebbW #analysis #biology: Combining analysis and synthesis in a model of a biological cell (KW, TW), pp. 185–190.
GPCE-2004-LiuB #automation #product line: Automatic Remodularization and Optimized Synthesis of Product-Families (JL, DSB), pp. 379–395.
DAC-2004-BriskKS #configuration management #design #set: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs (PB, AK, MS), pp. 395–400.
DAC-2004-ChengTM #embedded #named: FITS: framework-based instruction-set tuning synthesis for embedded application specific processors (ACC, GST, TNM), pp. 920–923.
DAC-2004-CongFZ #architecture #automation #pipes and filters: Architecture-level synthesis for automatic interconnect pipelining (JC, YF, ZZ), pp. 602–607.
DAC-2004-HungSYYP #analysis #logic #quantum #reachability: Quantum logic synthesis by symbolic reachability analysis (WNNH, XS, GY, JY, MAP), pp. 838–841.
DAC-2004-KapoorJ #concurrent #logic #specification: Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis (HKK, MBJ), pp. 830–833.
DAC-2004-KappS #automation #behaviour #control flow #scheduling: Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis (KK, VKS), pp. 61–66.
DAC-2004-Kerntopf #algorithm #heuristic #logic: A new heuristic algorithm for reversible logic synthesis (PK), pp. 834–837.
DAC-2004-KwonKK #functional #graph #metric: Systematic functional coverage metric synthesis from hierarchical temporal event relation graph (YSK, YIK, CMK), pp. 45–48.
DAC-2004-ZhangDRRC #performance #towards: A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits (GZ, EAD, RAR, RAR, LRC), pp. 155–158.
DATE-DF-2004-BruschiB #communication #design: A Design Methodology for the Exploitation of High Level Communication Synthesis (FB, MB), pp. 180–185.
DATE-DF-2004-LettninBBGR #case study #design #embedded #network: Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks (DL, AGB, MB, JG, WR), pp. 248–255.
DATE-DF-2004-Ruiz-AmayaRMFRPR #matlab: MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators (JRA, JLdlR, FM, FVF, RdR, MBPV, ÁRV), pp. 150–155.
DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation: RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.
DATE-v1-2004-AboushadyLBL #automation #simulation: Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators (HA, LdL, NB, MML), pp. 674–675.
DATE-v1-2004-BurnsSKY #tool support #using: An Asynchronous Synthesis Toolset Using Verilog (FPB, DS, AK, AY), pp. 724–725.
DATE-v1-2004-GuptaDGN #control flow #design: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow (SG, ND, RG, AN), pp. 114–121.
DATE-v1-2004-HounsellT #embedded: Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration (BIH, RT), pp. 682–683.
DATE-v1-2004-PatelMP #architecture #energy #memory management #multi: Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC (KP, EM, MP), pp. 700–701.
DATE-v1-2004-RanjanVASVG #modelling #performance #using: Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DATE-v1-2004-ThepayasuwanD #architecture #layout: Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (NT, AD), pp. 108–113.
DATE-v2-2004-AgrawalJ #logic: Synthesis of Reversible Logic (AA, NKJ), pp. 1384–1385.
DATE-v2-2004-LanD #analysis #modelling: Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs (HL, RWD), pp. 836–843.
DATE-v2-2004-LiuWH #logic: Crosstalk Minimization in Logic Synthesis for PLA (YYL, KHW, TH), pp. 790–795.
DATE-v2-2004-LiverisB #design #interface #power management: Power Aware Interface Synthesis for Bus-Based SoC Design (NDL, PB), pp. 864–869.
DATE-v2-2004-NardiS: Synthesis for Manufacturability: A Sanity Check (AN, ALSV), pp. 796–803.
DATE-v2-2004-ZhangGZJ #logic #network #optimisation: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies (RZ, PG, LZ, NKJ), pp. 904–909.
LCTES-2004-QinRM #architecture #concurrent #development #modelling #tool support: A formal concurrency model based architecture description language for synthesis of software development tools (WQ, SR, SM), pp. 47–56.
FASE-2004-ChildsGRDDHJSS #analysis #component #development #ide #named #verification: Cadena: An Integrated Development Environment for Analysis, Synthesis, and Verification of Component-Based Systems (AC, JG, VPR, XD, MBD, JH, GJ, PS, GS), pp. 160–164.
VMCAI-2004-PodelskiR #linear #ranking: A Complete Method for the Synthesis of Linear Ranking Functions (AP, AR), pp. 239–251.
CIAA-2003-WallmeierHT #finite #specification: Symbolic Synthesis of Finite-State Controllers for Request-Response Specifications (NW, PH, WT), pp. 11–22.
FME-2003-BoyerS #constraints #protocol #verification: Synthesis and Verification of Constraints in the PGM Protocol (MB, MS), pp. 264–281.
ICEIS-v3-2003-BalabkoW #concept #modelling: A Synthesis of Business Role Models: Conceptual Tool for Business Innovations (PB, AW), pp. 211–220.
ICML-2003-KrawiecB #learning #visual notation: Visual Learning by Evolutionary Feature Synthesis (KK, BB), pp. 376–383.
LOPSTR-2003-AlexandreBD #induction #proving: Predicate Synthesis from Inductive Proof Attempt of Faulty Conjectures (FA, KB, MD), pp. 20–33.
LOPSTR-2003-Ellman #animation #automaton #hybrid #specification: Specification and Synthesis of Hybrid Automata for Physics-Based Animation (TE), pp. 54–55.
LOPSTR-2003-FischerV #prolog #syntax: Adding Concrete Syntax to a Prolog-Based Program Synthesis System (BF, EV), pp. 56–58.
ASE-2003-Ellman #animation #automaton #hybrid #specification: Specification and Synthesis of Hybrid Automata for Physics-Based Animation (TE), pp. 80–93.
DAC-2003-ChanKLNR #performance #physics: Physical synthesis methodology for high performance microprocessors (YHC, PK, LBL, GAN, TER), pp. 696–701.
DAC-2003-ChenGK: Performance-impact limited area fill synthesis (YC, PG, ABK), pp. 22–27.
DAC-2003-MemikMJK #data flow #graph #resource management: Global resource sharing for synthesis of control data flow graphs on FPGAs (SOM, GM, RJ, EK), pp. 604–609.
DAC-2003-MillerMD #algorithm #logic: A transformation based algorithm for reversible logic synthesis (DMM, DM, GWD), pp. 318–323.
DAC-2003-NohlGBALSM #architecture #encoding #modelling #using: Instruction encoding synthesis for architecture exploration using hierarchical processor models (AN, VG, GB, AH, RL, OS, HM), pp. 262–267.
DAC-2003-QinM #automation #performance: Automated synthesis of efficient binary decoders for retargetable software toolkits (WQ, SM), pp. 764–769.
DAC-2003-RiedelB: The synthesis of cyclic combinational circuits (MDR, JB), pp. 163–168.
DAC-2003-SoDH #behaviour #design #tool support #using: Using estimates from behavioral synthesis tools in compiler-directed design space exploration (BS, PCD, MWH), pp. 514–519.
DAC-2003-WongM #composition #data-driven: High-level synthesis of asynchronous systems by data-driven decomposition (CGW, AJM), pp. 508–513.
DAC-2003-YuanAAP #constraints #functional #modelling #verification: Constraint synthesis for environment modeling in functional verification (JY, KA, AA, CP), pp. 296–299.
DATE-2003-BombanaB: SystemC-VHDL Co-Simulation and Synthesis in the HW Domain (MB, FB), pp. 20101–20105.
DATE-2003-BruschiF #behaviour #modelling: Synthesis of Complex Control Structures from Behavioral SystemC Models (FB, FF), pp. 20112–20119.
DATE-2003-ChiouBR #multi #power management: Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications (LYC, SB, KR), pp. 10096–10103.
DATE-2003-ChooMR #architecture #named #power management: MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters (HC, KM, KR), pp. 10700–10705.
DATE-2003-GuptaDGN #branch #design: Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs (SG, NDD, RKG, AN), pp. 10270–10275.
DATE-2003-HaubeltTFM #satisfiability: SAT-Based Techniques in System Synthesis (CH, JT, RF, BM), pp. 11168–11169.
DATE-2003-IskanderDAMHSM #using: Synthesis of CMOS Analog Cells Using AMIGO (RI, MD, MA, MM, NH, NS, SM), pp. 20297–20302.
DATE-2003-KrausP #flexibility #named: XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines (OK, MP), pp. 11092–11093.
DATE-2003-NielsenM: Power Constrained High-Level Synthesis of Battery Powered Digital Systems (SFN, JM), pp. 11136–11137.
DATE-2003-OikonomakosZA #metric #online #self #testing #using: Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric (PO, MZ, BMAH), pp. 10596–10601.
DATE-2003-PopEP #analysis #clustering #distributed #embedded #multi #optimisation #scheduling: Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems (PP, PE, ZP), pp. 10184–10189.
DATE-2003-WuAE #embedded #graph #power management #scheduling: Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems (DW, BMAH, PE), pp. 10090–10095.
LCTES-2003-Wasowski #on the #performance: On efficient program synthesis from statecharts (AW), pp. 163–170.
CSL-2003-Walukiewicz: Winning Strategies and Synthesis of Controllers (IW), p. 574.
CBSE-2002-SchmidtR #adaptation #contract: Parameterised Contracts and Adapter Synthesis (HWS, RR), p. 6.
CBSE-2003-InverardiT #assembly #component #composition: A compositional synthesis of failure-free connectors for correct components assembly (PI, MT), p. 17.
JCDL-2002-Bergmark: Collection synthesis (DB), pp. 253–262.
PODS-2002-CadoliM #compilation #query: Knowledge Compilation = Query Rewriting + View Synthesis (MC, TM), pp. 199–208.
ICALP-2002-Cachat #automaton #game studies #graph: Symbolic Strategy Synthesis for Games on Pushdown Graphs (TC), pp. 704–715.
ICALP-2002-HenzingerKKM: Synthesis of Uninitialized Systems (TAH, SCK, OK, FYCM), pp. 644–656.
FME-2002-Basin #calculus: The Next 700 Synthesis Calculi (DAB), p. 430.
ICPR-v1-2002-YuLC #multi: Multiresolution Block Sampling-Based Method for Texture Synthesis (YY, JL, CWC), pp. 239–242.
ICPR-v2-2002-AraqueBCNV #image: Synthesis of Fingerprint Images (JLA, MB, BEC, DN, PRV), pp. 422–425.
ICPR-v3-2002-Vasilescu #analysis #recognition: Human Motion Signatures: Analysis, Synthesis, Recognition (MAOV), pp. 456–460.
ICPR-v4-2002-DassJL #detection #markov #modelling #random #using: Face Detection and Synthesis Using Markov Random Field Models (SCD, AKJ, XL), pp. 201–204.
SEKE-2002-CavalcantiV #approach #automation #maintenance #web: A logic-based approach for automatic synthesis and maintenance of web sites (JMBC, WWV), pp. 619–626.
LOPSTR-2002-AbdennadherR #constraints #logic programming #theorem proving #using: Constraint Solver Synthesis Using Tabled Resolution for Constraint Logic Programming (SA, CR), pp. 32–47.
LOPSTR-2002-AkamaNK: Program Synthesis Based on the Equivalent Transformation Computation Model (KA, EN, HK), pp. 278–279.
ASE-2002-EllmanDF #animation #knowledge-based #simulation #source code: Knowledge-Based Synthesis of Numerical Programs for Simulation of Rigid-Body Systems in Physics-Based Animation (TE, RD, JF), p. 93–?.
ASE-2002-RoachB #automation #case study #deduction #experience: Experience Report on Automated Procedure Construction for Deductive Synthesis (SR, JVB), p. 69–?.
ASE-2002-Stefanescu #automation #distributed: Automatic Synthesis of Distributed Systems (AS), p. 315.
ICSE-2002-DengDHM #concurrent #invariant #source code #specification #verification: Invariant-based specification, synthesis, and verification of synchronization in concurrent programs (XD, MBD, JH, MM), pp. 442–452.
GPCE-2002-NeemaBGG #adaptation #distributed #embedded #generative #realtime: Generators for Synthesis of QoS Adaptation in Distributed Real-Time Embedded Systems (SN, TB, JG, ASG), pp. 236–251.
DAC-2002-DrinicK #behaviour: Behavioral synthesis via engineering change (MD, DK), pp. 18–21.
DAC-2002-GuptaSDGNKKR #coordination #performance: Coordinated transformations for high-level synthesis of high performance microprocessor blocks (SG, NS, NDD, RKG, AN, TK, MK, SR), pp. 898–903.
DAC-2002-HrkicL #named: S-Tree: a technique for buffered routing tree synthesis (MH, JL), pp. 578–583.
DAC-2002-JiangB #logic #simulation #specification #using: Software synthesis from synchronous specifications using logic simulation techniques (YJ, RKB), pp. 319–324.
DAC-2002-KangSC #power management: An optimal voltage synthesis technique for a power-efficient satellite application (DIK, JS, SPC), pp. 492–497.
DAC-2002-MolinaMH #multi: High-level synthesis of multiple-precision circuitsindependent of data-objects length (MCM, JMM, RH), pp. 612–615.
DAC-2002-OhH #data flow #graph #multi #performance: Efficient code synthesis from extended dataflow graphs for multimedia applications (HO, SH), pp. 275–280.
DAC-2002-PintoCS #communication #constraints: Constraint-driven communication synthesis (AP, LPC, ALSV), pp. 783–788.
DAC-2002-SeoKP #algorithm #memory management: An integrated algorithm for memory allocation and assignment in high-level synthesis (JS, TK, PRP), pp. 608–611.
DAC-2002-SiegmundM #communication #declarative #hardware #novel #protocol #specification: A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications (RS, DM), pp. 602–607.
DAC-2002-UmK: Layout-aware synthesis of arithmetic circuits (JU, TK), pp. 207–212.
DAC-2002-WongMP #concept: Forward-looking objective functions: concept & applications in high level synthesis (JLW, SM, MP), pp. 904–909.
DATE-2002-ChelceaNBE: A Burst-Mode Oriented Back-End for the Balsa Synthesis System (TC, SMN, AB, DAE), pp. 330–337.
DATE-2002-ChenS #scheduling: Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis (CC, MS), pp. 1016–1020.
DATE-2002-JungKK #logic #performance: Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain (SOJ, KWK, SMK), pp. 260–265.
DATE-2002-MunzenbergerDSH #design #embedded #realtime #specification #validation: A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems (RM, MD, FS, RH), p. 1095.
DATE-2002-PandiniPS #logic: Congestion-Aware Logic Synthesis (DP, LTP, AJS), pp. 664–671.
LCTES-SCOPES-2002-OhH #data flow #multi #performance: Fractional rate dataflow model and efficient code synthesis for multimedia applications (HO, SH), pp. 12–17.
CADE-2002-WhalenSF #automation #certification #named: AutoBayes/CC — Combining Program Synthesis with Automatic Code Certification — System Description (MWW, JS, BF), pp. 290–294.
ISSTA-2002-Yavuz-KahveciB #component #concurrent #specification #verification: Specification, verification, and synthesis of concurrency control components (TYK, TB), pp. 169–179.
TestCom-2002-Jard #distributed #modelling: Principles of Distributed Test Synthesis based on True-concurrency Models (CJ), pp. 301–316.
CBSE-2001-Hamlet #component #problem: Component Synthesis Theory: The Problem of Scale (DH), p. 15.
ICDAR-2001-AmanoAMSS #analysis #documentation #grammarware: Table Form Document Synthesis by Grammar-Based Structure Analysis (AA, NA, TM, TS, KS), pp. 533–539.
ITiCSE-2001-Vat #design #education #human-computer: Teaching HCI with scenario-based design: the constructivist’s synthesis (KHV), pp. 9–12.
ICALP-2001-MadhusudanT #distributed #specification: Distributed Controller Synthesis for Local Specifications (PM, PST), pp. 396–407.
RE-2001-Lowry #question #requirements: Requirements Engineering and Program Synthesis: Mutually Exclusive or Synergistic? (MRL), pp. 12–13.
ASE-2001-CookIM #higher-order #proving #theorem proving: Higher Order Function Synthesis Through Proof Planning (AC, AI, GM), pp. 307–310.
ASE-2001-Denney #algorithm #java: The Synthesis of a Java Card Tokenization Algorithm (ED), pp. 43–50.
ASE-2001-InverardiS #architecture #component #concurrent: Connectors Synthesis for Deadlock-Free Component-Based Architectures (PI, SS), p. 174–?.
ASE-2001-WhittleBSRPPOLB #deduction #estimation #named: Amphion/NAV: Deductive Synthesis of State Estimation Software (JW, JVB, JS, PR, TP, JP, PO, MRL, GPB), pp. 395–399.
ESEC-FSE-2001-InverardiT #automation #concurrent: Automatic synthesis of deadlock free connectors for COM/DCOM applications (PI, MT), pp. 121–131.
DAC-2001-BeniniMMMP #architecture #embedded #layout #memory management: From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (LB, LM, AM, EM, MP), pp. 784–789.
DAC-2001-BruniBB #design #statistics: Statistical Design Space Exploration for Application-Specific Unit Synthesis (DB, AB, LB), pp. 641–646.
DAC-2001-DoboliV #constraints #design: Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints (AD, RV), pp. 629–634.
DAC-2001-GanesanV #behaviour #clustering: Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems (SG, RV), pp. 133–138.
DAC-2001-GuptaSKDGN #design: Speculation Techniques for High Level Synthesis of Control Intensive Designs (SG, NS, SK, NDD, RKG, AN), pp. 269–272.
DAC-2001-KuhnOWREK #framework #hardware #object-oriented #specification #verification: A Framework for Object Oriented Hardware Specification, Verification, and Synthesis (TK, TO, MW, WR, ME, YK), pp. 413–418.
DAC-2001-ParkK #representation: Digital Filter Synthesis Based on Minimal Signed Digit Representation (ICP, HJK), pp. 468–473.
DAC-2001-PeymandoustM #algebra #algorithm #using: Using Symbolic Algebra in Algorithmic Level DSP Synthesis (AP, GDM), pp. 277–282.
DAC-2001-TheobaldN #distributed #optimisation: Transformations for the Synthesis and Optimization of Asynchronous Distributed Control (MT, SMN), pp. 263–268.
DAC-2001-YuYW #representation #using: Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits (ZY, MLY, ANWJ), pp. 456–461.
DATE-2001-EconomakosOPPP #behaviour: Behavioral synthesis with systemC (GE, PO, IP, IP, GKP), pp. 21–25.
DATE-2001-IrionKVW #clustering #logic #performance: Circuit partitioning for efficient logic BIST synthesis (AI, GK, HPEV, HJW), pp. 86–91.
DATE-2001-NayakHCB #analysis #automation #fault #hardware #matlab #precise: Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs (AN, MH, ANC, PB), pp. 722–728.
DATE-2001-OuaissV #configuration management #memory management: Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers (IO, RV), pp. 650–657.
LCTES-OM-2001-KangCS #design #distributed #power management #realtime: Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems (DIK, SPC, JS), pp. 20–28.
TACAS-2001-ColonS #linear #ranking: Synthesis of Linear Ranking Functions (MC, HS), pp. 67–81.
ICPR-v1-2000-Boufama #using: The Use of Homographies for View Synthesis (BB), pp. 1563–1566.
ICPR-v2-2000-SanfeliuAS #clustering #graph: Clustering of Attributed Graphs and Unsupervised Synthesis of Function-Described Graphs (AS, RA, FS), pp. 6022–6025.
ICPR-v4-2000-WorthingtonH00a: View Synthesis from Needle-Maps (PLW, ERH), pp. 4110–4113.
LOPSTR-2000-AvelloneFF #framework #logic programming #source code #verification: A formal framework for synthesis and verification of logic programs (AA, MF, CF).
LOPSTR-J-2000-AvelloneFF #framework #logic programming #source code #verification: A Formal Framework for Synthesis and Verification of Logic Programs (AA, MF, CF), pp. 1–17.
DAC-2000-BeniniMMP #embedded #optimisation: Synthesis of application-specific memories for power optimization in embedded systems (LB, AM, EM, MP), pp. 300–303.
DAC-2000-ChenKRZ: Practical iterated fill synthesis for CMP uniformity (YC, ABK, GR, AZ), pp. 671–674.
DAC-2000-ChouB #coordination #distributed #embedded #optimisation: Synthesis and optimization of coordination controllers for distributed embedded systems (PHC, GB), pp. 410–415.
DAC-2000-DoughertyT #behaviour #design #physics: Unifying behavioral synthesis and physical design (WED, DET), pp. 756–761.
DAC-2000-KimNK #logic: Domino logic synthesis minimizing crosstalk (KWK, UN, SMK), pp. 280–285.
DAC-2000-NarasimhanR #bound #on the #problem #scheduling: On lower bounds for scheduling problems in high-level synthesis (MN, JR), pp. 546–551.
DAC-2000-PhelpsKRCH #case study: A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC (RP, MK, RAR, LRC, JRH), pp. 1–6.
DAC-2000-UmKL #fine-grained #optimisation #power management: A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis (JU, TK, CLL), pp. 98–103.
DATE-2000-BringmannRM #architecture #multi: Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation (OB, WR, CM), pp. 326–332.
DATE-2000-CarroKWO #embedded #multi: System Synthesis for Multiprocessor Embedded Applications (LC, MEK, FRW, MO), pp. 697–702.
DATE-2000-DessoukyLP #performance: Layout-Oriented Synthesis of High Performance Analog Circuits (MD, MML, JP), pp. 53–57.
DATE-2000-DonathKSVRSC: Transformational Placement and Synthesis (WED, PK, LS, PV, LNR, AS, KC), pp. 194–201.
DATE-2000-JosephsF #interface #specification: Delay-Insensitive Interface Specification and Synthesis (MBJ, DPF), pp. 169–173.
DATE-2000-KravetsS #symmetry #using: Constructive Library-Aware Synthesis Using Symmetries (VNK, KAS), pp. 208–213.
DATE-2000-OzevBO: Test Synthesis for Mixed-Signal SOC Paths (SO, IB, AO), pp. 128–133.
DATE-2000-SemeriaSM #behaviour #c #memory management #pointer: Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C (LS, KS, GDM), pp. 312–319.
DATE-2000-ShenoyBC #algorithm #quality: A System-Level Synthesis Algorithm with Guaranteed Solution Quality (UNS, PB, ANC), pp. 417–424.
DATE-2000-YangC #logic: Synthesis for Mixed CMOS/PTl Logic (CY, MJC), p. 750.
FASE-2000-HuneS #automaton #case study #using: A Case Study on Using Automata in Control Synthesis (TH, AS), pp. 349–362.
CL-2000-LaceyRS #higher-order #logic programming: Logic Program Synthesis in a Higher-Order Setting (DL, JR, AS), pp. 87–100.
WCRE-1999-WatersA #architecture #multi: Architectural Synthesis: Integrating Multiple Architectural Perspectives (RW, GDA), pp. 2–12.
FM-v1-1999-TripakisA #on the fly: On-the-Fly Controller Synthesis for Discrete and Dense-Time Systems (ST, KA), pp. 233–252.
FM-v1-1999-TyuguMP #source code: Applications of Structural Synthesis of Programs (ET, MM, JP), pp. 551–569.
FM-v2-1999-GarbettPSA #empirical #process: Secure Synthesis of Code: A Process Improvement Experiment (PG, JPP, MS, SA), pp. 1816–1835.
FM-v2-1999-MarchandS #design #incremental #using: Incremental Design of a Power Transformer Station Controller Using a Controller Synthesis Methodology (HM, MS), pp. 1605–1624.
HCI-CCAD-1999-WatanabeO #analysis #communication #interactive: Virtual face-to-face communication system for human interaction analysis by synthesis (TW, MO), pp. 182–186.
KDD-1999-BuntineFP #automation #data mining #mining #source code #towards: Towards Automated Synthesis of Data Mining Programs (WLB, BF, TP), pp. 372–376.
ASE-1999-EmersonB #constraints #development #specification: Development of a Constraint-Based Airlift Scheduler by Program Synthesis from Formal Specifications (TE, MHB), pp. 267–270.
ASE-1999-FischerW #deduction #integration #retrieval: An Integration of Deductive Retrieval into Deductive Synthesis (BF, JW), p. 52–?.
ASE-1999-Penix99a #architecture #deduction: Deductive Synthesis of Event-Based Software Architectures (JP), pp. 311–314.
ASE-1999-StarkI #automation #imperative #proving #theorem proving #towards: Towards Automatic Imperative Program Synthesis Through Proof Planning (JS, AI), pp. 44–51.
ASE-1999-Tronci #automation #industrial: Automatic Synthesis of Control Software for an Industrial Automation Control System (ET), pp. 247–250.
ASE-1999-WilliamsonH #category theory #industrial: Industrial Applications of Software Synthesis via Category Theory (KEW, MH), pp. 35–43.
ICSE-1999-EzranMT #case study #experience #industrial #reuse #source code: Failure and Success Factors in Reuse Programs: A Synthesis of Industrial Experiences (ME, MM, CT), pp. 681–682.
DAC-1999-BeniniMMPS #communication #interface #power management: Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses (LB, AM, EM, MP, RS), pp. 128–133.
DAC-1999-Bergamaschi #behaviour #graph #logic #network: Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis (RAB), pp. 213–218.
DAC-1999-DoboliNDGV #behaviour #design #using: Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration (AD, ANA, NRD, SG, RV), pp. 951–957.
DAC-1999-ErcegovacKP #behaviour #multi #optimisation #power management #precise #using: Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic (MDE, DK, MP), pp. 568–573.
DAC-1999-HongP #behaviour: Behavioral Synthesis Techniques for Intellectual Property Protection (IH, MP), pp. 849–854.
DAC-1999-KaulVGO #approach #automation #clustering #configuration management: An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications (MK, RV, SG, IO), pp. 616–622.
DAC-1999-KimHT #on the #self: On ILP Formulations for Built-In Self-Testable Data Path Synthesis (HBK, DSH, TT), pp. 742–747.
DAC-1999-KirovskiP #behaviour: Engineering Change: Methodology and Applications to Behavioral and System Synthesis (DK, MP), pp. 604–609.
DAC-1999-KondratyevCKLY #automation #optimisation: Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems (AK, JC, MK, LL, AY), pp. 110–115.
DAC-1999-KrasnickiPRC #named #performance: MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells (MK, RP, RAR, LRC), pp. 945–950.
DAC-1999-MukherjeeSML #layout #novel: Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique (AM, RS, MMS, SIL), pp. 466–471.
DAC-1999-PatraN #automation #power management: Automated Phase Assignment for the Synthesis of Low Power Domino Circuits (PP, UN), pp. 379–384.
DAC-1999-RichterZETT #embedded #optimisation #representation: Representation of Function Variants for Embedded System Optimization and Synthesis (KR, DZ, RE, LT, JT), pp. 517–522.
DAC-1999-SgroiL #embedded #petri net #using: Synthesis of Embedded Software Using Free-Choice Petri Nets (MS, LL), pp. 805–810.
DAC-1999-SundararajanP #power management #using: Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages (VS, KKP), pp. 72–75.
DAC-1999-ZhuG #scheduling: Soft Scheduling in High Level Synthesis (JZ, DG), pp. 219–224.
DATE-1999-CarlettaNP #testing: Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs (JC, MN, CAP), pp. 278–282.
DATE-1999-DhanwadaNV #constraints #using: Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis (NRD, ANA, RV), p. 328–?.
DATE-1999-DickJ #multi #named: MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis (RPD, NKJ), pp. 263–270.
DATE-1999-DoboliV #architecture #behaviour #compilation #generative: A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems (AD, RV), pp. 338–345.
DATE-1999-EvekingHR #automation #scheduling #verification: Automatic Verification of Scheduling Results in High-Level Synthesis (HE, HH, GR), pp. 59–64.
DATE-1999-GhoshKL #c #c++ #hardware: Hardware Synthesis from C/C++ (AG, JK, SYL), pp. 387–389.
DATE-1999-JantschKH #analysis #case study #concept #modelling: The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems (AJ, SK, AH), pp. 256–262.
DATE-1999-KimKHL #logic #power management: Logic Transformation for Low Power Synthesis (KWK, SMK, TH, CLL), pp. 158–162.
DATE-1999-MakrisO #behaviour #reachability: Channel-Based Behavioral Test Synthesis for Improved Module Reachability (YM, AO), pp. 283–288.
DATE-1999-Micheli #c #c++ #hardware #modelling: Hardware Synthesis from C/C++ Models (GDM), pp. 382–383.
DATE-1999-Nunez-AldanaV #effectiveness #performance: An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis (ANA, RV), pp. 406–411.
DATE-1999-ONilsJ #implementation #independence #operating system #protocol #specification: Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification (MO, AJ), pp. 562–567.
DATE-1999-RadetzkiSPN #analysis #data type #hardware #modelling #object-oriented: Data Type Analysis for Hardware Synthesis from Object-Oriented Models (MR, AS, WPR, WN), p. 491–?.
DATE-1999-VercauterenSV #constraints #generative #hardware #interface #realtime: Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints (SV, JvdS, DV), pp. 556–561.
DATE-1999-Wakabayashi #behaviour #case study #experience: C-based Synthesis Experiences with a Behavior Synthesizer, “Cyber” (KW), p. 390–?.
LCTES-1999-KangGGHS #design #distributed #embedded: A Software Synthesis Tool for Distributed Embedded System Design (DIK, RG, LG, JKH, MS), pp. 87–95.
CHI-1998-ZhouF #automation #visual notation: Visual Task Characterization for Automated Visual Discourse Synthesis (MXZ, SF), pp. 392–399.
ICPR-1998-AsadaBA #approach #image: Calibrated computer graphics: a new approach to realistic image synthesis based on camera calibration (NA, MB, AA), pp. 705–707.
ICPR-1998-MaruyamaAN #bidirectional #recognition: Face recognition by bidirectional view synthesis (MM, SA, YN), pp. 157–159.
ICPR-1998-PagetL #markov #multi #parametricity #random #recognition: Texture synthesis and unsupervised recognition with a nonparametric multiscale Markov random field model (RP, DL), pp. 1068–1070.
UML-1998-KhrissEK #automation #collaboration #diagrams #multi #statechart #uml: Automating the Synthesis of UML StateChart Diagrams from Multiple Collaboration Diagrams (IK, ME, RKK), pp. 132–147.
TOOLS-ASIA-1998-Hsiung98a #message passing #object-oriented #parallel: Parallel Object-Oriented Synthesis Environment Based On Message-Passing (PAH), p. 251–?.
LOPSTR-1998-AvelloneFM #data type #source code: Synthesis of Programs in Abstract Data Types (AA, MF, PM), pp. 81–100.
LOPSTR-1998-BaalenR #deduction #using: Using Decision Procedures to Accelerate Domain-Specific Deductive Synthesis Systems (JVB, SR), pp. 61–70.
LOPSTR-1998-BellotR #imperative #logic #source code: Logical Synthesis of Imperative O. O. Programs (PB, BR), pp. 316–318.
LOPSTR-1998-HamfeltN #combinator #composition #induction #logic programming #source code: Inductive Synthesis of Logic Programs by Composition of Combinatory Program Schemes (AH, JFN), pp. 143–158.
LOPSTR-1998-RobertsonA #logic programming #source code: Pragmatics in the Synthesis of Logic Programs (DSR, JAC), pp. 41–60.
LOPSTR-1998-ZidoumFH #source code: Schema-Guided Synthesis of CLP Programs (HZ, PF, BH), pp. 309–312.
ASE-1998-BlaineGLSW #named: Planware — Domain-Specific Synthesis of High-Performance Schedulers (LB, LG, JL, DRS, SJW), p. 270–?.
ASE-1998-FlenerZH #constraints #logic programming #source code: Schema-Guided Synthesis of Constraint Logic Programs (PF, HZ, BH), pp. 168–176.
SAC-1998-EconomakosPT #attribute grammar #multi: Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs (GE, GKP, PT), pp. 45–49.
DAC-1998-JiangJH #composition #encoding: Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis (JHRJ, JYJ, JDH), pp. 712–717.
DAC-1998-KishinevskyCK #analysis #interface #specification: Asynchronous Interface Specification, Analysis and Synthesis (MK, JC, AK), pp. 2–7.
DAC-1998-KravetsS #logic #multi #named: M32: A Constructive multilevel Logic Synthesis System (VNK, KAS), pp. 336–341.
DAC-1998-LakshminarayanaJ98a #behaviour #power management: Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions (GL, NKJ), pp. 439–444.
DAC-1998-Lin #concurrent #source code: Software Synthesis of Process-Based Concurrent Programs (BL), pp. 502–505.
DAC-1998-PasseroneRS #automation #interface #protocol: Automatic Synthesis of Interfaces Between Incompatible Protocols (RP, JAR, ALSV), pp. 8–13.
DAC-1998-SilvaYMCWJCVSM #data transfer #performance: Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer (JLdSJ, CYC, MM, KC, SW, GGdJ, FC, DV, PS, HDM), pp. 76–81.
DAC-1998-TarafdarL #data transfer #using: The DT-Model: High-Level Synthesis Using Data Transfers (ST, ML), pp. 114–117.
DATE-1998-BringmannR: Cross-Level Hierarchical High-Level Synthesis (OB, WR), pp. 451–456.
DATE-1998-ElesKPDP #embedded #graph #process #scheduling: Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems (PE, KK, ZP, AD, PP), pp. 132–138.
DATE-1998-GasteierGM #communication #generative: Generation of Interconnect Topologies for Communication Synthesis (MG, MG, MM), pp. 36–42.
DATE-1998-GhoshKBH #benchmark #equivalence #invariant #metric: Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking (DG, NK, FB, JEHI), pp. 656–663.
DATE-1998-GongCK #architecture: Architectural Rule Checking for High-level Synthesis (JG, CTC, KK), pp. 949–950.
DATE-1998-HansenKR #comparison #interface #simulation #using #verification: Verification by Simulation Comparison using Interface Synthesis (CH, AK, WR), pp. 436–443.
DATE-1998-JemaiKJ #architecture #behaviour #simulation: Architectural Simulation in the Context of Behavioral Synthesis (AJ, PK, AAJ), pp. 590–595.
DATE-1998-KaulV #architecture #clustering #configuration management: Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures (MK, RV), pp. 389–396.
DATE-1998-KhouriLJ #control flow #named #power management: IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits (KSK, GL, NKJ), pp. 848–854.
DATE-1998-LagoJLSB #fuzzy #logic #named: XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers (EL, CJJ, DRL, SSS, ABB), pp. 102–107.
DATE-1998-MendiasH #formal method #perspective: Correct High-Level Synthesis: a Formal Perspective (JMM, RH), pp. 977–978.
DATE-1998-NiemannM #communication #concurrent #hardware: Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems (RN, PM), pp. 912–913.
DATE-1998-ObergHK #communication #grammarware #hardware #protocol #scheduling: Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols (JÖ, AH, AK), pp. 596–603.
DATE-1998-PomeranzR #flexibility #logic: A Synthesis Procedure for Flexible Logic Functions (IP, SMR), pp. 973–974.
DATE-1998-XuK #architecture: Layout-Driven High Level Synthesis for FPGA Based Architectures (MX, FJK), pp. 446–450.
DATE-1998-YangP #algorithm #performance #scheduling: An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis (LTY, ZP), pp. 74–81.
DATE-1998-YiCPHK #behaviour #multi: Multiple Behavior Module Synthesis Based on Selective Groupings (JHY, HC, ICP, SHH, CMK), pp. 384–388.
LCTES-1998-ChildersD #design #pipes and filters: A Design Environment for Counterflow Pipeline Synthesis (BRC, JWD), pp. 113–234.
FASE-1998-MargariaS #automation #backtracking #design: Backtracking-Free Design Planning by Automatic Synthesis in METAFrame (TMS, BS), pp. 188–204.
LICS-1998-Tatsuta: Realizability for Constructive Theory of Functions and Classes and its Application to Program Synthesis (MT), pp. 358–367.
ICFP-1997-Ostvold #functional #induction #recursion #source code: Inductive Synthesis of Recursive Functional Programs (Poster Abstract) (BMØ), p. 323.
ICFP-1997-Pareja-FloresV #constraints: Synthesis of Functions by Transformations and Constraints (CPF, JÁVI), p. 317.
HCI-SEC-1997-Morishima #communication #recognition: Expression Recognition and Synthesis for Face-to-Face Communication (SM), pp. 415–418.
TOOLS-ASIA-1997-HsiungLC #multi #object-oriented: Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis (PAH, TYL, SJC), pp. 284–293.
LOPSTR-1997-BibelKKKOSS #approach #multi: A Multi-level Approach to Program Synthesis (WB, DSK, CK, FK, JO, SS, GS), pp. 1–27.
LOPSTR-1997-Christiansen: Implicit Program Synthesis by a Reversible Metainterpreter (HC), pp. 90–110.
LOPSTR-1997-SemeraroEMFF #datalog #framework #incremental #induction #logic: A Logic Framework for the Incremental Inductive Synthesis of Datalog Theories (GS, FE, DM, NF, SF), pp. 300–321.
ASE-1997-ArmandoSG #automation #paradigm #recursion #source code: Automatic Synthesis of Recursive Programs: The Proof-Planning Paradigm (AA, AS, IG), pp. 2–9.
ASE-1997-FlenerLO #source code: Correct-Schema-Guided Synthesis of Steadfast Programs (PF, KKL, MO), p. 153–?.
ASE-1997-MatskinT #source code: Strategies of Structural Synthesis of Programs (MM, ET), pp. 305–306.
DAC-1997-ChangLMAC #approach: A Test Synthesis Approach to Reducing BALLAST DFT Overhead (DC, MTCL, MMS, TA, KTC), pp. 466–471.
DAC-1997-CongW #pipes and filters: FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (JC, CW), pp. 644–649.
DAC-1997-CroixW #logic #performance: A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis (JFC, DFW), pp. 337–340.
DAC-1997-GuruswamyMDRCFJ #automation #layout #library #named #standard: CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries (MG, RLM, DD, SR, VC, AF, LGJ), pp. 327–332.
DAC-1997-HsiehPMR #evaluation: Profile-Driven Program Synthesis for Evaluation of System Power Dissipation (CTH, MP, GM, FR), pp. 576–581.
DAC-1997-KimC #using: Power-conscious High Level Synthesis Using Loop Folding (DK, KC), pp. 441–445.
DAC-1997-KimKP #programmable: Synthesis of Application Specific Programmable Processors (KK, RK, MP), pp. 353–358.
DAC-1997-KirovskiP #power management #realtime: System-Level Synthesis of Low-Power Hard Real-Time Systems (DK, MP), pp. 697–702.
DAC-1997-LefebvreMS #future of #generative #physics: The Future of Custom Cell Generation in Physical Synthesis (ML, DM, CS), pp. 446–451.
DAC-1997-LiW #memory management #multi: A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors (YL, WW), pp. 153–156.
DAC-1997-MeyerST #array #design: Design and Synthesis of Array Structured Telecommunication Processing Applications (WM, AS, FT), pp. 486–491.
DAC-1997-PandaN #power management: Technology-Dependent Transformations for Low-Power Synthesis (RP, FNN), pp. 650–655.
DAC-1997-SemenovYPPC #independence: Synthesis of Speed-Independent Circuits from STG-Unfolding Segment (ALS, AY, EP, MAP, JC), pp. 16–21.
DAC-1997-YeR #algorithm #graph #network: A Graph-Based Synthesis Algorithm for AND/XOR Networks (YY, KR), pp. 107–112.
EDTC-1997-BeckmannH #constraints #in memory #logic programming #memory management #using: Using constraint logic programming in memory synthesis for general purpose computers (RB, JH), p. 619.
EDTC-1997-BeniniMMPS #logic #network #optimisation: Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (LB, GDM, EM, MP, RS), pp. 514–520.
EDTC-1997-CabodiCLQ #verification: Verification and synthesis of counters based on symbolic techniques (GC, PC, LL, SQ), pp. 176–181.
EDTC-1997-DonnayGSKLB #interface: High-level synthesis of analog sensor interface front-ends (SD, GGEG, WMCS, WK, DL, WvB), pp. 56–60.
EDTC-1997-HerrmannE: Register synthesis for speculative computation (DH, RE), pp. 463–467.
EDTC-1997-HettDB #order #performance: Fast and efficient construction of BDDs by reordering based synthesis (AH, RD, BB), pp. 168–175.
EDTC-1997-IhsD: Test synthesis for DC test of switched-capacitors circuits (HI, CD), p. 616.
EDTC-1997-SchaumontVREB #multi: Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications (PS, SV, LR, ME, IB), pp. 542–546.
EDTC-1997-ThoenSJGM #embedded #graph #multi #realtime #thread: Multi-thread graph: a system model for real-time embedded software synthesis (FT, JVDS, GGdJ, GG, HDM), pp. 476–481.
EDTC-1997-XuK #physics: RTL synthesis with physical and controller information (MX, FJK), pp. 299–303.
HPDC-1997-WilliamsC #distributed #music: Distributed Polyphonic Music Synthesis (JW, MJC), pp. 20–29.
TACAS-1997-Berry #hardware #optimisation #source code #verification: Hardware and Software Synthesis, Optimization, and Verification from Esterel Programs (GB), pp. 1–3.
TACAS-1997-BoigelotG #automation #source code #specification: Automatic Synthesis of Specifications from the Dynamic Observation of Reactive Programs (BB, PG), pp. 321–333.
ICPR-1996-BergerSPW #image #video: Mixing synthesis and video images of outdoor environments: application to the bridges of Paris (MOB, GS, SP, BWD), pp. 90–94.
ICPR-1996-KrotkovKZ #analysis #invariant: Analysis and synthesis of the sounds of impact based on shape-invariant properties of materials (EK, RLK, NBZ), pp. 115–119.
ICPR-1996-LaiNC: Tracking of deformable contours by synthesis and match (KFL, CWN, SC), pp. 657–661.
ICPR-1996-Nishida #analysis #modelling: Analysis and synthesis of deformed patterns based on structural models (HN), pp. 315–319.
ICPR-1996-TatsunoSYIT #analysis #image #using: Analysis and synthesis of six primary facial expressions using range images (YT, SS, NY, HI, HT), pp. 489–493.
SEKE-1996-VerlageDMM #process: A Synthesis of Two Process Support Approaches (MV, BD, FM, JM), pp. 59–68.
LOPSTR-1996-DungKT #proving #reasoning: Synthesis of Proof Procedures for Default Reasoning (PMD, RAK, FT), pp. 313–324.
LOPSTR-1996-MatskinKK #deduction #framework #source code: Partial Deduction in the Framework of Structural Synthesis of Programs (MM, HJK, JK), pp. 239–255.
KBSE-1996-EllmanM #algebra #deduction #difference #equation #network #simulation #source code: Deductive Synthesis of Numerical Simulation Programs from Networks of Algebraic and Ordinary Differential Equations (TE, TM), p. 5.
KBSE-1996-GomesSW: Synthesis of Schedulers for Planned Shutdowns of Power Plants (CPG, DRS, SJW), p. 6.
KBSE-1996-Jr.B #algebra #algorithm: Synthesis of Local Search Algorithms by Algebraic Means (RPGJ, PDB), p. 7.
KBSE-1996-SatoMYW #design #trade-off: Software Synthesis for Trade-off Design (AS, MM, TY, MW), p. 20.
DAC-1996-BerrebiKVTHFJB #control flow #data flow: Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis (EB, PK, SV, SDT, JCH, JF, AAJ, IB), pp. 573–578.
DAC-1996-Camposano #behaviour: Behavioral Synthesis (RC), pp. 33–34.
DAC-1996-CarleyGRS #tool support: Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies (LRC, GGEG, RAR, WMCS), pp. 298–303.
DAC-1996-CortadellaKKLY #encoding #tool support: Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis (JC, MK, AK, LL, AY), pp. 63–66.
DAC-1996-ErcanliP #scheduling: A Register File and Scheduling Model for Application Specific Processor Synthesis (EE, CAP), pp. 35–40.
DAC-1996-HansenS #diagrams #using: Synthesis by Spectral Translation Using Boolean Decision Diagrams (JPH, MS), pp. 248–253.
DAC-1996-HuiskenW #architecture #design #named: FADIC: Architectural Synthesis applied in IC Design (JH, FW), pp. 579–584.
DAC-1996-ImanP #named #optimisation: POSE: Power Optimization and Synthesis Environment (SI, MP), pp. 21–26.
DAC-1996-IyerK #architecture #named #self: Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis (BI, RK), pp. 137–142.
DAC-1996-KudvaGJN #multi #network: Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes (PK, GG, HMJ, SMN), pp. 77–82.
DAC-1996-LeeHCF #design #modelling #using: Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL (MTCL, YCH, BC, MF), pp. 585–590.
DAC-1996-MarculescuMP #generative #probability #sequence: Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation (DM, RM, MP), pp. 696–701.
DAC-1996-Rudell #design #logic #named #tutorial: Tutorial: Design of a Logic Synthesis System (RLR), pp. 191–196.
DAC-1996-TsaiM #logic #multi: Multilevel Logic Synthesis for Arithmetic Functions (CCT, MMS), pp. 242–247.
DAC-1996-WagnerD #overview #perspective #testing: High-Level Synthesis for Testability: A Survey and Perspective (KDW, SD), pp. 131–136.
CAV-1996-BraytonHSSACEKKPQRSSSV #named #verification: VIS: A System for Verification and Synthesis (RKB, GDH, ALSV, FS, AA, STC, SAE, SPK, YK, AP, SQ, RKR, SS, TRS, GS, TV), pp. 428–432.
JICSLP-1996-TanL #logic programming #source code: Type Synthesis for Logic Programs (JT, IPL), pp. 200–214.
ICALP-1995-AndersenKLN #automation #realtime: Automatic Synthesis of Real Time Systems (JHA, KJK, KGL, JN), pp. 535–546.
RTA-1995-ChazarainM #automation #equation #named #recursion #source code: LEMMA: A System for Automated Synthesis of Recursive Programs in Equational Theories (JC, SM), pp. 420–425.
CIKM-1995-NgR #database #statistics: Information Synthesis in Statistical Databases (WKN, CVR), pp. 355–361.
ICML-1995-Lang95a #problem #search-based: Hill Climbing Beats Genetic Search on a Boolean Circuit Synthesis Problem of Koza’s (KJL), pp. 340–343.
SEKE-1995-Rosca #generative #towards: Towards a New Generation of Program Synthesis Approaches (JPR), p. 428.
SEKE-1995-Sliva: A G-Net Module Synthesis Method for Software Applications (VPS), pp. 419–426.
LOPSTR-1995-LauO #deduction #logic programming #object-oriented #source code #towards: Towards an Object-Oriented Methodology for Deductive Synthesis of Logic Programs (KKL, MO), pp. 152–169.
LOPSTR-1995-ParkesW #horn clause #induction #logic programming: Logic Program Synthesis by Induction over Horn Clauses (AJP, GAW), p. 170.
KBSE-1995-BhansaliH #constraints #geometry #knowledge-based: Knowledge-Based Program Synthesis for a Geometric Constraint Satisfaction System (SB, TJH), pp. 11–18.
KBSE-1995-LowryB #domain-specific language #named #performance: META-AMPHION: Synthesis of Efficient Domain-Specific Program Synthesis Systems (MRL, JVB), pp. 2–10.
KBSE-1995-Reuss #deduction #towards #type system: Towards High-Level Deductive Program Synthesis Based on Type Theory (HR), pp. 174–183.
KBSE-1995-SatoTYWH #process #re-engineering: Domain-Oriented Software Process Re-engineering with Software Synthesis Shell SOFTEX/S (AS, MT, TY, MW, MH), pp. 97–104.
DAC-1995-BombanaCCHMZ #case study: Design-Flow and Synthesis for ASICs: A Case Study (MB, PC, SC, RBH, GM, GZ), pp. 292–297.
DAC-1995-ChiodoGJLHSSS #embedded #source code: Synthesis of Software Programs for Embedded Control Applications (MC, PG, AJ, LL, HH, KS, ALSV, ES), pp. 587–592.
DAC-1995-KnappLMM #behaviour #specification #validation: Behavioral Synthesis Methodology for HDL-Based Specification and Validation (DK, TL, DM, RM), pp. 286–291.
DAC-1995-KrauterGWP: Transmission Line Synthesis (BK, RG, JW, LTP), pp. 358–363.
DAC-1995-KruiskampL #algorithm #named #search-based: DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm (WK, DL), pp. 433–438.
DAC-1995-LavagnoMSS #design #power management: Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool (LL, PCM, AS, ALSV), pp. 254–260.
DAC-1995-LinCCMC #logic: Logic Synthesis for Engineering Change (CCL, KCC, SCC, MMS, KTC), pp. 647–652.
DAC-1995-ReddyKP #framework #novel #verification: Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment (SMR, WK, DKP), pp. 414–419.
DAC-1995-RekhiTL #automation #layout: Automatic Layout Synthesis of Leaf Cells (SR, JDT, DHL), pp. 267–272.
DAC-1995-StanionS: A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis (TS, CS), pp. 60–64.
LCT-RTS-1995-ThoenCGM #information management #realtime: Software Synthesis for Real-Time Information Processing Systems (FT, MC, GG, HDM), pp. 60–69.
PPoPP-1995-HwangLJ #array #fortran #source code: An Array Operation Synthesis Scheme to Optimize Fortran 90 Programs (GHH, JKL, RDCJ), pp. 112–122.
TAPSOFT-1995-BadouelBD #algorithm #bound #polynomial: Polynomial Algorithms for the Synthesis of Bounded Nets (EB, LB, PD), pp. 364–378.
CAV-1995-Vardi #approach: An Automata-Theoretic Approach to Fair Realizability and Synthesis (MYV), pp. 267–278.
ICLP-1995-TanL #logic programming #source code: Type Synthesis for Logic Programs (JT, IPL), p. 823.
ILPS-1995-LauO #approach #constraints #deduction #formal method #logic programming #source code: A Formal Approach to Deductive Synthesis of Constraint Logic Programs (KKL, MO), pp. 543–557.
SEKE-1994-LuqiG #analysis #certification: Suggestions for progress in software analysis, synthesis and certification (L, JAG), pp. 501–507.
LOPSTR-1994-FlenerP #induction #on the #reasoning #using: On the Use of Inductive Reasoning in Program Synthesis: Prejudice and Prospects (PF, LP), pp. 69–87.
LOPSTR-1994-LauO #deduction #framework #logic programming #on the #source code #specification: On Specification Frameworks and Deductive Synthesis of Logic Programs (KKL, MO), pp. 104–121.
PLILP-1994-Bsaies #implementation: Implementing the Synthesis of Properties in Unfold/Fold Transformations (KB), pp. 459–460.
POPL-1994-Thatte #adaptation #automation #interface #reuse: Automated Synthesis of Interface Adapters for Reusable Classes (ST), pp. 174–187.
DAC-1994-AloqeelyC #algorithm: Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms (MA, CYRC), pp. 155–160.
DAC-1994-ArnsteinT #abstraction #behaviour #tool support: The Attributed-Behavior Abstraction and Synthesis Tools (LFA, DET), pp. 557–561.
DAC-1994-ChangCWM #layout #logic: Layout Driven Logic Synthesis for FPGAs (SCC, KTC, NSW, MMS), pp. 308–313.
DAC-1994-FannRJ #scheduling: Global Scheduling for High-Level Synthesis Applications (YF, MR, RJ), pp. 542–546.
DAC-1994-HarrisO #architecture #concurrent #design: Microarchitectural Synthesis of VLSI Designs with High Test Concurrency (IGH, AO), pp. 206–211.
DAC-1994-HuangD #pipes and filters #set: Synthesis of Instruction Sets for Pipelined Microprocessors (IJH, AMD), pp. 5–11.
DAC-1994-JunH #automation #pipes and filters: Automatic Synthesis of Pipeline Structures with Variable Data Initiation Intervals (HSJ, SYH), pp. 537–541.
DAC-1994-JyuM #design #logic #modelling #statistics: Statistical Delay Modeling in Logic Design and Synthesis (HFJ, SM), pp. 126–130.
DAC-1994-KarriO #architecture #detection #fault #self: Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis (RK, AO), pp. 552–556.
DAC-1994-KolsonND #memory management: Minimization of Memory Traffic in High-Level Synthesis (DJK, AN, NDD), pp. 149–154.
DAC-1994-OchottaRC #agile #named #tool support: ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits (ESO, RAR, LRC), pp. 24–30.
DAC-1994-PrasadAB #design #incremental: A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes (SCP, PA, PWB), pp. 441–446.
DAC-1994-PuriG #approach #clustering #composition: A Modular Partitioning Approach for Asynchronous Circuit Synthesis (RP, JG), pp. 63–69.
DAC-1994-SarabiSCP #2d #approach #array #design #logic #physics: A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays (AS, NS, MCJ, MAP), pp. 321–326.
DAC-1994-VerbauwhedeSR #estimation #memory management: Memory Estimation for High Level Synthesis (IV, CJS, JMR), pp. 143–148.
DAC-1994-WalkupB #interface #verification: Interface Timing Verification with Application to Synthesis (EAW, GB), pp. 106–112.
EDAC-1994-BhatiaJ #behaviour #named #overview #testing: Genesis: A Behavioral Synthesis System for Hierarchical Testability (SB, NKJ), pp. 272–276.
EDAC-1994-BurgunDGPS #complexity #logic #multi: Multilevel Logic Synthesis of Very High Complexity Circuits (LB, ND, AG, EP, CS), p. 669.
EDAC-1994-DhodhiAC #multi: Synthesis of Application-Specific Multiprocessor Systems (MKD, IA, CYRC), p. 671.
EDAC-1994-FlottesHR #automation #specification: Automatic Synthesis of BISTed Data Paths From High Level Specification (MLF, DH, BR), pp. 591–598.
EDAC-1994-GhatrajuAM #fixpoint: High-Level Synthesis of Digital Circuits by Finding Fixpoints (LG, MHAEB, CM), pp. 94–98.
EDAC-1994-HellebrandW #self: Synthesis of Self-Testable Controllers (SH, HJW), pp. 580–585.
EDAC-1994-KeM: Synthesis of Delay-Verifiable Two-Level Circuits (WK, PRM), pp. 297–301.
EDAC-1994-KimCL #refinement #testing: A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability (TK, KSC, CLL), pp. 586–590.
EDAC-1994-KorfS #interface #specification: Interface Controller Synthesis from Requirement Specifications (FK, RS), pp. 385–394.
EDAC-1994-LinKL #approach: Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach (KJL, JWK, CSL), pp. 178–183.
EDAC-1994-NarayanG #interface: Synthesis of System-Level Bus Interfaces (SN, DG), pp. 395–399.
EDAC-1994-NguyenTDTV #cpu #logic #verification: Logic Synthesis and Verification of the CPU and Caches of a Mainframe System (HNN, JPT, LD, MT, PV), pp. 60–64.
EDAC-1994-RamachandranK: Incorporating the Controller Effects During Register Transfer Level Synthesis (CR, FJK), pp. 308–313.
EDAC-1994-RouzeyreDS #component #scheduling: Component Selection, Scheduling and Control Schemes for High Level Synthesis (BR, DD, GS), pp. 482–489.
EDAC-1994-Wang #testing: Synthesis of Sequential Machines with Reduced Testing Cost (SJW), pp. 302–306.
EDAC-1994-WuTWL #behaviour: A Synthesis Method for Mixed Synchronous / Asynchronous Behavior (TYW, TCT, ACHW, YLL), pp. 277–281.
CADE-1994-Hutter #induction #order #proving: Synthesis of Induction Orderings for Existence Proofs (DH), pp. 29–41.
CAV-1994-AnuchitanukulM: Realizability and Synthesis of Reactive Modules (AA, ZM), pp. 156–168.
ICLP-1994-LauOT #deduction #logic programming #problem #source code: The Halting Problem for Deductive Synthesis of Logic Programs (KKL, MO, SÅT), pp. 665–683.
ICLP-1994-LauW #logic programming #source code #specification #tutorial: A Tutorial on Synthesis of Logic Programs from Specifications (KKL, GAW), pp. 11–14.
FME-1993-KalinichenkoNZ #composition #development #query #semantics: Application of Composition Development Method for definition of SYNTHESIS information resource query language semantics (LAK, NSN, VZ), pp. 428–441.
HCI-SHI-1993-DohiI #human-computer #interactive #realtime #towards: Realtime Synthesis of a Realistic Anthropomorphous Agent Toward Advanced Human-Computer Interaction (HD, MI), pp. 152–157.
HCI-SHI-1993-MorishimaH #animation #communication #human-computer: Facial Animation Synthesis for Human-Machine Communication System (SM, HH), pp. 1085–1090.
HCI-SHI-1993-PayneWC #comprehension #hypermedia: Cognitive Processing and Hypermedia Comprehension: A Preliminary Synthesis (DGP, MJW, MSC), pp. 633–638.
ICML-1993-Ellman #abstraction #approximate #clustering #constraints: Synthesis of Abstraction Hierarchies for Constraint Satisfaction by Clustering Approximately Equivalent Objects (TE), pp. 104–111.
LOPSTR-1993-BergadanoG #induction #logic programming #source code: Inductive Synthesis of Logic Programs and Inductive Logic Programming (FB, DG), pp. 45–56.
LOPSTR-1993-LauO #deduction #logic programming #source code #specification: A Formal View of Specification, Deductive Synthesis and Transformation of Logic Programs (KKL, MO), pp. 10–31.
LOPSTR-1993-LombartWD #proving: Guiding Synthesis Proofs (VL, GAW, YD), pp. 67–81.
LOPSTR-1993-ProiettiP #proving #source code: Synthesis of Programs from Unfold/Fold Proofs (MP, AP), pp. 141–158.
LOPSTR-1993-Smith #algorithm #constraints #towards: Towards the Synthesis of Constraint Propagation Algorithms (DRS), pp. 1–9.
WSA-1993-BoyePM #functional #logic programming #source code: Synthesis of Directionality Information for Functional Logic Programs (JB, JP, JM), pp. 165–177.
KBSE-1993-JulligS #diagrams: Diagrams for Software Synthesis (RJ, YS), p. 6.
KBSE-1993-Smith #algorithm #named: KIDS: An Algorithm Synthesis System (DRS), p. 2.
KBSE-1993-SmithS #design #towards: Towards Supporting Design Phase Synthesis (TES, DES), p. 7.
DAC-1993-CloutierT #pipes and filters #set: Synthesis of Pipelined Instruction Set Processors (RJC, DET), pp. 583–588.
DAC-1993-GhoshNSP #architecture #multi: Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving (DG, SKN, PS, KP), pp. 303–307.
DAC-1993-KarriO #architecture: High-Level Synthesis of Fault-Secure Microarchitectures (RK, AO), pp. 429–433.
DAC-1993-KimL #multi: Utilization of Multiport Memories in Data Path Synthesis (TK, CLL), pp. 298–302.
DAC-1993-LaiPV #composition #logic: BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis (YTL, MP, SBKV), pp. 642–647.
DAC-1993-LeeJW #behaviour: Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments (TCL, NKJ, WW), pp. 292–297.
DAC-1993-MurgaiBS #array #programmable: Sequential Synthesis for Table Look Up Programmable Gate Arrays (RM, RKB, ALSV), pp. 224–229.
DAC-1993-PapachristouHN #approach: An Approach for Redesigning in Data Path Synthesis (CAP, HH, MN), pp. 419–423.
DAC-1993-SeawrightB #performance: High-Level Symbolic Construction Technique for High Performance Sequential Synthesis (AS, FB), pp. 424–428.
DAC-1993-SharmaJ93a #architecture #performance: Estimating Architectural Resources and Performance for High-Level Synthesis Applications (AS, RJ), pp. 355–360.
DAC-1993-VemuriMSKRV #case study #experience #functional #validation: Experiences in Functional Validation of a High Level Synthesis System (RV, PM, PS, NK, JR, RV), pp. 194–201.
DAC-1993-WangDNS #architecture #multi #scalability #using: High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules (HW, NDD, AN, KYS), pp. 336–342.
PDP-1993-SharpC #algorithm #fourier #functional #performance #program transformation: Synthesis of the fast Fourier transform algorithm by functional language program transformation (DWNS, MC), pp. 136–143.
CAV-1993-Brayton #design #logic #verification: Logic Synthesis and Design Verification (RKB), pp. 1–2.
ICLP-1993-KraanBB #logic programming #reasoning: Middle-Out Reasoning for Logic Program Synthesis (IK, DAB, AB), pp. 441–455.
ICLP-1993-LauO #deduction #logic programming #source code: An Incompleteness Result for Deductive Synthesis of Logic Programs (KKL, MO), pp. 456–477.
CAiSE-1992-ShawG #information management #re-engineering: The Synthesis of Knowledge Engineering and Software Engineering (MLGS, BRG), pp. 208–220.
LOPSTR-1992-KraanBB #logic programming #proving #theorem proving: Logic Program Synthesis via Proof Planning (IK, DAB, AB), pp. 1–14.
LOPSTR-1992-Loria-Saenz #source code: Synthesis of Narrowing Programs (CLS), pp. 30–45.
LOPSTR-1992-NardiR #deduction #query #source code: Deductive Synthesis of Programs for Query Answering (DN, RR), pp. 15–29.
PEPM-1992-Bsaies #framework #logic programming #program transformation: A Framework for Mechanizing Logic Program Transformation: The Synthesis of Eureka-Properties (KB), pp. 108–115.
KBSE-1992-GravesLM #empirical: A Code Synthesis Experiment (HG, JL, TM), p. 4.
KBSE-1992-SetliffS #constraints #knowledge-based: Knowledge-Based Constraint-Driven Software Synthesis (DES, TES), p. 5.
KBSE-1992-YamanouchiSTTTW: Software Synthesis Shell SOFTEX/S (TY, AS, MT, HT, JT, MW), p. 6.
DAC-1992-BergamaschiLK #behaviour #optimisation #using: Control Optimization in High-Level Synthesis Using Behavioral Don’t Cares (RAB, DAL, AK), pp. 657–661.
DAC-1992-ChakradharKA #fault tolerance #finite #state machine: Finite State Machine Synthesis with Fault Tolerant Test Function (STC, SK, VDA), pp. 562–567.
DAC-1992-DuttaRV #distributed: Distributed Design-Space Exploration for High-Level Synthesis Systems (RD, JR, RV), pp. 644–650.
DAC-1992-GuptaCM #component #hardware #simulation: Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components (RKG, CJNCJ, GDM), pp. 225–230.
DAC-1992-HsuS #algebra #logic #multi: Coalgebraic Division for Multilevel Logic Synthesis (WJH, WZS), pp. 438–442.
DAC-1992-HuangD #compilation #pipes and filters #set: High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers (IJH, AMD), pp. 135–140.
DAC-1992-HungP #constraints #design #multi: High-Level Synthesis with Pin Constraints for Multiple-Chip Designs (YHH, ACP), pp. 231–234.
DAC-1992-KarriO #fault tolerance: Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs (RK, AO), pp. 662–665.
DAC-1992-LiaoC #layout: Routing Considerations in Symbolic Layout Synthesis (YL, SC), pp. 682–686.
DAC-1992-MaulikCR #approach #programming: A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis (PCM, LRC, RAR), pp. 698–703.
DAC-1992-MurgaiBS #algorithm #multi: An Improved Synthesis Algorithm for Multiplexor-Based PGA’s (RM, RKB, ALSV), pp. 380–386.
DAC-1992-NouraniP #automation #scheduling: Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems (MN, CAP), pp. 99–105.
DAC-1992-PrabhuP: Superpipelined Control and Data Path Synthesis (UP, BMP), pp. 638–643.
DAC-1992-RimJ #branch #representation: Representing Conditional Branches for High-Level Synthesis Applications (MR, RJ), pp. 106–111.
DAC-1992-RimJL: Optimal Allocation and Binding in High-Level Synthesis (MR, RJ, RDL), pp. 120–123.
DAC-1992-RundensteinerG #functional #optimisation #using: Functional Synthesis Using Area and Delay Optimization (EAR, DG), pp. 291–296.
DAC-1992-SeawrightB #specification: Synthesis from Production-Based Specifications (AS, FB), pp. 194–199.
DAC-1992-StollD #constraints: High-Level Synthesis from VHDL with Exact Timing Constraints (AS, PD), pp. 188–193.
DAC-1992-WolfTHMW #behaviour: The Princeton University Behavioral Synthesis System (WW, AT, CYH, RM, EW), pp. 182–187.
CADE-1992-HeskethBS #reasoning #recursion #source code #using: Using Middle-Out Reasoning to Control the Synthesis of Tail-Recursive Programs (JH, AB, AS), pp. 310–324.
CAV-1992-AagaardL #case study #logic #verification: Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification (MA, ML), pp. 69–81.
JICSLP-1992-HaasJ #definite clause grammar #interactive: Interactive Synthesis of Definite-Clause Grammars (JH, BJ), pp. 541–555.
JICSLP-1992-Wiggins #development #logic programming #proving #source code: Synthesis and Transformation of Logic Programs in the Whelk Proof Development System (GAW), pp. 351–365.
KDD-1991-ChiuWC: Information Discovery through Hierarchical Maximum Entropy Discretization and Synthesis (DKYC, AKCW, BC), pp. 125–140.
LOPSTR-1991-FlenerD #logic programming #towards: Towards Stepwise, Schema-guided Synthesis of Logic Programms (PF, YD), pp. 46–64.
LOPSTR-1991-JantkeG #induction: Inductive Synthesis of Rewrite Rules as Program Synthesis (KPJ, UG), pp. 65–68.
LOPSTR-1991-MiglioliMO #specification: Program Specification and Synthesis in Constructive Formal Systems (PM, UM, MO), pp. 13–26.
LOPSTR-1991-Popelinsky #prolog #source code #towards: Towards Synthesis of Nearly Pure Prolog Programs (LP), pp. 94–96.
LOPSTR-1991-WigginsBKH #induction #logic programming #proving #source code: Synthesis and Transfomation of Logic Programs from Constructive, Inductive Proof (GAW, AB, IK, JH), pp. 27–45.
WSA-1991-Breuer #analysis #learning: An Analysis/Synthesis Language with Learning Strategies (PTB), pp. 202–209.
DAC-1991-AmonB91a #case study: Sizing Synchronization Queues: A Case Study in Higher Level Synthesis (TA, GB), pp. 690–693.
DAC-1991-BenkoskiS #layout #verification: The Role of Timing Verification in Layout Synthesis (JB, AJS), pp. 612–619.
DAC-1991-BergamaschiCP #analysis #using: Data-Path Synthesis Using Path Analysis (RAB, RC, MP), pp. 591–596.
DAC-1991-ChengDK #design #generative #robust #standard #testing: Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology (KTC, SD, KK), pp. 80–86.
DAC-1991-ChiuP #design #testing: A Design for Testability Scheme with Applications to Data Path Synthesis (SC, CAP), pp. 271–277.
DAC-1991-DuttK #library: Bridging High-Level Synthesis to RTL Technology Libraries (NDD, JRK), pp. 526–529.
DAC-1991-EschermannW #approach #finite #self #state machine: A Unified Approach for the Synthesis of Self-Testable Finite State Machines (BE, HJW), pp. 372–377.
DAC-1991-Fuhrman #industrial #tool support: Industrial Extensions to University High Level Synthesis Tools: Making It Work in the Real World (TEF), pp. 520–525.
DAC-1991-GebotysE #architecture #scheduling: Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis (CHG, MIE), pp. 2–7.
DAC-1991-Hafer #constraints #hardware: Constraint improvements for MILP-based hardware synthesis (LJH), pp. 14–19.
DAC-1991-JainMSW #empirical #evaluation #heuristic #scheduling: Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics (RJ, AM, AS, HW), pp. 686–689.
DAC-1991-Kozminski #benchmark #evolution #layout #metric: Benchmarks for Layout Synthesis — Evolution and Current Status (KK), pp. 265–270.
DAC-1991-Krasniewski #logic #performance #pseudo #testing: Logic Synthesis for Efficient Pseudoexhaustive Testability (AK), pp. 66–72.
DAC-1991-LaddB #finite #multi #state machine: Synthesis of Multiple-Input Change Asynchronous Finite state Machines (ML, WPB), pp. 309–314.
DAC-1991-LavagnoKS #algorithm: Algorithms for Synthesis of Hazard-Free Asynchronous Circuits (LL, KK, ALSV), pp. 302–308.
DAC-1991-LinL #automation: Automatic Synthesis of Asynchronous Circuits (KJL, CSL), pp. 296–301.
DAC-1991-LyM #bottom-up #fuzzy: Bottom Up Synthesis Based on Fuzzy Schedules (TAL, JTM), pp. 674–679.
DAC-1991-MorganG #logic: An ECL Logic Synthesis System (VM, DG), pp. 106–111.
DAC-1991-NicolauP #incremental #reduction: Incremental Tree Height Reduction for High Level Synthesis (AN, RP), pp. 770–774.
DAC-1991-NoteGCM #architecture #named #throughput: Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications (SN, WG, FC, HDM), pp. 597–602.
DAC-1991-PangrleBLS: Relevant Issues in High-Level Connectivity Synthesis (BMP, FB, DAL, AS), pp. 607–610.
DAC-1991-PapachristouCH #design #self: A Data Path Synthesis Method for Self-Testable Designs (CAP, SC, HH), pp. 378–384.
DAC-1991-PrakashP #architecture #multi: Synthesis of Application-Specific Multiprocessor Architectures (SP, ACP), pp. 8–13.
DAC-1991-RaghavendraL #automation #self: Automated Micro-Roll-back Self-Recovery Synthesis (VR, CL), pp. 385–390.
DAC-1991-WengP #3d #scheduling: 3D Scheduling: High-Level Synthesis with Floorplanning (JPW, ACP), pp. 668–673.
CAV-1991-NicollinS #algebra #overview #process: An Overview and Synthesis on Timed Process Algebras (XN, JS), pp. 376–398.
CSL-1991-Voronkov #on the: On Completeness of Program Synthesis Systems (AV), pp. 411–418.
ISLP-1991-LauP #product line #recursion #sorting: Synthesis of a Family of Recursive Sorting Procedures (KKL, SDP), pp. 641–658.
OOPSLA-ECOOP-1990-Dony #exception #object-oriented #programming #towards: Exception Handling and Object-Oriented Programming: Towards a Synthesis (CD), pp. 322–330.
DAC-1990-AbouzeidSSP #multi: Multilevel Synthesis Minimizing the Routing Factor (PA, KS, GS, FP), pp. 365–368.
DAC-1990-AgrawalC #specification: Test Function Specification in Synthesis (VDA, KTC), pp. 235–240.
DAC-1990-BreternitzS #architecture: Architecture Synthesis of High-Performance Application-Specific Processors (MBJ, JPS), pp. 542–548.
DAC-1990-ChenG #behaviour #component #database: An Intelligent Component Database for Behavioral Synthesis (GDC, DG), pp. 150–155.
DAC-1990-CompasanoB #algorithm #scheduling #using: Synthesis Using Path-Based scheduling: algorithms and Exercises (RC, RAB), pp. 450–455.
DAC-1990-DevadasK #logic #optimisation #robust: Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits (SD, KK), pp. 221–227.
DAC-1990-Domic #layout: Layout Synthesis of MOS Digital Cells (AD), pp. 241–245.
DAC-1990-DuttHG #behaviour #representation: An Intermediate Representation for Behavioral Synthesis (NDD, TH, DG), pp. 14–19.
DAC-1990-GrantD #algorithm #memory management: Memory, Control and Communications Synthesis for Scheduled Algorithms (DMG, PBD), pp. 162–167.
DAC-1990-HillP #benchmark #metric: Benchmarks for Cell Synthesis (DDH, BP), pp. 317–320.
DAC-1990-HillS: Global Routing Considerations in a Cell Synthesis System (DDH, DS), pp. 312–316.
DAC-1990-LyEG: A Generalized Interconnect Model for Data Path Synthesis (TAL, WLE, EFG), pp. 168–173.
DAC-1990-McNallC #architecture #automation #pipes and filters: Automatic Operator Configuration in the Synthesis of Pipelined Architectures (KNM, AEC), pp. 174–179.
DAC-1990-MurgaiNSBS #array #logic #programmable: Logic Synthesis for Programmable Gate Arrays (RM, YN, NVS, RKB, ALSV), pp. 620–625.
DAC-1990-PotasmanLNG: Percolation Based Synthesis (RP, JL, AN, DG), pp. 444–449.
DAC-1990-SarmaDNH #industrial: High-Level Synthesis: Technology Transfer to Industry (RCS, MDD, NCN, GH), pp. 549–554.
DAC-1990-ScheichenzuberGLM #behaviour #data flow #hardware: Global Hardware Synthesis from Behavioral Dataflow Descriptions (JS, WG, UL, SM), pp. 456–461.
DAC-1990-WhitcombN #data type: Abstract Data Types and High-Level Synthesis (GSW, ARN), pp. 680–685.
DAC-1990-Wolf #automaton #behaviour #network: The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines (WW), pp. 692–697.
DAC-1990-Woo: A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System (NSW), pp. 505–510.
ESOP-1990-ProiettiP #logic programming #source code: Synthesis of Eureka Predicates for Developing Logic Programs (MP, AP), pp. 306–325.
CLP-1990-LauP90 #first-order #logic #recursion #specification #top-down: Top-down Synthesis of Recursive Logic Procedures from First-order Logic Specifications (KKL, SDP), pp. 667–684.
ICALP-1989-PnueliR #on the: On the Synthesis of an Asynchronous Reactive Module (AP, RR), pp. 652–671.
RTA-1989-Reddy: Rewriting Techniques for Program Synthesis (USR), pp. 388–403.
POPL-1989-AttieE #concurrent #process: Synthesis of Concurrent Systems with Many Similar Sequential Processes (PCA, EAE), pp. 191–201.
POPL-1989-PnueliR #on the: On the Synthesis of a Reactive Module (AP, RR), pp. 179–190.
DAC-1989-BalakrishnanM #approach #design #scheduling: Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration (MB, PM), pp. 68–74.
DAC-1989-BusetE #architecture #interface #named #visual notation: ACE: A Hierarchical Graphical Interface for Architectual Synthesis (OAB, MIE), pp. 537–542.
DAC-1989-Cyre #towards: Toward Synthesis from English Descriptions (WRC), pp. 742–745.
DAC-1989-Devadas #logic #multi: Approaches to Multi-level Sequential Logic Synthesis (SD), pp. 270–276.
DAC-1989-DragomireckyGJDSd #user interface #visual notation: High-Level Graphical User Interface Management in the FACE Synthesis Environment (MD, EPG, JRJ, DAD, WDS, MAd), pp. 549–554.
DAC-1989-DuttG #behaviour #design: Designer Controlled Behavioral Synthesis (NDD, DG), pp. 754–757.
DAC-1989-GoreR #array #automation #equation #logic #programmable #using: Automatic Synthesis of Boolean Equations Using Programmable Array Logic (RG, KR), pp. 283–289.
DAC-1989-HwangOI #communication #complexity #logic #multi #using: Multi-Level Logic Synthesis Using Communication Complexity (TH, RMO, MJI), pp. 215–220.
DAC-1989-JainKMP #experience: Experience with ADAM Synthesis System (RJ, KK, MJM, ACP), pp. 56–61.
DAC-1989-Keutzer #architecture #design #generative #logic: Three Competing Design Methodologies for ASIC’s: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation (KK), pp. 308–313.
DAC-1989-KumarKKG #automation #behaviour: Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions (AK, SK, PK, SG), pp. 147–154.
DAC-1989-LinDY #2d #layout #matrix: Gate Matrix Layout Synthesis with Two-Dimensional Folding (IL, DHCD, SHCY), pp. 37–42.
DAC-1989-LisG #modelling #using: VHDL Synthesis Using Structured Modeling (JL, DG), pp. 606–609.
DAC-1989-OngLL #automation #named: GENAC: An Automatic Cell Synthesis Tool (CLO, JTL, CYL), pp. 239–244.
DAC-1989-PaulinK #algorithm #scheduling: Scheduling and Binding Algorithms for High-Level Synthesis (PGP, JPK), pp. 1–6.
DAC-1989-SetliffR #automation #named #physics: ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software (DES, RAR), pp. 543–548.
DAC-1989-TrickD #behaviour #layout #named #tool support: LASSIE: Structure to Layout for Behavioral Synthesis Tools (MTT, SWD), pp. 104–109.
DAC-1989-WeinerS #analysis #logic: Timing Analysis in a Logic Synthesis Environment (NW, ALSV), pp. 655–661.
SOSP-1989-MassalinP #kernel #thread: Threads and Input/Output in the Synthesis Kernel (HM, CP), pp. 191–201.
OOPSLA-1988-ScalettiJ #composition #interactive #music #object-oriented: An Interactive Environment for Object-Oriented Music Composition and Sound Synthesis (CAS, REJ), pp. 222–233.
DAC-1988-BergstraesserGHW #architecture #named #tool support: SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture (TB, JG, KH, SW), pp. 654–657.
DAC-1988-BorrielloD: High-Level Synthesis: Current Status and Future Directions (GB, ED), pp. 477–482.
DAC-1988-GebotysE #design #testing: VLSI Design Synthesis with Testability (CHG, MIE), pp. 16–21.
DAC-1988-JainPP #pipes and filters: Module Selection for Pipelined Synthesis (RJ, ACP, NP), pp. 542–547.
DAC-1988-McFarlandPC #tutorial: Tutorial on High-Level Synthesis (MCM, ACP, RC), pp. 330–336.
DAC-1988-MicheliK #named: HERCULES — a System for High-Level Synthesis (GDM, DCK), pp. 483–488.
DAC-1988-Stroud #approach #automation #logic: An Automated BIST Approach for General Sequential Logic Synthesis (CES), pp. 3–8.
DAC-1988-TsengWRTB #behaviour #named: Bridge: A Versatile Behavioral Synthesis System (CJT, RSW, SGR, MMT, AKB), pp. 415–420.
DAC-1988-WeiRJ #behaviour #named: BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping (RSW, SGR, JYJ), pp. 409–414.
CADE-1988-Jacquet #type system: Program Synthesis by Completion with Dependent Subtypes (PJ), pp. 550–562.
ESEC-1987-EnselmeBV #automation #data type: Automatic Program Synthesis from Data Structures (DE, GB, FYV), pp. 339–347.
ICSE-1987-Ladkin #concurrent #dependence #process #specification: Specification of Time Dependencies and Synthesis of Concurrent Processes (PBL), pp. 106–115.
DAC-1987-CesearIT #named: PAMS: An Expert System for Parameterized Module Synthesis (TC, EI, CT), pp. 666–671.
DAC-1987-HarjaniRC #framework #knowledge-based #prototype: A Prototype Framework for Knowledge-Based Analog Circuit Synthesis (RH, RAR, LRC), pp. 42–49.
DAC-1987-PaulinK #automation #scheduling: Force-Directed Scheduling in Automatic Data Path Synthesis (PGP, JPK), pp. 195–202.
DAC-1987-Trevillyan #logic #overview: An Overview of Logic Synthesis Systems (LT), pp. 166–172.
DAC-1987-WongL #array #optimisation: Array Optimization for VLSI Synthesis (DFW, CLL), pp. 537–543.
ICLP-1987-Kluzniak87 #prolog: Type Synthesis for Ground Prolog (FK), pp. 788–816.
ICALP-1986-Lisper #concurrent #equivalence: Synthesis and Equivalence of Concurrent Systems (BL), pp. 226–235.
OOPSLA-1986-BhaskarPB #object-oriented: Virtual Instruments: Object-Oriented Program Synthesis (KSB, JKP, JLB), pp. 303–314.
DAC-1986-BruckKKR #algorithm #composition #concurrent: Synthesis of concurrent modular controllers from algorithmic descriptions (RB, BK, TK, FJR), pp. 285–292.
DAC-1986-DevadasN #array #named: GENIE: a generalized array optimizer for VLSI synthesis (SD, ARN), pp. 631–637.
DAC-1986-Geus #automation #benchmark #design #logic #metric #optimisation: Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference (AJdG), p. 78.
DAC-1986-JoynerTBNG #adaptation #logic: Technology adaption in logic synthesis (WHJJ, LT, DB, TAN, SCG), pp. 94–100.
DAC-1986-KrekelbergSSL #automation #compilation #layout: Automated layout synthesis in the YASC silicon compiler (DEK, ES, GES, LSL), pp. 447–453.
DAC-1986-Larsen #analysis #clustering #data type: Rules-based object clustering: a data structure for symbolic VLSI synthesis and analysis (RPL), pp. 768–777.
DAC-1986-Marwedel: A new synthesis for the MIMOLA software system (PM), pp. 271–277.
DAC-1986-McFarland #behaviour #bottom-up #design #hardware #using: Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions (MCM), pp. 474–480.
DAC-1986-ParkerPM #named: MAHA: a program for datapath synthesis (ACP, JTP, MJM), pp. 461–466.
DAC-1986-ParkP #named #pipes and filters: Sehwa: a program for synthesis of pipelines (NP, ACP), pp. 454–460.
DAC-1986-PaulinKG #approach #automation #multi #named: HAL: a multi-paradigm approach to automatic data path synthesis (PGP, JPK, EFG), pp. 263–270.
DAC-1986-Peng #design: Synthesis of VLSI systems with the CAMAD design aid (ZP), pp. 278–284.
DAC-1986-SaitoSYK #array #logic #rule-based: A rule-based logic circuit synthesis system for CMOS gate arrays (TS, HS, MY, NK), pp. 594–600.
DAC-1986-Sasao #generative #multi #named #using: MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators (TS), pp. 86–93.
DAC-1986-ShinshaKSKI #identification #incremental #logic: Incremental logic synthesis through gate logic structure identification (TS, TK, YS, JK, KI), pp. 391–397.
CADE-1986-Traugott86a #deduction #sorting #source code: Deductive Synthesis of Sorting Programs (JT), pp. 641–660.
LICS-1986-JonssonMW #data flow #deduction #network #towards: Towards Deductive Synthesis of Dataflow Networks (BJ, ZM, RJW), pp. 26–37.
FPCA-1985-PatelSE85 #algorithm #analysis #hardware #multi #named #specification: vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms (DP, MDFS, MDE), pp. 238–255.
DAC-1985-BlackburnT #behaviour #representation: Linking the behavioral and structural dominis of representation in a synthesis system (RLB, DET), pp. 374–380.
DAC-1985-Camposano #design: Synthesis techniques for digital systems design (RC), pp. 475–481.
DAC-1985-ParkP: Synthesis of optimal clocking schemes (NP, ACP), pp. 489–495.
DAC-1985-RajanT: Synthesis by delayed binding of decisions (JVR, DET), pp. 367–373.
DAC-1985-WalkerT #design #representation: A model of design representation and synthesis (RAW, DET), pp. 453–459.
CSE-1985-Gribomont #invariant #parallel #source code: Synthesis of Parallel Programs Invariants (EPG), pp. 325–338.
LFP-1984-CointeR #composition #music #named: Formes: an Object and Time Oriented System for Music Composition and Synthesis (PC, XR), pp. 85–95.
DAC-1984-DussaultLT #design: A high level synthesis tool for MOS chip design (JPD, CCL, MMT), pp. 308–314.
DAC-1984-EvansBD #algorithm #design #named: ADL: An algorithmic design language for integrated circuit synthesis (WHE, JCB, NHD), pp. 66–72.
DAC-1984-ParkerKM #design #verification: A general methodology for synthesis and verification of register-transfer designs (ACP, FJK, MJM), pp. 329–335.
DAC-1984-RajPG: Microprocessor synthesis (VKR, BMP, DDG), pp. 676–678.
DAC-1984-ShinshaKHAI #algorithm #logic #named: Polaris: Polarity propagation algorithm for combinational logic synthesis (TS, TK, MH, KA, KI), pp. 322–328.
DAC-1983-HitchcockT #automation: A method of automatic data path synthesis (CYHI, DET), pp. 484–489.
DAC-1983-StebniskyMWPF #automation #named: APSS: An automatic PLA synthesis system (MWS, MJM, JCW, RP, AF), pp. 430–435.
DAC-1983-TsengS #automation #named: Facet: A procedure for the automated synthesis of digital systems (CJT, DPS), pp. 490–496.
DAC-1983-WimerS #optimisation: HOPLA-PLA optimization and synthesis (SW, NS), pp. 790–794.
POPL-1982-Wolper #communication #logic #process #specification #using: Specification and Synthesis of Communicating Processes using an Extended Temporal Logic (PW), pp. 20–33.
DAC-1982-KawatoUHS #interactive #logic: An interactive logic synthesis system based upon AI techniques (NK, TU, SH, TS), pp. 858–864.
DAC-1982-LuhukayK #layout: A layout synthesis system for NMOS gate-cells (JFPL, WJK), pp. 307–314.
DAC-1982-MaisselO #approach #design #documentation #hardware #interactive #simulation: Interactive design language: A unified approach to hardware simulation, synthesis and documentation (LIM, DLO), pp. 193–201.
DAC-1982-ShivaC #composition #simulation #using: Modular description/simulation/synthesis using DDL (SGS, JAC), pp. 321–329.
CADE-1982-Smith: Derived Preconditions and Their Use in Program Synthesis (DRS), pp. 172–193.
DAC-1981-KangC #automation: Automatic PLA synthesis from a DDL-P description (SK, WMvC), pp. 391–397.
DAC-1981-LeiveT #logic: A technology relative Logic Synthesis and Module Selection system (GWL, DET), pp. 479–485.
DAC-1981-TsengS #modelling: The modeling and synthesis of bus systems (CJT, DPS), pp. 471–478.
DAC-1980-DarringerJ #logic: A new look at logic synthesis (JAD, WHJJ), pp. 543–549.
DAC-1980-Shiva #logic: Combinational logic synthesis from an HDL description (SGS), pp. 550–555.
CADE-1980-GuihoG: Program Synthesis from Incomplete Specifiactions (GDG, CG), pp. 53–62.
POPL-1979-Clarke #concurrent #invariant #source code: Synthesis of Resource Invariants for Concurrent Programs (EMC), pp. 211–221.
DAC-1979-Barbacci #evaluation #set #simulation #specification: Instruction set processor specifications for simulation, evaluation, and synthesis (MB), pp. 64–72.
ICSE-1978-MannaW #source code: The Synthesis of Structure Changing Programs (ZM, RJW), pp. 175–187.
DAC-1978-AgerwalaC #concurrent: A synthesis rule for concurrent systems (TA, YCCA), pp. 305–311.
VLDB-1977-Vetter #database #design: Data Base Design by Applied Data Synthesis (MV), pp. 428–440.
SOSP-1977-Snyder #analysis #on the: On the Synthesis and Analysis of Protection Systems (LS), pp. 141–150.
ICSE-1976-BarstowK #interactive #performance: Observations on the Interaction Between Coding and Efficiency Knowledge in the PSI Program Synthesis System (DRB, EK), pp. 19–31.
ICSE-1976-Green #design: The Design of the PSI Program Synthesis System (CCG), pp. 4–18.
DAC-1971-WeinzapfelJP #image #interactive #multi #named: IMAGE: An interactive computer system for multi-constrained spatial synthesis (GW, TEJ, JP), pp. 101–108.
DAC-1968-Marin #algorithm #logic #on the #strict #using: On a general synthesis algorithm of logical circuits using a restricted inventory of integrated circuits (MAM).