Using Formal Verification Techniques to Reduce Simulation and Test Effort
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Odile Laurent, Pierre Michel, Virginie Wiels
Using Formal Verification Techniques to Reduce Simulation and Test Effort
FM, 2001.

FME 2001
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@inproceedings{FME-2001-LaurentMW,
	author        = "Odile Laurent and Pierre Michel and Virginie Wiels",
	booktitle     = "{Proceedings of the International Symposium of Formal Methods Europe: Formal Methods for Increasing Software Productivity}",
	doi           = "10.1007/3-540-45251-6_27",
	isbn          = "3-540-41791-5",
	pages         = "465--477",
	publisher     = "{Springer-Verlag}",
	series        = "{Lecture Notes in Computer Science}",
	title         = "{Using Formal Verification Techniques to Reduce Simulation and Test Effort}",
	volume        = 2021,
	year          = 2001,
}

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