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Travelled to:
1 × France
1 × USA
Collaborated with:
G.Eneman J.Cho V.Moroz D.Milojevic M.Choi K.D.Meyer E.Beyne T.Hoffmann G.V.d.Plas A.Mallik P.Zuber T.Liu B.Chava B.Ballal P.R.D.Bario R.Baert K.Croes J.Ryckaert M.Badaroglu D.Verkest
Talks about:
technolog (1) framework (1) systemat (1) configur (1) silicon (1) multipl (1) compact (1) analysi (1) stress (1) analyt (1)

Person: Abdelkarim Mercha

DBLP DBLP: Mercha:Abdelkarim

Contributed to:

DAC 20132013
DATE 20112011

Wrote 2 papers:

DAC-2013-MallikZLCBBBCRBMV #analysis #evaluation #framework #named
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes (AM, PZ, TTL, BC, BB, PRDB, RB, KC, JR, MB, AM, DV), p. 6.
DATE-2011-EnemanCMMCMMBHP #estimation #multi
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations (GE, JC, VM, DM, MC, KDM, AM, EB, TH, GVdP), pp. 505–506.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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