Travelled to:1 × Germany
3 × USA
Collaborated with:D.Sinha P.Banerjee H.Zhou J.Cosgrove R.P.Dick G.Memik P.A.Dinda Y.Iosifidis S.Mamagkakis E.d.Greef A.Bartzas D.Soudris F.Catthoor P.Zuber T.Liu B.Chava B.Ballal P.R.D.Bario R.Baert K.Croes J.Ryckaert M.Badaroglu A.Mercha D.Verkest
Talks about:framework (2) optim (2) dynam (2) base (2) technolog (1) systemat (1) platform (1) parallel (1) frequenc (1) systemc (1)
Person: Arindam Mallik
DBLP: Mallik:Arindam
Contributed to:
20132010
2008
2006Wrote 4 papers:
- DAC-2013-MallikZLCBBBCRBMV #analysis #evaluation #framework #named
- TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes (AM, PZ, TTL, BC, BB, PRDB, RB, KC, JR, MB, AM, DV), p. 6.
- DAC-2010-IosifidisMMGBSC #automation #framework #memory management #optimisation #parallel #platform
- A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms (YI, AM, SM, EdG, AB, DS, FC), pp. 549–554.
- ASPLOS-2008-MallikCDMD #named #performance #scalability
- PICSEL: measuring user-perceived performance to control dynamic frequency scaling (AM, JC, RPD, GM, PAD), pp. 70–79.
- DATE-2006-MallikSBZ #design #optimisation #power management
- Smart bit-width allocation for low power optimization in a systemc based ASIC design environment (AM, DS, PB, HZ), pp. 618–623.