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Travelled to:
1 × Germany
Collaborated with:
R.Vemu J.A.Abraham S.Patil R.Galivanche
Talks about:
processor (1) techniqu (1) control (1) concurr (1) detect (1) logic (1) error (1) cost (1) low (1)

Person: Abhijit Jas

DBLP DBLP: Jas:Abhijit

Contributed to:

DATE 20082008

Wrote 1 papers:

DATE-2008-VemuJAPG #concurrent #detection #fault #logic #low cost
A low-cost concurrent error detection technique for processor control logic (RV, AJ, JAA, SP, RG), pp. 897–902.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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