Person: Azalea Raad

DBLP: Raad:Azalea

Contributed to:

2015

2018

2018

2019

2018

2019

2019

2019

2020

Wrote 10 papers:

ESOP-2015-RaadVG #concurrent #logic #named

CoLoSL: Concurrent Local Subjective Logic (AR, JV, PG), pp. 710–735.

ESOP-2018-RaadLV #consistency #on the #parallel

On Parallel Snapshot Isolation and Release/Acquire Consistency (AR, OL, VV), pp. 940–967.

CIG-2018-CookCR #analysis #constraints #design #game studies

Inferring Design Constraints From Game Ruleset Analysis (MC0, SC, AR), pp. 1–8.

CoG-2019-CookR #analysis #automation #game studies #graph

Hyperstate Space Graphs for Automated Game Analysis (MC0, AR), pp. 1–8.

OOPSLA-2018-RaadV #memory management #persistent #semantics

Persistence semantics for weak memory: integrating epoch persistency with the TSO memory model (AR, VV), p. 27.

OOPSLA-2019-Kokologiannakis #effectiveness #model checking

Effective lock handling in stateless model checking (MK, AR, VV), p. 26.

OOPSLA-2019-RaadWV #formal method #modelling #semantics #transaction

Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models (AR, JW, VV), p. 27.

PLDI-2019-Kokologiannakis #consistency #library #model checking

Model checking for weakly consistent libraries (MK, AR, VV), pp. 96–110.

POPL-2019-RaadDRLV #concurrent #consistency #correctness #declarative #library #memory management #modelling #on the #specification #verification

On library correctness under weak memory consistency: specifying and verifying concurrent libraries under declarative consistency models (AR, MD, LR, OL, VV), p. 31.

POPL-2020-RaadWNV #architecture #semantics

Persistency semantics of the Intel-x86 architecture (AR, JW, GN, VV), p. 31.