Collaborated with:S.Flur P.Sewell S.Sarkar K.E.Gray Will Deacon Jon French A.Sezgin L.Maranget J.Pichon-Pharabod J.Kang Sung Hwan Lee C.Hur K.Nienhuis M.Batty A.Armstrong Thomas Bauereiss Brian Campbell 0001 A.Reid Robert M. Norton Prashanth Mundkur Mark Wassell I.Stark Neel Krishnaswami
Talks about:concurr (4) model (3) oper (3) arm (3) risc (2) isa (2) architectur (1) multicopi (1) simplifi (1) simpler (1)
Person: Christopher Pulte
DBLP: Pulte:Christopher
Contributed to:
201620172018
20192019Wrote 5 papers:
- POPL-2016-FlurGPSSMDS #architecture #concurrent #modelling
- Modelling the ARMv8 architecture, operationally: concurrency and ISA (SF, KEG, CP, SS, AS, LM, WD, PS), pp. 608–621.
- POPL-2017-FlurSPNMGSBS #concurrent
- Mixed-size concurrency: ARM, POWER, C/C++11, and SC (SF, SS, CP, KN, LM, KEG, AS, MB, PS), pp. 429–442.
- POPL-2018-PulteFDFSS #axiom #concurrent #modelling #multi
- Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8 (CP, SF, WD, JF, SS, PS), p. 29.
- PLDI-2019-PultePKLH #concurrent #named #performance
- Promising-ARM/RISC-V: a simpler and faster operational concurrency model (CP, JPP, JK, SHL, CKH), pp. 1–15.
- POPL-2019-ArmstrongBCRGNM #semantics
- ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS (AA, TB, BC0, AR, KEG, RMN, PM, MW, JF, CP, SF, IS, NK, PS), p. 31.