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Travelled to:
1 × USA
Collaborated with:
J.Rose
Talks about:
architectur (1) transistor (1) explor (1) autom (1) size (1) fpga (1)

Person: Ian Kuon

DBLP DBLP: Kuon:Ian

Contributed to:

DAC 20082008

Wrote 1 papers:

DAC-2008-KuonR #architecture #automation
Automated transistor sizing for FPGA architecture exploration (IK, JR), pp. 792–795.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.