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Travelled to:
1 × USA
Collaborated with:
N.Matsumoto T.Hamai C.Ogawa S.Mori
Talks about:
compact (1) method (1) layout (1) vlsi (1) full (1) chip (1)

Person: Joseph Dao

DBLP DBLP: Dao:Joseph

Contributed to:

DAC 19931993

Wrote 1 papers:

DAC-1993-DaoMHOM
A Compaction Method for Full Chip VLSI Layouts (JD, NM, TH, CO, SM), pp. 407–412.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.