BibSLEIGH
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document (74)
system (67)
analysi (59)
base (59)
design (54)

Stem layout$ (all stems)

552 papers:

DACDAC-2015-HanF #analysis #approach #cpu #gpu #graph #scalability
Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems (LH, ZF), p. 6.
DACDAC-2015-OuTLWC
Layout-dependent-effects-aware analytical analog placement (HCO, KHT, JYL, IPW, YWC), p. 6.
DACDAC-2015-XiaoGWYTW #layout #optimisation #self #verification
Layout optimization and template pattern verification for directed self-assembly (DSA) (ZX, DG, MDFW, HY, MCT, HSPW), p. 6.
DATEDATE-2015-LourencoMH #using
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction (NCL, RM, NH), pp. 1156–1161.
DATEDATE-2015-NowosielskiGBVB #design #fault tolerance #named
FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design (RN, LG, SB, GPV, HB), pp. 297–300.
DATEDATE-2015-PerriconeZSHN #3d #design #towards
Towards systematic design of 3D pNML layouts (RP, YZ, KMS, XSH, MTN), pp. 1539–1542.
DocEngDocEng-2015-EskenaziGO #documentation #layout
The Delaunay Document Layout Descriptor (SE, PGK, JMO), pp. 167–175.
DocEngDocEng-2015-HassanH #automation #documentation #flexibility #layout
Knuth-Plass Revisited: Flexible Line-Breaking for Automatic Document Layout (TH, AH), pp. 17–20.
DocEngDocEng-2015-KidoYTA #automation #documentation #layout #optimisation
Document Layout Optimization with Automated Paraphrasing (YK, HY, GT, AA), pp. 13–16.
DocEngDocEng-2015-VernicaV #adaptation #framework #layout #named #synthesis #web
AERO: An Extensible Framework for Adaptive Web Layout Synthesis (RV, NDV), pp. 187–190.
DRRDRR-2015-ChenSWLHI #analysis #dataset #documentation #layout
Ground truth model, tool, and dataset for layout analysis of historical documents (KC, MS, HW, ML, JH, RI), p. 940204.
SIGMODSIGMOD-2015-FengLKX #in memory #layout #memory management #named
ByteSlice: Pushing the Envelop of Main Memory Data Processing with a New Storage Layout (ZF, EL, BK, WX), pp. 31–46.
SASSAS-2015-ChoiCNS #javascript #layout #named #type system
SJS: A Type System for JavaScript with Fixed Object Layout (WC, SC, GCN, KS), pp. 181–198.
CHICHI-2015-ODonovanAH #design #interactive #layout #named
DesignScape: Design with Interactive Layout Suggestions (PO, AA, AH), pp. 1221–1224.
HCIHCI-UC-2015-JachK #layout #online
Factors Influencing Online Shop Layout Preferences (KJ, MK), pp. 419–429.
MoDELSMoDELS-2015-GregoricsGKDD #algorithm #diagrams #layout #visualisation
Textual diagram layout language and visualization algorithm (BG, TG, GFK, AD, GD), pp. 196–205.
OOPSLAOOPSLA-2015-HottelierB #constraints #layout #relational #synthesis
Synthesis of layout engines from relational constraints (TH, RB), pp. 74–88.
ICSTICST-2015-HalleBGB #constraints #layout #testing #web
Testing Web Applications Through Layout Constraints (SH, NB, FG, GLB), pp. 1–8.
DACDAC-2014-DingCM #layout #optimisation #throughput
Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout (YD, CC, WKM), p. 6.
DACDAC-2014-YuP #composition #layout
Layout Decomposition for Quadruple Patterning Lithography and Beyond (BY, DZP), p. 6.
DATEDATE-2014-AndradesRC #design #detection
Signature indexing of design layouts for hotspot detection (CA, MAR, CCC), pp. 1–6.
DRRDRR-2014-TaoTX #documentation #learning #random #using
Document page structure learning for fixed-layout e-books using conditional random fields (XT, ZT, CX), p. ?–9.
HCIHCI-TMT-2014-SteigerLMKK #layout
Deterministic Local Layouts through High-Dimensional Layout Stitching (MS, HLT, TM, AK, JK), pp. 643–651.
HCILCT-NLE-2014-PurgathoferL #architecture #harmful #layout
Layout Considered Harmful: On the Influence of Information Architecture on Dialogue (PP, NL), pp. 216–225.
ICPRICPR-2014-FernandezT #analysis #documentation #layout
EM-Based Layout Analysis Method for Structured Documents (FCF, ORT), pp. 315–320.
MLDMMLDM-2014-BozkirS #layout #named #similarity #visual notation #web
SimiLay: A Developing Web Page Layout Based Visual Similarity Search Engine (ASB, EAS), pp. 457–470.
SEKESEKE-2014-ZhuangZL #fine-grained #framework #layout #reuse #runtime
Runtime Code Reuse Attacks: A Dynamic Framework Bypassing Fine-Grained Address Space Layout Randomization (YZ, TZ, ZL), pp. 609–614.
SIGIRSIGIR-2014-LinGHTXL #layout #retrieval
A mathematics retrieval system for formulae in layout presentations (XL, LG, XH, ZT, YX, XL), pp. 697–706.
MODELSMoDELS-2014-Storrle #comprehension #diagrams #layout #matter #on the #quality #uml
On the Impact of Layout Quality to Understanding UML Diagrams: Size Matters (HS), pp. 518–534.
MODELSMoDELS-2014-Storrle #comprehension #diagrams #layout #matter #on the #quality #uml
On the Impact of Layout Quality to Understanding UML Diagrams: Size Matters (HS), pp. 518–534.
OOPSLAOOPSLA-2014-UrecheBO #data transformation #layout #representation
Late data layout: unifying data representation transformations (VU, EB, MO), pp. 397–416.
CASECASE-2013-FerreiraR #comparison #design #layout #performance #simulation #using
Performance comparison of the virtual cell layout with cellular and job shop configurations using simulation and design of experiments (JCEF, PAR), pp. 795–800.
DACDAC-2013-EbrahimiAT #analysis #approach #multi
A layout-based approach for multiple event transient analysis (ME, HA, MBT), p. 6.
DACDAC-2013-KuangY #approach #composition #layout #performance
An efficient layout decomposition approach for triple patterning lithography (JK, EFYY), p. 6.
DATEDATE-2013-ZhangYH0 #testing
Capturing post-silicon variation by layout-aware path-delay testing (XZ, JY, YH, XL), pp. 288–291.
DocEngDocEng-2013-AlvaroZ #layout
A shape-based layout descriptor for classifying spatial relationships in handwritten math (FA, RZ), pp. 123–126.
DocEngDocEng-2013-PiccoliO #automation #documentation #flexibility #layout
Balancing font sizes for flexibility in automated document layout (RFBP, JBSdO), pp. 151–160.
DRRDRR-2013-AzawiLB #documentation #layout
WFST-based ground truth alignment for difficult historical documents with text modification and layout variations (MIAAA, ML, TMB).
DRRDRR-2013-XuTTS #documentation #segmentation
Graphic composite segmentation for documents with complex layouts (CX, ZT, XT, CS).
ICDARICDAR-2013-AntonacopoulosCPP #analysis #contest #layout
ICDAR 2013 Competition on Historical Newspaper Layout Analysis (HNLA 2013) (AA, CC, CP, SP), pp. 1454–1458.
ICDARICDAR-2013-WeiBSI #analysis #classification #documentation #evaluation #layout
Evaluation of SVM, MLP and GMM Classifiers for Layout Analysis of Historical Documents (HW, MB, FS, RI), pp. 1220–1224.
GT-VMTGT-VMT-2013-MaierM #approach #diagrams #layout
A Pattern-based Approach for Initial Diagram Layout (SM, MM).
HCIHCI-UC-2013-BergmannMSO #automation #case study #generative #layout
Automatic Layout Generation for Digital Photo Albums: A User Study (FBB, IHM, MSS, JBSdO), pp. 117–126.
HCIHIMI-D-2013-ChangSCH #design #interface #layout #on the #performance #topic
On the Reading Performance of Text Layout, Switch Position, Topic of Text, and Luminance Contrast for Chinese E-books Interface Design (WTC, LHS, ZC, KCH), pp. 567–575.
SACSAC-2013-ChanHN #layout #semantics #using #wiki #word
Computing semantic relatedness using word frequency and layout information of Wikipedia (PC, YH, SN), pp. 282–287.
HPCAHPCA-2013-KoibuchiFMC #random
Layout-conscious random topologies for HPC off-chip interconnects (MK, IF, HM, HC), pp. 484–495.
PPoPPPPoPP-2013-LiuDJK #architecture #layout #optimisation
Data layout optimization for GPGPU architectures (JL, WD, OJ, MTK), pp. 283–284.
DACDAC-2012-CongL #architecture #metric #optimisation #synthesis
A metric for layout-friendly microarchitecture optimization in high-level synthesis (JC, BL), pp. 1239–1244.
DACDAC-2012-FangCC #algorithm #composition #layout #novel
A novel layout decomposition algorithm for triple patterning lithography (SYF, YWC, WYC), pp. 1185–1190.
DATEDATE-2012-BesteT #analysis #robust #standard
Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells (MB, MBT), pp. 1609–1614.
DATEDATE-2012-GuptaPMR #optimisation
Layout-aware optimization of stt mrams (SKG, SPP, NNM, KR), pp. 1455–1458.
DATEDATE-2012-PonsMP #layout #metric
Fixed origin corner square inspection layout regularity metric (MP, MNM, CP), pp. 1397–1402.
DocEngDocEng-2012-AcebalBRL #css #implementation #javascript #layout #named
ALMcss: a javascript implementation of the CSS template layout module (CFA, BB, MR, JMCL), pp. 23–32.
DocEngDocEng-2012-GangeMS #layout
Optimal guillotine layout (GG, KM, PJS), pp. 13–22.
DocEngDocEng-2012-MoulderM #how #layout #learning
Learning how to trade off aesthetic criteria in layout (PM, KM), pp. 33–36.
DRRDRR-2012-EsserSMBS #approach #automation #documentation
Automatic indexing of scanned documents: a layout-based approach (DE, DS, KM, MB, AS).
DRRDRR-2012-SchellenbergYZ #retrieval
Layout-based substitution tree indexing and retrieval for mathematical expressions (TS, BY, RZ).
GT-VMTGT-VMT-2012-MaierM #ad hoc #automation #diagrams #editing #layout
Layout Improvement in Diagram Editors by Automatic Ad-hoc Layout (SM, MM).
CHICHI-2012-TeoJB #layout #named
CogTool-Explorer: a model of goal-directed user exploration that considers information layout (LT, BEJ, MHB), pp. 2479–2488.
SIGIRSIGIR-2012-LeiCCIH #layout #retrieval #scalability
Where is who: large-scale photo retrieval by facial attributes and canvas layout (YHL, YYC, BCC, LI, WHH), pp. 701–710.
ICSEICSE-2012-Rodes #layout #source code #stack #towards
Stack layout transformation: Towards diversity for securing binary programs (BR), pp. 1543–1546.
SLESLE-2012-ErdwegRKO #generalised parsing #parsing
Layout-Sensitive Generalized Parsing (SE, TR, CK, KO), pp. 244–263.
DACDAC-2011-BanLP #2d #composition #flexibility #framework #layout
Flexible 2D layout decomposition framework for spacer-type double pattering lithography (YB, KL, DZP), pp. 789–794.
DACDAC-2011-BanY #layout #modelling #optimisation
Layout aware line-edge roughness modeling and poly optimization for leakage minimization (YB, JSY), pp. 447–452.
DACDAC-2011-HsuSPCH #algorithm #distributed #geometry #layout
A distributed algorithm for layout geometry operations (KTH, SS, YCP, CC, TYH), pp. 182–187.
DACDAC-2011-NandakumarM #3d #layout
Layout effects in fine grain 3D integrated regular microprocessor blocks (VSN, MMS), pp. 639–644.
DACDAC-2011-RyzhenkoB #geometry #layout #physics #synthesis
Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries (NR, SB), pp. 83–88.
DATEDATE-2011-GraupnerJW #approach #design #generative #layout #optimisation
Generator based approach for analog circuit and layout design and optimization (AG, RJ, RW), pp. 1675–1680.
DocEngDocEng-2011-Brailsford #automation #layout
Automated conversion of web-based marriage register data into a printed format with predefined layout (DFB), pp. 61–64.
DocEngDocEng-2011-GangeMMS #automation #layout
Optimal automatic table layout (GG, KM, PM, PJS), pp. 23–32.
DocEngDocEng-2011-NebelingMSN #adaptation #effectiveness #layout #web
Adaptive layout template for effective web content presentation in large-screen contexts (MN, FM, LS, MCN), pp. 219–228.
DocEngDocEng-2011-PiccoliCCOM #documentation #for free #interactive #layout #novel
A novel physics-based interaction model for free document layout (RFBP, RC, NCC, JBSdO, IHM), pp. 153–162.
ICDARICDAR-2011-AntonacopoulosCPP #analysis #contest #documentation #layout
Historical Document Layout Analysis Competition (AA, CC, CP, SP), pp. 1516–1520.
ICDARICDAR-2011-BaechlerI #analysis #layout #multi #using
Multi Resolution Layout Analysis of Medieval Manuscripts Using Dynamic MLP (MB, RI), pp. 1185–1189.
ICDARICDAR-2011-BukhariSB11a #analysis #documentation #image #layout #performance
High Performance Layout Analysis of Arabic and Urdu Document Images (SSB, FS, TMB), pp. 1275–1279.
ICDARICDAR-2011-ClausnerPA #documentation #layout #named
Aletheia — An Advanced Document Layout and Text Ground-Truthing System for Production Environments (CC, SP, AA), pp. 48–52.
ICDARICDAR-2011-ClausnerPA11a #analysis #documentation #evaluation #layout #performance
Scenario Driven In-depth Performance Evaluation of Document Layout Analysis Methods (CC, SP, AA), pp. 1404–1408.
ICDARICDAR-2011-DiemKS #analysis #classification #documentation #layout
Text Classification and Document Layout Analysis of Paper Fragments (MD, FK, RS), pp. 854–858.
ICDARICDAR-2011-GarzSD #analysis #layout #using
Layout Analysis for Historical Manuscripts Using Sift Features (AG, RS, MD), pp. 508–512.
ICDARICDAR-2011-HadjarI #generative #layout
Minimizing User Annotations in the Generation of Layout Ground-Truthed Data (KH, RI), pp. 703–707.
ICDARICDAR-2011-WinderAS #algorithm #documentation #segmentation
Extending Page Segmentation Algorithms for Mixed-Layout Document Processing (AW, TLA, EHBS), pp. 1245–1249.
ICSMEICSM-2011-Sharif #architecture #assessment #diagrams #empirical #uml
Empirical assessment of UML class diagram layouts based on architectural importance (BS), pp. 544–549.
AGTIVEAGTIVE-2011-MaierM #diagrams #editing #integration #layout
Integration of a Pattern-Based Layout Engine into Diagram Editors (SM, MM), pp. 89–96.
CHICHI-2011-FrischKLD #layout #multi #tool support
Grids & guides: multi-touch layout and alignment tools (MF, SK, RL, RD), pp. 1615–1618.
CHICHI-2011-NebelingMN #evaluation #layout #metric
Metrics for the evaluation of news site content layout in large-screen contexts (MN, FM, MCN), pp. 1511–1520.
HCIDUXU-v2-2011-NakataniOKNH #case study #internet #layout
The Layout for the User-Friendly Manual: Case Study on an Internet Set-Up Manual (MN, TO, YK, AN, SH), pp. 40–45.
OOPSLAOOPSLA-2011-VerwaestBLN #flexibility #lightweight
Flexible object layouts: enabling lightweight language extensions by intercepting slot access (TV, CB, ML, ON), pp. 959–972.
POPLPOPL-2011-RamananandroRL #c++ #inheritance #layout #multi #verification
Formal verification of object layout for c++ multiple inheritance (TR, GDR, XL), pp. 67–80.
SLESLE-2011-JongeV #algorithm #layout #refactoring
An Algorithm for Layout Preservation in Refactoring Transformations (MdJ, EV), pp. 40–59.
CCCC-2011-HenrettySPFRS #architecture #layout
Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures (TH, KS, LNP, FF, JR, PS), pp. 225–245.
HPDCHPDC-2011-SongYCS #file system #layout #parallel
A cost-intelligent application-specific data layout scheme for parallel file systems (HS, YY, YC, XHS), pp. 37–48.
CASECASE-2010-WangKF #approach #assembly #hybrid #layout
A hybrid approach for dynamic assembly shop floor layout (LW, SK, HYF), pp. 604–609.
DACDAC-2010-Agarwal #composition
Frequency domain decomposition of layouts for double dipole lithography (KA), pp. 404–407.
DACDAC-2010-BanP #layout #modelling #optimisation #robust
Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography (YB, DZP), pp. 408–411.
DACDAC-2010-JoshiSTASB #modelling
Closed-form modeling of layout-dependent mechanical stress (VJ, VS, AT, KA, DS, DB), pp. 673–678.
DACDAC-2010-YangALLP #3d #analysis #layout #optimisation
TSV stress aware timing analysis with applications to 3D-IC layout optimization (JSY, KA, YJL, SKL, DZP), pp. 803–806.
DATEDATE-2010-LiuZYX #power management #pseudo #testing
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects (XL, YZ, FY, QX), pp. 1432–1437.
DocEngDocEng-2010-BaechlerI #layout
Medieval manuscript layout model (MB, RI), pp. 275–278.
DocEngDocEng-2010-BilaucaH #automation #layout
A new model for automated table layout (MB, PH), pp. 169–176.
DocEngDocEng-2010-BilaucaH10a #authoring #documentation #layout #performance #tool support
Table layout performance of document authoring tools (MB, PH), pp. 199–202.
DocEngDocEng-2010-Lumley #documentation #functional #invariant #layout
Pre-evaluation of invariant layout in functional variable-data documents (JWL), pp. 251–254.
DocEngDocEng-2010-SpenglerG #documentation #layout #random #web
Document structure meets page layout: loopy random fields for web news content extraction (AS, PG), pp. 151–160.
DocEngDocEng-2010-TerradesTSRVJ #analysis #documentation #interactive #layout
Interactive layout analysis and transcription systems for historic handwritten documents (ORT, AHT, NS, VR, EV, AJ), pp. 219–222.
SIGMODSIGMOD-2010-OzmenSSD #database #layout
Workload-aware storage layout for database systems (OO, KS, JS, SD), pp. 939–950.
CSEETCSEET-2010-SharifM #design pattern #detection #layout
The Effects of Layout on Detecting the Role of Design Patterns (BS, JIM), pp. 41–48.
ICSMEICSM-2010-SharifM #comprehension #design pattern #eye tracking #layout
An eye tracking study on the effects of layout in understanding the role of design patterns (BS, JIM), pp. 1–10.
SOFTVISSOFTVIS-2010-AlbrechtEHK #algorithm #automation #layout #process
An automatic layout algorithm for BPEL processes (BA, PE, MH, MK), pp. 173–182.
SOFTVISSOFTVIS-2010-Zeckzer #layout #matrix #using #visualisation
Visualizing software entities using a matrix layout (DZ), pp. 207–208.
SACSAC-2010-LecerfC #documentation #layout #ranking #retrieval #scalability
Scalable indexing for layout based document retrieval and ranking (LL, BC), pp. 28–32.
SACSAC-2010-RiponGHT #approach #layout #multi #problem #using
Multi-objective evolutionary approach for solving facility layout problem using local search (KSNR, KG, MH, JT), pp. 1155–1156.
SACSAC-2010-RyuCC #image #layout #named #using
PHOTOLAND: a new image layout system using spatio-temporal information in digital photos (DSR, WKC, HGC), pp. 1884–1891.
CGOCGO-2010-WangWY #layout #memory management #on the
On improving heap memory layout by dynamic pool allocation (ZW, CW, PCY), pp. 92–100.
HPDCHPDC-2010-ChenSTS #optimisation
A layout-aware optimization strategy for collective I/O (YC, HS, RT, XHS), pp. 360–363.
DACDAC-2009-YeLCC #analysis #layout #process #variability
Variability analysis under layout pattern-dependent rapid-thermal annealing process (YY, FL, MC, YC), pp. 551–556.
DATEDATE-2009-BobbaZPAM #design #logic #standard #synthesis
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis (SB, JZ, AP, DA, GDM), pp. 616–621.
DATEDATE-2009-GrabBCCFLS #layout #synthesis
Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.
DocEngDocEng-2009-BalinskyHW #layout
Aesthetically-driven layout engine (HB, JRH, AW), pp. 119–122.
DocEngDocEng-2009-BertholdoVA #documentation #readability
Layout-aware limiarization for readability enhancement of degraded historical documents (FB, EV, AdAA), pp. 131–134.
DRRDRR-2009-IwamuraNHKUO #documentation #image
Layout-free dewarping of planar document images (MI, RN, AH, KK, SU, SO), pp. 1–10.
HTHT-2009-Francisco-RevillaC #layout #web
Interpreting the layout of web pages (LFR, JC), pp. 157–166.
ICDARICDAR-2009-AntonacopoulosBPP #analysis #dataset #documentation #evaluation #layout #performance
A Realistic Dataset for Performance Evaluation of Document Layout Analysis (AA, DB, CP, SP), pp. 296–300.
ICDARICDAR-2009-FerilliBEB #analysis #layout
A Distance-Based Technique for Non-Manhattan Layout Analysis (SF, MB, FE, TMAB), pp. 231–235.
ICDARICDAR-2009-GordoV #classification #documentation #invariant #layout #retrieval
A Rotation Invariant Page Layout Descriptor for Document Classification and Retrieval (AG, EV), pp. 481–485.
ICDARICDAR-2009-MalleronEEDR #analysis #documentation #layout
Text Lines and Snippets Extraction for 19th Century Handwriting Documents Layout Analysis (VM, VE, HE, SDC, PR), pp. 1001–1005.
ICDARICDAR-2009-MontreuilGHN #2d #documentation #layout #random #using
Unconstrained Handwritten Document Layout Extraction Using 2D Conditional Random Fields (FM, EG, LH, SN), pp. 853–857.
ICDARICDAR-2009-Smith #analysis #detection #hybrid #layout
Hybrid Page Layout Analysis via Tab-Stop Detection (RWS), pp. 241–245.
ICDARICDAR-2009-TatsumiHK #layout #optimisation
Context-oriented Layout Optimization of Large-Print Textbooks (IT, HH, MK), pp. 1016–1020.
ICPCICPC-2009-SharifM #comprehension #diagrams #empirical #uml
An empirical study on the comprehension of stereotyped UML class diagram layouts (BS, JIM), pp. 268–272.
FMFM-2009-Gast #memory management #reasoning
Reasoning about Memory Layouts (HG), pp. 628–643.
VISSOFTVISSOFT-2009-SharifM #comprehension #diagrams #empirical #layout #uml
The effect of layout on the comprehension of UML class diagrams: A controlled experiment (BS, JIM), pp. 11–18.
ICEISICEIS-HCI-2009-TroianoBAC #algorithm #layout #mobile #optimisation #search-based #web
Web Form Page in Mobile Devices — Optimization of Layout with a Simple Genetic Algorithm (LT, CB, RA, GC), pp. 118–123.
ASEASE-2008-MooreS #analysis #design #layout
Combining the Analysis of Spatial Layout and Text to Support Design Exploration (JMM, FMSI), pp. 379–382.
CASECASE-2008-TeoP #heuristic #hybrid #layout #problem
A hybrid ACO/PSO heuristic to solve single row layout problem (YTT, SGP), pp. 597–602.
DACDAC-2008-JoshiCSBA #power management #reduction #using
Leakage power reduction using stress-enhanced layouts (VJ, BC, DS, DB, KA), pp. 912–917.
DACDAC-2008-TamPB #analysis #automation #layout #locality #precise #using
Precise failure localization using automated layout analysis of diagnosis candidates (WCT, OP, RD(B), pp. 367–372.
DATEDATE-2008-ChakrabortySP #layout #optimisation
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices (AC, SXS, DZP), pp. 849–855.
DATEDATE-2008-LeeNKT #fault #generative
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation (JL, SN, MK, MT), pp. 1172–1177.
DocEngDocEng-2008-HurstM #layout
Satisficing scrolls: a shortcut to satisfactory layout (NH, KM), pp. 131–140.
DocEngDocEng-2008-IorioFVLW #abstraction #layout
Higher-level layout through topological abstraction (ADI, LF, FV, JWL, TW), pp. 90–99.
DocEngDocEng-2008-Oliveira #algorithm #automation #documentation #layout
Two algorithms for automatic document page layout (JBSdO), pp. 141–149.
WCREWCRE-2008-KuhnLN #consistency #layout
Consistent Layout for Thematic Software Maps (AK, PL, ON), pp. 209–218.
GT-VMTGT-VMT-2008-MaierM #algorithm #layout
A Static Layout Algorithm for DiaMeta (SM, MM).
CHICHI-2008-GoldbergHM #distance #layout
Information distance and orientation in liquid layout (JHG, JH, LM), pp. 1153–1156.
SOFTVISSOFTVIS-2008-Eichelberger #automation #case study #diagrams #layout #uml
Automatic layout of UML use case diagrams (HE), pp. 105–114.
ICPRICPR-2008-BridsonA #analysis #approach #evaluation #geometry #layout #performance
A geometric approach for accurate and efficient performance evaluation of layout analysis methods (DB, AA), pp. 1–4.
ICPRICPR-2008-FerilliBBE #comprehension #documentation #incremental #layout #machine learning
Incremental machine learning techniques for document layout understanding (SF, MB, TMAB, FE), pp. 1–4.
ICPRICPR-2008-HennigS #automation
Tailoring text for automatic layouting of newspaper pages (LH, TS), pp. 1–4.
ICPRICPR-2008-JhaN #independence #layout #representation
Wang Notation Tool: Layout independent representation of tables (PJ, GN), pp. 1–4.
ICPRICPR-2008-ShafaitBKB #analysis #layout #modelling #statistics #variability
Background variability modeling for statistical layout analysis (FS, JvB, DK, TMB), pp. 1–4.
ECOOPECOOP-2008-ZhangH #adaptation #layout #online
Online Phase-Adaptive Data Layout Selection (CZ, MH), pp. 309–334.
SACSAC-2008-ChidlovskiiL #dependence #documentation #layout #network
Stacked dependency networks for layout document structuring (BC, LL), pp. 424–428.
SACSAC-2008-TakasuA #analysis #documentation #information management #layout #probability
Information extraction from scanned documents by stochastic page layout analysis (AT, KA), pp. 447–448.
CCCC-2008-NitaG #automation #c #multi
Automatic Transformation of Bit-Level C Code to Support Multiple Equivalent Data Layouts (MN, DG), pp. 85–99.
LCTESLCTES-2008-ChoPIDPK #array #compilation #data access #layout #optimisation
Compiler driven data layout optimization for regular/irregular array access patterns (DC, SP, II, ND, YP, SK), pp. 41–50.
PPoPPPPoPP-2008-NishtalaAC #communication #layout #performance
Performance without pain = productivity: data layout and collective communication in UPC (RN, GA, CC), pp. 99–110.
CASECASE-2007-FogelBRSMG #automation #layout #modelling #symmetry
Automated Tracking of Pallets in Warehouses: Beacon Layout and Asymmetric Ultrasound Observation Models (MF, NB, HR, JS, MQM, KG), pp. 678–685.
DACDAC-2007-TsaiZT #design #layout #modelling
Modeling Litho-Constrained Design Layout (MCT, DZ, ZT), pp. 354–357.
DATEDATE-2007-BaneresCK
Layout-aware gate duplication and buffer insertion (DB, JC, MK), pp. 1367–1372.
DRRDRR-2007-ZouLT #analysis #layout #online
Online medical journal article layout analysis (JZ, DXL, GRT).
ICDARICDAR-2007-AntonacopoulosB #analysis #framework #layout #performance
Performance Analysis Framework for Layout Analysis Methods (AA, DB), pp. 1258–1262.
ICDARICDAR-2007-BulacuKSZ #analysis #documentation #layout
Layout Analysis of Handwritten Historical Documents for Searching the Archive of the Cabinet of the Dutch Queen (MB, RvK, LS, TvdZ), pp. 357–361.
ICDARICDAR-2007-Burget #documentation #html #information management #layout
Layout Based Information Extraction from HTML Documents (RB), pp. 624–628.
ICDARICDAR-2007-ChenMT #documentation #layout #logic #recognition
Simultaneous Layout Style and Logical Entity Recognition in a Heterogeneous Collection of Documents (SC, SM, GT), pp. 118–122.
ICDARICDAR-2007-HiranoOOY #analysis #documentation #information management #layout
Text and Layout Information Extraction from Document Files of Various Formats Based on the Analysis of Page Description Language (TH, YO, YO, FY), pp. 262–266.
ICDARICDAR-2007-LemaitreGP #2d #analysis #approach #layout #markov
Preliminary experiments in layout analysis of handwritten letters based on textural and spatial information and a 2D Markovian approach (ML, EG, FJP), pp. 1023–1027.
ICDARICDAR-2007-MinagawaFTF #analysis #image #layout #logic
Logical Structure Analysis for Form Images with Arbitrary Layout by Belief Propagation (AM, YF, HT, KF), pp. 714–718.
ICDARICDAR-2007-YoshidaN #approach #documentation #modelling #parsing #web
Web Document Parsing: A New Approach to Modeling Layout-Language Relations (MY, HN), pp. 203–207.
AGTIVEAGTIVE-2007-MaierM #algorithm #editing #layout #metamodelling #modelling
A Generic Layout Algorithm for Meta-model Based Editors (SM, MM), pp. 66–81.
HCIHCI-IPT-2007-ChenLWS #layout
Screen Layout on Color Search Task for Customized Product Color Combination Selection (CYC, YJL, FGW, CFS), pp. 32–40.
SIGIRSIGIR-2007-ChibaneD #algorithm #layout #segmentation #topic #visual notation #web
A web page topic segmentation algorithm based on visual criteria and content layout (IC, BLD), pp. 817–818.
SIGIRSIGIR-2007-Obrador #documentation #image #layout #retrieval
Document layout and color driven image retrieval (PO), pp. 889–890.
CCCC-2007-JeonSH #data access #layout #using
Layout Transformations for Heap Objects Using Static Access Patterns (JJ, KS, HH), pp. 187–201.
CGOCGO-2007-RamanHM #layout #optimisation #parallel #source code #thread
Structure Layout Optimization for Multithreaded Programs (ER, RH, SM), pp. 271–282.
DATEDATE-2006-AngioliniMCBR #layout
Contrasting a NoC and a traditional interconnect fabric with layout awareness (FA, PM, SC, LB, LR), pp. 124–129.
DATEDATE-2006-IizukaIA #layout #optimisation
Timing-driven cell layout de-compaction for yield optimization by critical area minimization (TI, MI, KA), pp. 884–889.
DATEDATE-2006-KastnerGHBKBS #communication #layout #optimisation #synthesis
Layout driven data communication optimization for high level synthesis (RK, WG, XH, FB, AK, PB, MS), pp. 1185–1190.
DATEDATE-2006-ShinKKH #embedded #memory management
Restructuring field layouts for embedded memory systems (KS, JK, SK, HH), pp. 937–942.
DocEngDocEng-2006-HurstMA #layout #problem
Solving the simple continuous table layout problem (NH, KM, DWA), pp. 28–30.
DocEngDocEng-2006-LumleyGR #layout
Resolving layout interdependency with presentational variables (JWL, RG, OR), pp. 95–97.
DocEngDocEng-2006-MacdonaldBL #documentation #layout
Evaluating invariances in document layout functions (AJM, DFB, JWL), pp. 25–27.
DRRDRR-2006-LinCND #comprehension #documentation #layout #version control
Active document versioning: from layout understanding to adjustment (XL, HC, GN, ED).
SOFTVISSOFTVIS-2006-GauvinB #automation #data flow #layout #programming language #visual notation
Transparency, holophrasting, and automatic layout applied to control structures for visual dataflow programming languages (SG, OB), pp. 67–75.
SOFTVISSOFTVIS-2006-GudenbergNEE #diagrams #layout #uml
Evolutionary layout of UML class diagrams (JWvG, AN, ME, HE), pp. 163–164.
SOFTVISSOFTVIS-2006-Jucknath-JohnGT #development #layout #modelling
Evolutionary layout: preserving the mental map during the development of class models (SJJ, DG, GT), pp. 165–166.
ECIRECIR-2006-YaoWLLM #layout #ranking #visual notation #web
Ranking Web News Via Homepage Visual Layout and Cross-Site Voting (JY, JW, ZL, ML, WYM), pp. 131–142.
ICPRICPR-v2-2006-LiuCC #analysis #image #layout
Latent Layout Analysis for Discovering Objects in Images (DL, DC, TC), pp. 468–471.
ICPRICPR-v4-2006-TokaiH #layout #multi #navigation
Attention Navigation by Keeping Screen Layout for Switching Multiple Views (ST, HH), pp. 766–769.
PPDPPPDP-2006-NguyenO #compilation #layout #ml #morphism #polymorphism
Compiling ML polymorphism with explicit layout bitmap (HDN, AO), pp. 237–248.
CGOCGO-2006-HundtMC #layout #optimisation
Practical Structure Layout Optimization and Advice (RH, SM, DRC), pp. 233–244.
LCTESLCTES-2006-PlatenE #feedback #layout #optimisation
Feedback linking: optimizing object code layout for updates (CvP, JE), pp. 2–11.
CASECASE-2005-ZhuD #design #layout #synthesis
Grasp synthesis and fixture layout design in discrete domain (XZ, HD), pp. 73–78.
DACDAC-2005-BhattacharyaJS #optimisation
Template-driven parasitic-aware optimization of analog integrated circuit layouts (SB, NJ, CJRS), pp. 644–647.
DACDAC-2005-NieKT #incremental #layout
A watermarking system for IP protection by a post layout incremental router (TN, TK, MT), pp. 218–221.
DATEDATE-2005-ChenKK #approach #constraints #layout #memory management #network #optimisation
A Constraint Network Based Approach to Memory Layout Optimization (GC, MTK, MK), pp. 1156–1161.
DATEDATE-2005-ChenLL #integration #layout #multi #verification
Integration, Verification and Layout of a Complex Multimedia SOC (CLC, JYL, YLL), pp. 1116–1117.
DocEngDocEng-2005-LumleyGR #documentation #framework #layout
A framework for structure, layout & function in documents (JWL, RG, OR), pp. 32–41.
ICDARICDAR-2005-BeheraLI #documentation #geometry #identification #using
Enhancement of Layout-based Identification of Low-resolution Documents using Geometrical Color Distribution (AB, DL, RI), pp. 468–472.
ICDARICDAR-2005-BerardiACM #analysis #layout #process
A color-based layout analysis to process censorship cards of film archives (MB, OA, MC, DM), pp. 1110–1114.
ICDARICDAR-2005-ChaoL #documentation #layout #reuse
Capturing the Layout of Electronic Documents for Reuse in Variable Data Printing (HC, XL), pp. 940–944.
ICDARICDAR-2005-HuangDDGH #documentation #layout #ranking
Document Ranking by Layout Relevance (MH, DD, DSD, LG, BAH), pp. 362–366.
ICDARICDAR-2005-Lin #documentation #layout #synthesis
Active Document Layout Synthesis (XL), pp. 86–90.
ICDARICDAR-2005-MarinaiMS #documentation #image #layout #reduction #retrieval
Layout based document image retrieval by means of XY tree reduction (SM, EM, GS), pp. 432–436.
ICDARICDAR-2005-Sun #documentation #layout #segmentation
Page Segmentation for Manhattan and Non-Manhattan Layout Documents via Selective CRLA (HMS), pp. 116–120.
ICDARICDAR-2005-TakiguchiOM #comprehension #layout #recognition #semantics
A Fundamental Study of Output Translation from Layout Recognition and Semantic Understanding System for Mathematical Formulae (YT, MO, YM), pp. 745–749.
ICDARICDAR-2005-YingsaereeK #analysis #detection #documentation #layout #rule-based
Rule-based Middle-level Character Detection for Simplifying Thai Document Layout Analysis (CY, AK), pp. 888–892.
IWPCIWPC-2005-SunW #comprehension #diagrams #layout #on the #uml
On Evaluating the Layout of UML Class Diagrams for Program Comprehension (DS, KW), pp. 317–326.
PLDIPLDI-2005-LattnerA #automation #data type #layout #performance
Automatic pool allocation: improving performance by controlling data structure layout in the heap (CL, VSA), pp. 129–142.
SOFTVISSOFTVIS-2005-NoackL #graph #layout #modelling
A space of layout styles for hierarchical graph models of software systems (AN, CL), pp. 155–164.
VISSOFTVISSOFT-2005-AndriyevskaDSM #architecture #diagrams #layout #uml
Evaluating UML Class Diagram Layout based on Architectural Importance (OA, ND, BS, JIM), pp. 14–19.
SACSAC-2005-Hosobe #constraints #documentation #layout #linear #web
Solving linear and one-way constraints for web document layout (HH), pp. 1252–1253.
PPoPPPPoPP-2005-SonCKC #compilation #energy #layout #parallel
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems (SWS, GC, MTK, ANC), pp. 174–185.
DACDAC-2004-AgarwalSYV #modelling #performance
Fast and accurate parasitic capacitance models for layout-aware (AA, HS, VY, RV), pp. 145–150.
DACDAC-2004-AlpertHHQ #flexibility #layout #performance #physics
Fast and flexible buffer trees that navigate the physical layout environment (CJA, MH, JH, STQ), pp. 24–29.
DACDAC-2004-BhattacharyaJHS #design #scalability
Correct-by-construction layout-centric retargeting of large analog designs (SB, NJ, RH, CJRS), pp. 139–144.
DACDAC-2004-CaoK #logic #optimisation
Post-layout logic optimization of domino circuits (AC, CKK), pp. 820–825.
DACDAC-2004-JerkeLS #design #layout
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs (GJ, JL, JS), pp. 181–184.
DACDAC-2004-LiuM #estimation
Pre-layout wire length and congestion estimation (QL, MMS), pp. 582–587.
DACDAC-2004-XuPB #layout #named #optimisation
ORACLE: optimization with recourse of analog circuits including layout extraction (YX, LTP, SPB), pp. 151–154.
DACDAC-2004-YoshidaDB #estimation #standard
Accurate pre-layout estimation of standard cell characteristics (HY, KD, VB), pp. 208–211.
DATEDATE-DF-2004-DaglioIRRS #component #performance #simulation
Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components (PD, DI, DR, CR, SS), pp. 336–337.
DATEDATE-v1-2004-BabighianBM04a #distributed
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating (PB, LB, EM), pp. 720–723.
DATEDATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DATEDATE-v1-2004-ThepayasuwanD #architecture #layout #synthesis
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (NT, AD), pp. 108–113.
DATEDATE-v2-2004-VrankenSW #layout
Impact of Test Point Insertion on Silicon Area and Timing during Layout (HPEV, FSS, HJW), pp. 810–815.
DocEngDocEng-2004-HarringtonNJRT #automation #documentation #layout #metric
Aesthetic measures for automated document layout (SJH, JFN, RPJ, PGR, NT), pp. 109–111.
VLDBVLDB-2004-ShaoSSAG #layout #memory management #named
Clotho: Decoupling memory page layout from storage organization (MS, JS, SWS, AA, GRG), pp. 696–707.
SACSAC-2004-TominskiAS #visualisation
Axes-based visualizations with radial layouts (CT, JA, HS), pp. 1242–1247.
CGOCGO-2004-SoHZ #layout #memory management #parallel
Custom Data Layout for Memory Parallelism (BS, MWH, HEZ), pp. 291–302.
DACDAC-2003-ChenCCKMSYZ #algebra #clustering #layout #multi
An algebraic multigrid solver for analytical placement with layout based clustering (HC, CKC, NCC, ABK, JFM, PS, BY, ZZ), pp. 794–799.
DACDAC-2003-ChoiK #design #embedded #layout #memory management #performance
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design (YC, TK), pp. 881–886.
DATEDATE-2003-GirardiB #automation #generative #layout #named
LIT — An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks (AG, SB), pp. 11106–11107.
DATEDATE-2003-GoelM #architecture #design
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization (SKG, EJM), pp. 10738–10741.
DATEDATE-2003-HettiaratchiC #approach #clustering #energy #layout #performance
Mesh Partitioning Approach to Energy Efficient Data Layout (SH, PYKC), pp. 11076–11081.
DATEDATE-2003-RenczSP #algorithm #layout #performance #simulation
A Fast Algorithm for the Layout Based Electro-Thermal Simulation (MR, VS, AP), pp. 11032–11037.
ICDARICDAR-2003-Breuel #algorithm #analysis #documentation #layout
An Algorithm for Finding Maximal Whitespace Rectangles at Arbitrary Orientations for Document Layout Analysis (TMB), pp. 66–70.
ICDARICDAR-2003-EglinB #classification #documentation #layout #query #similarity #visual notation
Document page similarity based on layout visual saliency: Application to query by example and document classification (VE, SB), pp. 1208–1212.
ICDARICDAR-2003-FutrelleSCG #analysis #classification #diagrams #documentation #layout
Extraction, layout analysis and classification of diagrams in PDF documents (RPF, MS, CC, AEG), pp. 1007–1014.
ICDARICDAR-2003-MalerbaEACB #approach #documentation #layout #machine learning
Correcting the Document Layout: A Machine Learning Approach (DM, FE, OA, MC, MB), p. 97–?.
SIGMODSIGMOD-2003-PadmanabhanBMCH #clustering #layout #multi
Multi-Dimensional Clustering: A New Data Layout Scheme in DB2 (SP, BB, TM, LC, MH), pp. 637–641.
SOFTVISSOFTVIS-2003-EiglspergerKS #approach #automation #diagrams #layout #uml
A Topology-Shape-Metrics Approach for the Automatic Layout of UML Class Diagram (ME, MK, MS), pp. 189–198.
VISSOFTVISSOFT-2003-EichelbergerG #diagrams #layout #state of the art #uml
UML Class Diagrams – State of the Art in Layout Techniques (HE, JWvG), pp. 30–34.
VISSOFTVISSOFT-2003-EichelbergerW #diagrams #layout #uml
Demonstration of Advanced Layout of UML Class Diagrams by SugiBib (HE, JW), pp. 58–59.
ICMLICML-2003-BerardiCEM #analysis #layout #learning #logic programming #source code
Learning Logic Programs for Layout Analysis Correction (MB, MC, FE, DM), pp. 27–34.
ECOOPECOOP-2003-ZibinG #2d #layout
Two-Dimensional Bi-directional Object Layout (YZ, JYG), pp. 329–350.
POPLPOPL-2003-PetersenHCP #layout #memory management #type system
A type theory for memory allocation and data layout (LP, RH, KC, FP), pp. 172–184.
ICSEICSE-2003-SeyboldGMM #adaptation #effectiveness #layout #modelling #visual notation
An Effective Layout Adaptation Technique for a Graphical Modeling Tool (CS, MG, SM, NMS), pp. 826–827.
DACDAC-2002-UmK #synthesis
Layout-aware synthesis of arithmetic circuits (JU, TK), pp. 207–212.
DATEDATE-2002-KutzschebauchS #composition #layout
Layout Driven Decomposition with Congestion Consideration (TK, LS), pp. 672–676.
DATEDATE-2002-SommerRHGMMECSN #design #layout #specification #top-down
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications (RS, IRH, EH, UG, PM, FM, KE, CC, PS, GN), pp. 884–891.
CIKMCIKM-2002-RosenfeldFA #documentation #layout #visual notation
Structural extraction from visual layout of documents (BR, RF, YA), pp. 203–210.
ICPRICPR-v3-2002-LuT #analysis #documentation #image #layout #word
Word Spotting in Chinese Document Images without Layout Analysis (YL, CLT), pp. 57–60.
POPLPOPL-2002-RubinBC #framework #optimisation #performance
An efficient profile-analysis framework for data-layout optimizations (SR, RB, TMC), pp. 140–153.
SACSAC-2002-KangY #layout #multi
Smoothed fetching: bridging the data layout and transmission schemes in multimedia servers (SK, HYY), pp. 755–760.
DACDAC-2001-BeniniMMMP #architecture #embedded #layout #memory management #synthesis
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (LB, LM, AM, EM, MP), pp. 784–789.
DACDAC-2001-ChangWM #logic #using
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques (CWJC, KW, MMS), pp. 97–102.
DACDAC-2001-RiegerMP #design #layout
Layout Design Methodologies for Sub-Wavelength Manufacturing (MLR, JPM, SP), pp. 85–88.
DACDAC-2001-SchellenbergTCS #design #layout
Adoption of OPC and the Impact on Design and Layout (FMS, OT, LC, BS), pp. 89–92.
DACDAC-2001-SolomonH #layout #using
Using Texture Mapping with Mipmapping to Render a VLSI Layout (JS, MH), pp. 500–505.
DATEDATE-2001-KoranneG #analysis #automation #geometry #layout #on the
On automatic analysis of geometrically proximate nets in VSLI layout (SK, OPG), p. 818.
DATEDATE-2001-KulkarniGMCM #embedded #layout #multi
Cache conscious data layout organization for embedded multimedia applications (CK, CG, MM, FC, HDM), pp. 686–693.
DATEDATE-2001-MacchiaruloBM #generative #layout #on the fly
On-the-fly layout generation for PTL macrocells (LM, LB, EM), pp. 546–551.
ICDARICDAR-2001-HaseYSS #layout #recognition
Alignment of Free Layout Color Texts for Character Recognition (HH, MY, TS, CYS), pp. 932–936.
ICDARICDAR-2001-Hurst #layout #using
Layout and Language: Exploring Text Block Discovery in Tables Using Linguistic Resources (MH), pp. 523–527.
ICDARICDAR-2001-LiuLHY #algorithm #analysis #component #layout
A New Component Based Algorithm for Newspaper Layout Analysis (FL, YL, DH, MY), pp. 1176–1180.
ICDARICDAR-2001-WongSA01a #analysis #layout
Use of Colour in Form Layout Analysis (WSW, NS, TA), pp. 942–946.
DACDAC-2000-RanterMPVSGS #automation #design #layout #named
CYCLONE: automated design and layout of RF LC-oscillators (CDR, BDM, GVdP, PJV, MS, GGEG, WMCS), pp. 11–14.
DATEDATE-2000-BouraiS #layout #optimisation
Layout Compaction for Yield Optimization via Critical Area Minimization (YB, CJRS), pp. 122–125.
DATEDATE-2000-DessoukyLP #performance #synthesis
Layout-Oriented Synthesis of High Performance Analog Circuits (MD, MML, JP), pp. 53–57.
IFLIFL-2000-Grelck #array #effectiveness #layout
Improving Cache Effectiveness through Array Data Layout Manipulation in SAC (CG), pp. 231–248.
ICPRICPR-v1-2000-Mitchell #analysis #documentation #layout #segmentation #using
Document Page Segmentation and Layout Analysis Using Soft Ordering (PEM, HY), pp. 1458–1461.
ICPRICPR-v4-2000-OkunP #analysis #automation #documentation #evaluation #generative #layout
Automatic Ground-Truth Generation for Skew-Tolerance Evaluation of Document Layout Analysis Methods (OO, MP), pp. 4376–4379.
ICPRICPR-v4-2000-RyuLK #analysis #documentation #geometry #independence #layout
Parameter-Independent Geometric Document Layout Analysis (DSR, SWL, SMK), pp. 4397–4400.
ICPRICPR-v4-2000-WatanabeS #analysis #documentation #layout
Layout Analysis of Complex Documents (TW, TS), pp. 4447–4450.
ECOOPECOOP-2000-EckelG #empirical #optimisation
Empirical Study of Object-Layout Strategies and Optimization Techniques (NE, JYG), pp. 394–421.
HPCAHPCA-2000-BurnsG #layout #question #smt
Quantifying the SMT Layout Overhead — Does SMT Pull Its Weight? (JB, JLG), pp. 109–120.
DACDAC-1999-BalasaL #layout #representation #using
Module Placement for Analog Layout Using the Sequence-Pair Representation (FB, KL), pp. 274–279.
DACDAC-1999-KhatriMBOS #layout #novel
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications (SPK, AM, RKB, RHJMO, ALSV), pp. 491–496.
DACDAC-1999-MukherjeeSML #layout #novel #synthesis
Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique (AM, RS, MMS, SIL), pp. 466–471.
DACDAC-1999-YehKSW #design #layout
Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs (CWY, YSK, SJS, JSW), pp. 62–67.
DATEDATE-1999-ToulouseBLN #3d #modelling #performance
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts (AT, DB, CL, PN), pp. 576–580.
ICDARICDAR-1999-Hobby #classification #composition #geometry #layout
Page Decomposition and Signature Finding via Shape Classification and Geometric Layout (JDH), pp. 555–558.
ICDARICDAR-1999-HuKW #classification #comparison #documentation #image #layout
Document Image Layout Comparison and Classification (JH, RSK, GTW), pp. 285–288.
ICDARICDAR-1999-KlinkJ #named
MergeLayouts: Overcoming Faulty Segmentations by a Comprehensive Voting of Commercial OCR Devices (SK, TJ), pp. 386–389.
PLDIPLDI-1999-ChilimbiHL #layout
Cache-Conscious Structure Layout (TMC, MDH, JRL), pp. 1–12.
STOCSTOC-1999-MuthukrishnanPSS #grid #multi #network
Compact Grid Layouts of Multi-Level Networks (SM, MP, SCS, TS), pp. 455–463.
HCIHCI-CCAD-1999-Stempfhuber #layout #user interface #visual notation
Dynamic spatial layout in graphical user interfaces (MS), pp. 137–141.
OOPSLAOOPSLA-1999-SweeneyG #inheritance #layout #memory management #multi
Space and Time-Efficient Memory Layout for Multiple Inheritance (PFS, JYG), pp. 256–275.
ICSEICSE-1999-HolderBG #distributed #layout
Dynamic Layout of Distributed Applications in FarGo (OH, IBS, HG), pp. 163–173.
HPCAHPCA-1999-SchwarzSB #development #layout #permutation
Permutation Development Data Layout (PDDL) (TJES, JS, WAB), pp. 214–217.
DACDAC-1998-IenneG #case study #design #experience #question #standard #tool support
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? (PI, AG), pp. 396–401.
DACDAC-1998-KrauterM #analysis #layout
Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis (BK, SM), pp. 303–308.
DACDAC-1998-LiK #layout #verification
Layout Extraction and Verification Methodology CMOS I/O Circuits (TL, SMK), pp. 291–296.
DACDAC-1998-MassoudMBW #layout
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance (YM, SSM, TB, JW), pp. 566–571.
DATEDATE-1998-ArsintescuO #constraints #layout
Constraints Space Management for the Layout of Analog IC’s (BGA, RHJMO), pp. 971–972.
DATEDATE-1998-PrietoRGPHR #approach #design #fault #layout #predict #testing
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.
DATEDATE-1998-XuK #architecture #synthesis
Layout-Driven High Level Synthesis for FPGA Based Architectures (MX, FJK), pp. 446–450.
ICPRICPR-1998-TingL #layout #linear
Linear layout processing (AT, MKHL), pp. 403–405.
DACDAC-1997-GuptaH #2d #generative #layout #named #optimisation
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells (AG, JPH), pp. 452–455.
DACDAC-1997-GuruswamyMDRCFJ #automation #layout #library #named #standard #synthesis
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries (MG, RLM, DD, SR, VC, AF, LGJ), pp. 327–332.
DACDAC-1997-JiangKCM #logic #optimisation #performance
Post-Layout Logic Restructuring for Performance Optimization (YMJ, AK, KTC, MMS), pp. 662–665.
DACDAC-1997-KimK #algorithm #design #layout #performance
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design (JK, SMK), pp. 456–459.
DACDAC-1997-Lakos #layout
Technology Retargeting for IC Layout (JL), pp. 460–465.
DACDAC-1997-MurofushiIMM #layout #power management
Layout Driven Re-synthesis for Low Power Consumption LSIs (MM, TI, MM, TM), pp. 666–669.
DATEEDTC-1997-LangDG #automation #design #modelling #parametricity #top-down
Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems (ML, DD, MG), pp. 200–204.
DATEEDTC-1997-SeongK #clustering #design #layout
Two-way partitioning based on direction vector [layout design] (KSS, CMK), pp. 306–310.
DATEEDTC-1997-WalczowskiNWS #generative #layout #web
Analogue layout generation by World Wide Web server-based agents (LTW, DN, WAJW, KHS), pp. 384–388.
DATEEDTC-1997-WolfK #generative #independence
Application independent module generation in analog layouts (MW, UK), p. 624.
ICDARICDAR-1997-HurstD #layout
Layout and Language: Preliminary Investigations in Recognizing the Structure of Tables (MH, SD), pp. 1043–1047.
ICDARICDAR-1997-Ishitani #analysis #documentation #layout
Document Layout Analysis Based on Emergent Computation (YI), pp. 45–50.
ICDARICDAR-1997-WatanabeH #automation #comprehension #layout
Automatic Acquisition of Layout Knowledge for Understanding Business Cards (TW, XH), pp. 216–220.
ICALPICALP-1997-EilamFZ #layout #network #problem
A Complete Characterization of the Path Layout Construction Problem for ATM Networks with Given Hop Count and Load (Extended Abstract) (TE, MF, SZ), pp. 527–537.
RERE-1997-DarimontDML #analysis #integration #layout #named #requirements
GRAIL/KAOS: An Environment for Goal-Driven Requirements Analysis, Integration and Layout (RD, ED, PM, AvL), p. 140.
DACDAC-1996-ChenLH #layout
Layout Driven Selecting and Chaining of Partial Scan (CSC, KHL, TH), pp. 262–267.
DACDAC-1996-SatoKEM #design #optimisation
Post-Layout Optimization for Deep Submicron Design (KS, MK, HE, NM), pp. 740–745.
DACDAC-1996-WunderLM #concept #layout #modelling #named #simulation
VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems (BW, GL, KDMG), pp. 119–124.
STOCSTOC-1996-AggarwalKW #layout #trade-off
Node-Disjoint Paths on the Mesh and a New Trade-Off in VLSI Layout (AA, JMK, DPW), pp. 585–594.
ICPRICPR-1996-NakajimaTKY #analysis #layout #process #verification
Analysis of address layout on Japanese handwritten mail-a hierarchical process of hypothesis verification (NN, TT, TK, KY), pp. 726–731.
SEKESEKE-1996-OrjiN #interactive #layout #on-demand
Data Layout for Interactive Video-on-Demand Storage Systems (CUO, KCN), pp. 285–292.
DACDAC-1995-GeloshS #layout #modelling #performance #tool support
Deriving Efficient Area and Delay Estimates by Modeling Layout Tools (DSG, DES), pp. 402–407.
DACDAC-1995-HagenHK #heuristic #layout #quantifier
Quantified Suboptimality of VLSI Layout Heuristics (LWH, DJHH, ABK), pp. 216–221.
DACDAC-1995-RekhiTL #automation #layout #synthesis
Automatic Layout Synthesis of Leaf Cells (SR, JDT, DHL), pp. 267–272.
ICDARICDAR-v1-1995-EspositoMS #analysis #approach #knowledge-based #layout
A knowledge-based approach to the layout analysis (FE, DM, GS), pp. 466–471.
ICDARICDAR-v1-1995-LefevreR #documentation #layout #named
ODIL: an SGML description language of the layout structure of documents (PL, FR), pp. 480–488.
ICDARICDAR-v2-1995-AzoklyI #documentation #layout #segmentation
A language for document generic layout description and its use for segmentation into regions (AA, RI), pp. 1123–1126.
ICDARICDAR-v2-1995-Liu-GongDP #analysis #documentation #layout #recognition
A general analysis system for document’s layout structure recognition (YHLG, BD, HNP), pp. 597–600.
PLDIPLDI-1995-ColemanM #layout #using
Tile Size Selection Using Cache Organization and Data Layout (SC, KSM), pp. 279–290.
CHICHI-1995-ShipmanMM #using
Finding and Using Implicit Structure in Human-Organized Spatial Layouts of Information (FMSI, CCM, TPM), pp. 346–353.
OOPSLAOOPSLA-1995-Myers #bidirectional #compilation #layout
Bidirectional Object Layout for Separate Compilation (ACM), pp. 124–139.
DACDAC-1994-ChangCWM #layout #logic #synthesis
Layout Driven Logic Synthesis for FPGAs (SCC, KTC, NSW, MMS), pp. 308–313.
DATEEDAC-1994-AhmadM #automation #layout #named #reasoning
AREAL: Automated Reasoning Expert for Analogue Layout (HHA, RJM), p. 659.
DACDAC-1993-DaoMHOM
A Compaction Method for Full Chip VLSI Layouts (JD, NM, TH, CO, SM), pp. 407–412.
DACDAC-1993-MogakiSKH #approach #layout
Cooperative Approach to a Practical Analog LSI Layout System (MM, YS, MK, TH), pp. 544–549.
DACDAC-1993-NouraniP #algorithm #estimation #layout
A Layout Estimation Algorithm for RTL Datapaths (MN, CAP), pp. 285–291.
DACDAC-1993-PanDL #constraints #graph #layout #reduction
Optimal Graph Constraint Reduction for Symbolic Layout Compaction (PP, SkD, CLL), pp. 401–406.
DACDAC-1993-WanG #layout #named
ABLE: AMD Backplane for Layout Engines (KWW, RAG), pp. 556–560.
ICDARICDAR-1993-Conway #approach #documentation #layout #parsing #recognition
Page grammars and page parsing. A syntactic approach to document layout recognition (AC), pp. 761–764.
ICDARICDAR-1993-HaoWN #analysis #approach #classification #documentation #layout #segmentation
Nested segmentation: an approach for layout analysis in document classification (XH, JTLW, PAN), pp. 319–322.
ICDARICDAR-1993-HerrmannS #documentation #image #layout #retrieval #using
Retrieval of document images using layout knowledge (PH, GS), pp. 537–540.
ICDARICDAR-1993-IttnerB #analysis #layout
Language-free layout analysis (DJI, HSB), pp. 336–340.
ICDARICDAR-1993-IwaneYI #analysis #approach #classification #documentation #functional #image #layout
A functional classification approach to layout analysis of document images (KI, MY, OI), pp. 778–781.
ICDARICDAR-1993-KiseYBF #documentation #incremental #layout
Incremental acquisition of knowledge about layout structures from examples of documents (KK, NY, NB, KF), pp. 668–671.
ICDARICDAR-1993-WieserP #analysis #image #layout
Layout and analysis: Finding text, titles, and photos in digital images of newspaper pages (JW, AP), pp. 774–777.
HCIHCI-SHI-1993-Graf #constraints #layout #multi #named
LAYLAB — A Constraint-Based Layout Manager for Multimedia Presentations (WG), pp. 446–451.
HCIHCI-SHI-1993-HerrmannK #layout
Supporting Instead of Replacing the Planner — An Intelligent Assistant System for Factory Layout Planning (JH, MK), pp. 796–801.
HCIHCI-SHI-1993-LinLC #layout #process
Intelligent Keyboard Layout Process (CCL, TZL, FSC), pp. 1070–1074.
HCIHCI-SHI-1993-ZhanBR #design #layout #semantics
Screen Layout and Semantic Structure in Iconic Menu Design (PZ, RRB, MWR), pp. 146–151.
CHIINTERCHI-1993-HudsonH #approach #independence #specification
A synergistic approach to specifying simple number independent layouts by example (SEH, CNH), pp. 285–292.
DACDAC-1992-Frankle #adaptation #layout
Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing (JF), pp. 536–542.
DACDAC-1992-KimLS #graph #layout #modelling #using
A New Hierarchical Layout Compactor Using Simplified Graph Models (WK, JL, HS), pp. 323–326.
DACDAC-1992-LiaoC #layout #synthesis
Routing Considerations in Symbolic Layout Synthesis (YL, SC), pp. 682–686.
DACDAC-1992-OkudaO #algorithm #generative #layout #performance
An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style (RO, SO), pp. 676–681.
SEKESEKE-1992-SugiharaYM #automation #diagrams #layout #specification
Automatic Layout of Diagrams for Software Specification (KS, KY, IM), pp. 245–252.
SEKESEKE-1992-TaT #algorithm #layout
Layout Algorithms for DFD Processors (KPT, TCT), pp. 567–573.
DACDAC-1991-BenkoskiS #layout #synthesis #verification
The Role of Timing Verification in Layout Synthesis (JB, AJS), pp. 612–619.
DACDAC-1991-Gad-El-KarimG #generative #layout #performance
Generation of Performance Sensitivities for Analog Cell Layout (GGEK, RSG), pp. 500–505.
DACDAC-1991-Harrison #layout #using
VLSI Layout Compaction Using Radix Priority Search Trees (AJH), pp. 732–735.
DACDAC-1991-HwangHLH #automation #generative #layout #performance
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation (CYH, YCH, YLL, YCH), pp. 481–486.
DACDAC-1991-Kozminski #benchmark #evolution #layout #metric #synthesis
Benchmarks for Layout Synthesis — Evolution and Current Status (KK), pp. 265–270.
DACDAC-1991-Luk #constraints #generative #layout #performance #physics
A Fast Physical Constraint Generator for Timing Driven Layout (WKL), pp. 626–631.
DACDAC-1991-MogakiKSY #constraints #layout
A Layout Improvement Method Based on Constraint Propagation for Analog LSI’s (MM, NK, NS, YY), pp. 510–513.
DACDAC-1991-OnoderaTT #bound #layout
Branch-and-Bound Placement for Building Block Layout (HO, YT, KT), pp. 433–439.
DACDAC-1991-PedramB #layout
Layout Driven Technology Mapping (MP, NBB), pp. 99–105.
DACDAC-1991-Wang #layout #novel
Novel Routing Schemes for IC Layout, Part I: Two-Layer Channel Routing (DCW), pp. 49–53.
HTHT-1991-KaltenbachRF #hypermedia
Screen Management in Hypertext Systems with Rubber Sheet Layouts (MK, FR, CF), pp. 91–105.
ICLPICLP-1991-WatanabeK #layout #parallel #problem
Co-operative Hierarchical Layout Problem Solver on Parallel Inference Machine (TW, KK), p. 892.
DACDAC-1990-BowerSW #framework #generative #industrial #layout
A Framework for Industrial Layout Generators (WB, CS, WW), pp. 419–424.
DACDAC-1990-CaiNSM #assembly #layout #performance
A Data Path Layout Assembler for High Performance DSP Circuits (HC, SN, PS, HDM), pp. 306–311.
DACDAC-1990-CaiW #algorithm #layout
A Channel/Switchbox Definition Algorithm for Building-Block Layout (YC, DFW), pp. 638–641.
DACDAC-1990-Domic #layout #synthesis
Layout Synthesis of MOS Digital Cells (AD), pp. 241–245.
DACDAC-1990-EdahiroY #algorithm #standard
New Placement and Global Routing Algorithms for Standard Cell Layouts (ME, TY), pp. 642–645.
DACDAC-1990-Hojati #layout #optimisation
Layout Optimization by Pattern Modification (RH), pp. 632–637.
DACDAC-1990-HsiehHLH #generative #layout #named
LiB: A Cell Layout Generator (YCH, CYH, YLL, YCH), pp. 474–479.
DACDAC-1990-MatsumotoWUSHM #generative #layout
Datapath Generator Based on Gate-Level Symbolic Layout (NM, YW, KU, YS, HH, SM), pp. 388–393.
DACDAC-1990-Onozawa #constraints #layout
Layout Compaction with Attractive and Repulsive Constraints (AO), pp. 369–374.
DACDAC-1990-SaabR #effectiveness #evolution #heuristic #layout #performance #probability #problem
Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems (YS, VBR), pp. 26–31.
DACDAC-1990-SinghC #layout #matrix #order
A Transistor Reordering Technique for Gate Matrix Layout (US, CYRC), pp. 462–467.
DACDAC-1990-SutanthavibulS #adaptation #layout
An Adaptive Timing-Driven Layout for High Speed VLSI (SS, ES), pp. 90–95.
DACDAC-1990-TeraiTS #algorithm #assurance #constraints #design #layout
A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint (MT, KT, KS), pp. 96–102.
DACDAC-1990-Wang #layout
Pad Placement and Ring Routing for Custom Chip Layout (DCW), pp. 193–199.
PLDIPLDI-1990-PughW #inheritance #layout #multi
Two-Directional Record Layout for Multiple Inheritance (WP, GEW), pp. 85–91.
ICGTGG-1990-Brandenburg #approach #graph grammar #layout
Layout Graph Grammars: The Placement Approach (FJB), pp. 144–156.
CHICHI-1990-BohringerP #algorithm #automation #constraints #graph #layout #using
Using constraints to achieve stability in automatic graph layout algorithms (KFB, FNP), pp. 43–51.
DACDAC-1989-AdamsS #generative #layout
Template Style Considerations for Sea-of-Gates Layout Generation (GDA, CHS), pp. 31–36.
DACDAC-1989-ChenC #automation #layout
The Layout Synthesizer: An Automatic Netlist-to-Layout System (CCC, SLC), pp. 232–238.
DACDAC-1989-HedenstiernaJ #design #layout
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking (NH, KOJ), pp. 508–512.
DACDAC-1989-IrwinO #2d #comparison #layout #matrix #tool support
A Comparison of Four Two-dimensional Gate Matrix Layout Tools (MJI, RMO), pp. 698–701.
DACDAC-1989-JustSK #named
Plowing: Modifying Cells and Routing 45: 9D — Layouts (KMJ, WLS, TK), pp. 702–705.
DACDAC-1989-LinDY #2d #layout #matrix #synthesis
Gate Matrix Layout Synthesis with Two-Dimensional Folding (IL, DHCD, SHCY), pp. 37–42.
DACDAC-1989-Lo #automation #generative #layout
Automatic Tub Region Generation for Symbolic Layout Compaction (CYL), pp. 302–306.
DACDAC-1989-LukD #layout #multi #optimisation
Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout (WKL, AAD), pp. 110–115.
DACDAC-1989-Marple #layout #optimisation
Transistor Size Optimization in the Tailor Layout System (DM), pp. 43–48.
DACDAC-1989-MilsomSCMAS #layout #named #simulation
FACET: A CAE System for RF Analogue Simulation Including Layout (RFM, KJS, SGC, JCM, SA, FNS), pp. 622–625.
DACDAC-1989-PreasPC #automation #hybrid #layout
Automatic Layout of Silicon-on-Silicon Hybrid Packages (BP, MP, DC), pp. 394–399.
DACDAC-1989-ShinL #2d #algorithm #layout #performance
An Efficient Two-Dimensional Layout Compaction Algorithm (HS, CYL), pp. 290–295.
DACDAC-1989-TheWC #layout
VIA Minimization by Layout Modification (KST, DFW, JC), pp. 799–802.
DACDAC-1989-TrickD #behaviour #layout #named #synthesis #tool support
LASSIE: Structure to Layout for Behavioral Synthesis Tools (MTT, SWD), pp. 104–109.
DACDAC-1989-WaterkampWBRS #layout
Technology Tracking of Non Manhattan VLSI Layout (JW, RW, RB, MR, GS), pp. 296–301.
DACDAC-1989-WeninVCLG #layout #rule-based #verification
Rule-based VLSI Verification System Constrained by Layout Parasitics (JW, JV, MVC, JL, PG), pp. 662–667.
CHICHI-1989-IwaiDYFT #architecture #automation #documentation #layout #using
A document layout system using automatic document architecture extraction (II, MD, KY, MF, YT), pp. 369–374.
DACDAC-1988-BaltusA #generative #named #performance
SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit Schematics (DGB, JA), pp. 445–452.
DACDAC-1988-BarthMS #layout #named
Patchwork: Layout from Schematic Annotations (RB, LM, BS), pp. 250–255.
DACDAC-1988-Boyer #bibliography #layout #perspective
Symbolic Layout Compaction Review (DGB), pp. 383–389.
DACDAC-1988-Cai88a #layout
Connectivity Biased Channel Construction and Ordering for Building-Block Layout (HC), pp. 560–565.
DACDAC-1988-ChenB #layout
A Module Area Estimator for VLSI Layout (XC, MLB), pp. 54–59.
DACDAC-1988-HenkelG #layout #named #set #verification
RISCE — A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification (VH, UG), pp. 465–470.
DACDAC-1988-MarpleSH #layout #performance
An Efficient Compactor for 45° Layout (DM, MS, HH), pp. 396–402.
DACDAC-1988-ObermeierK #layout #physics
An Electrical Optimizer that Considers Physical Layout (FWO, RHK), pp. 453–459.
DACDAC-1988-OgawaTK #automation #layout
Automatic Layout Procedures for Serial Routing Devices (YO, HT, TK), pp. 642–645.
DACDAC-1988-Zimmerman #estimation
A New Area and Shape Function Estimation Technique for VLSI Layouts (GZ), pp. 60–65.
DACDAC-1987-ApteK #layout #standard
Strip Layout: A New Layout Methodology for Standard Circuit Modules (JA, GK), pp. 363–369.
DACDAC-1987-ChangCH #approach #automation #generative #layout #matrix #using
Automated Layout Generation Using Gate Matrix Approach (YCC, SCC, LHH), pp. 552–558.
DACDAC-1987-DaiSK #layout #performance #representation
A Dynamic and Efficient Representation of Building-Block Layout (WWMD, MS, ESK), pp. 376–384.
DACDAC-1987-Elias #case study #compilation #generative #layout #re-engineering
A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator (NJE), pp. 82–88.
DACDAC-1987-Koeppe #fault #layout
Optimal Layout to Avoid CMOS Stuck-Open Faults (SK), pp. 829–835.
DACDAC-1987-LinG #layout #named
LES: A Layout Expert System (YLSL, DG), pp. 672–678.
DACDAC-1987-LueM #game studies #layout #named
PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement (WJL, LPM), pp. 659–665.
DACDAC-1987-MaiaszH #functional #layout #optimisation
Layout Optimization of CMOS Functional Cells (RLM, JPH), pp. 544–551.
DACDAC-1987-MinaiWB #approach #evaluation #heuristic #predict
A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts (AAM, RDW, FWB), pp. 770–776.
DACDAC-1987-NaclerieMN
Via Minimization for Gridless Layouts (NJN, SM, KN), pp. 159–165.
DACDAC-1987-Preas #benchmark #layout #metric
Benchmarks for Cell-Based Layout Systems (BP), pp. 319–320.
DACDAC-1986-BootehsazC #approach #independence #layout
A technology independent approach to hierarchical IC layout extraction (AB, RAC), pp. 425–431.
DACDAC-1986-ClarkeF #geometry #layout #named #recursion
Escher — a geometrical layout system for recursively defined circuits (EMC, YF), pp. 650–653.
DACDAC-1986-DeJesusCW #layout #named #power management
PEARL: an expert system for power supply layout (EJD, JPC, CRW), pp. 615–621.
DACDAC-1986-FreemanKLN #automation #layout #matrix #modelling
Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning (RDF, SMK, CGLH, MLN), pp. 418–424.
DACDAC-1986-FrisonG #editing #layout #metaprogramming #named
MADMACS: a new VLSI layout macro editor (PF, EG), pp. 654–658.
DACDAC-1986-Hartoog #analysis #layout #standard
Analysis of placement procedures for VLSI standard cell layout (MRH), pp. 314–319.
DACDAC-1986-JustKJ #layout #on the #problem #standard
On the relative placement and the transportation problem for standard-cell layout (KMJ, JMK, FMJ), pp. 308–313.
DACDAC-1986-KrekelbergSSL #automation #compilation #layout #synthesis
Automated layout synthesis in the YASC silicon compiler (DEK, ES, GES, LSL), pp. 447–453.
DACDAC-1986-LinA #bound #layout #named
Minplex — a compactor that minimizes the bounding rectangle and individual rectangles in a layout (SLL, JA), pp. 123–130.
DACDAC-1986-Szepieniec #slicing
Integrated placement/routing in sliced layouts (AAS), pp. 300–307.
DACDAC-1986-VenkataramanW #automation #layout #named
GEMS: an automatic layout tool for MIMOLA schematics (VVV, CDW), pp. 131–137.
DACDAC-1985-AnwayFR #layout
PLINT layout system for VLSI chips (HA, GF, RR), pp. 449–452.
DACDAC-1985-BursteinY #design #layout
Timing influenced layout design (MB, MNY), pp. 124–130.
DACDAC-1985-ChuL #design #layout #tool support
Technology tracking for VLSI layout design tools (KCC, YEL), pp. 279–285.
DACDAC-1985-Cory #layout #named
Layla: a VLSI layout language (WEC), pp. 245–251.
DACDAC-1985-HsuTCPT #layout #named #standard
ALPS2: a standard cell layout system for double-layer metal technology (CPH, BNT, KC, RAP, JT), pp. 443–448.
DACDAC-1985-Marek-Sadowska #2d #layout
Two-dimensional router for double layer layout (MMS), pp. 117–123.
DACDAC-1985-Mata #named #specification
ALLENDE: a procedural language for the hierarchical specification of VLSI layouts (JMdM), pp. 183–189.
DACDAC-1985-NgJ #approach #generative #graph
Generation of layouts from MOS circuit schematics: a graph theoretic approach (TKN, SLJ), pp. 39–45.
DACDAC-1985-NodaYFKKF #algorithm #array #automation #layout
Automatic layout algorithms for function blocks of CMOS gate arrays (SN, HY, EF, HK, HK, TF), pp. 46–52.
DACDAC-1985-Rosenberg #layout
Auto-interactive schematics to layout translation (JBR), pp. 82–87.
DACDAC-1985-SaucierT #layout
Systematic and optimized layout of MOS cells (GS, GT), pp. 53–61.
DACDAC-1985-SpiraH #array #hardware #layout
Hardware acceleration of gate array layout (PMS, CH), pp. 359–366.
DACDAC-1985-TaylorBS #design #layout #lessons learnt #tutorial
Layout design-lessons from the Jedi designer (tutorial session) (SLT, RB, TS), p. 337.
STOCSTOC-1985-LeisersonM #algorithm #testing
Algorithms for Routing and Testing Routability of Planar VLSI Layouts (CEL, FMM), pp. 69–78.
DACDAC-1984-ChenK #design #layout #problem
The channel expansion problem in layout design (RRC, YK), pp. 388–391.
DACDAC-1984-DunlopADJKW #layout #optimisation #using
Chip layout optimization using critical path weighting (AED, VDA, DND, MFJ, PK, MW), pp. 133–136.
DACDAC-1984-KozawaMT #algorithm #layout #logic #top-down
Combine and top down block placement algorithm for hierarchical logic VLSI layout (TK, CM, HT), pp. 667–669.
DACDAC-1984-LotvinJG #layout #named
Amoeba: A symbolic VLSI layout system (ML, BJ, RG), pp. 294–300.
DACDAC-1984-Marvik #layout #verification
A method for IC layout verification (OAM), pp. 708–709.
DACDAC-1984-Mori #interactive #layout
Interactive compaction router for VLSI layout (HM), pp. 137–143.
DACDAC-1984-OusterhoutHMST #layout #named
Magic: A VLSI layout system (JKO, GTH, RNM, WSS, GST), pp. 152–159.
DACDAC-1984-OzakiWKIS #layout #named
MGX: An integrated symbolic layout system for VLSI (MO, MW, MK, MI, KS), pp. 572–579.
DACDAC-1984-Smith #layout #tool support #what
Basic turorial layout tools — what really is there (RS), p. 219.
DACDAC-1984-TienTCCE #array #automation #layout #named
GALA — an automatic layout system for high density CMOS gate arrays (BNT, BST, JC, KSKC, SCE), pp. 657–662.
DACDAC-1984-Wagner #layout #verification
Hierarchical layout verification (TJW), pp. 484–489.
DACDAC-1984-WieclawskiP #compilation #layout #network #optimisation
Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler (AW, MAP), pp. 703–704.
STOCSTOC-1984-Blum #layout #trade-off
An Area-Maximum Edge Length Tradeoff for VLSI Layout (NB), pp. 92–97.
DACDAC-1983-Barke #layout #verification
A layout verification system for analog bipolar integrated circuits (EB), pp. 353–359.
DACDAC-1983-KedemW #layout
Graph-optimization techniques for IC layout and compaction (GK, HW), pp. 113–120.
DACDAC-1983-LiaoW #algorithm #constraints #layout
An algorithm to compact a VLSI symbolic layout with mixed constraints (YZL, CKW), pp. 107–112.
DACDAC-1983-MayoO #layout
Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool (RNM, JKO), pp. 270–276.
DACDAC-1983-Robinson #array #automation #layout
Automatic layout for gate arrays with one layer of metal (PR0), pp. 658–664.
DACDAC-1983-Smith #independence #layout
Technology-independent circuit layout (RJSI), pp. 390–393.
DACDAC-1983-SmithNBSW #array #automation #geometry #layout #named
VGAUA: The Variable Geometry Automated Universal Array layout System (DCS, RN, FB, SSS, JCW), pp. 425–429.
DACDAC-1983-Supowit #layout #standard
Reducing channel density in standard cell layout (KJS), pp. 263–269.
DACDAC-1983-TamuraON #analysis #layout
Path delay analysis for hierarchical building block layout system (ET, KO, TN), pp. 403–410.
ICALPICALP-1983-MakedonS #linear
Minimizing Width in Linear Layouts (FM, IHS), pp. 478–490.
DACDAC-1982-AdachiKNS #design #layout #top-down
Hierarchical top-down layout design method for VLSI chip (TA, HK, MN, TS), pp. 785–791.
DACDAC-1982-ArnoldO #approach #geometry #layout #named
Lyra: A new approach to geometric layout rule checking (MHA, JKO), pp. 530–536.
DACDAC-1982-BeylsHLMP #design #layout #tool support
A design methodology based upon symbolic layout and integrated cad tools (AMB, BH, JL, GM, AP), pp. 872–878.
DACDAC-1982-Hassett #approach #automation #layout #problem
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI (JEH), pp. 777–784.
DACDAC-1982-InoueAF #design #layout #precise
A layout system for high precision design of progressive die (KI, MA, TF), pp. 246–252.
DACDAC-1982-KangKL #adaptation #cpu #design #evolution #layout #logic #matrix #random
Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design (SMK, RHK, HFSL), pp. 170–174.
DACDAC-1982-LieH #layout
A bus router for IC layout (ML, CSH), pp. 129–132.
DACDAC-1982-LiptonNSVV #named
ALI: A procedural language to describe VLSI layouts (RJL, SCN, RS, JV, GV), pp. 467–474.
DACDAC-1982-LuhukayK #layout #synthesis
A layout synthesis system for NMOS gate-cells (JFPL, WJK), pp. 307–314.
DACDAC-1982-MatsudaFTMNKG #design #layout #low cost #named
LAMBDA: A quick, low cost layout design system for master-slice LSI s (TM, TF, KT, HM, HN, FK, SG), pp. 802–808.
DACDAC-1982-MudgeRLA #image #layout #validation
Cellular image processing techniques for VLSI circuit layout validation and routing (TNM, RAR, RML, DEA), pp. 537–543.
DACDAC-1982-TeraiKSY #layout
A consideration of the number of horizontal grids used in the routing of a masterslice layout (MT, HK, KS, TY), pp. 121–128.
DACDAC-1982-ToddHPBGAB #array #layout #multi
CGALA-a multi technology Gate Array Layout system (LFT, JMH, SVP, JLB, DJG, RJA, AKB), pp. 792–801.
DACDAC-1982-WipflerWM #algorithm #layout
A combined force and cut algorithm for hierarchical VLSI layout (GJW, MW, DAM), pp. 671–677.
STOCSTOC-1982-Leighton #layout
A Layout Strategy for VLSI which Is Provably Good (Extended Abstract) (FTL), pp. 85–98.
DACDAC-1981-AblasserJ #layout #recognition #verification
Circuit recognition and verification based on layout information (IA, UJ), pp. 684–689.
DACDAC-1981-BradyS #layout #optimisation #verification
Verification and optimization for LSI & PCB layout (HNB, RJSI), pp. 365–371.
DACDAC-1981-ChibaOKNIK #layout #named
SHARPS: A hierarchical layout system for VLSI (TC, NO, TK, IN, TI, SK), pp. 820–827.
DACDAC-1981-EdmondsonJ #layout #low cost #verification
A low cost hierarchical system for VLSI layout and verification (THE, RMJ), pp. 505–510.
DACDAC-1981-GoatesP #array #design #layout #lisp #logic #modelling #named
ABLE: A LISP-based layout modeling language with user-definable procedural models for storage/logic array design (GBG, SSP), pp. 322–329.
DACDAC-1981-HorngL #automation #interactive #layout
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks (CSH, ML), pp. 293–300.
DACDAC-1981-PerskyES #automation #layout
The Hughes Automated Layout System — automated LSI/VLSI layout based on channel routing (GP, CE, DMS), pp. 22–28.
DACDAC-1981-RothermelM #layout #power management
Computation of power supply nets in VLSI layout (HJR, DAM), pp. 37–42.
DACDAC-1981-SatoNTSOY #layout #named
MILD — A cell-based layout system for MOS-LSI (KS, TN, MT, HS, MO, TY), pp. 828–836.
DACDAC-1981-TanakaMTYOTKT #array #design #layout
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 (CT, SM, HT, TY, KO, MT, RK, MT), pp. 812–819.
DACDAC-1981-Trimberger #interactive #layout
Combining graphics and a layout language in a single interactive system (ST), pp. 234–239.
DACDAC-1981-Weste #grid #layout
Virtual grid symbolic layout (NW), pp. 225–233.
DACDAC-1981-Williams #automation #layout #verification
Automatic VLSI layout verification (LW), pp. 726–732.
STOCSTOC-1981-KleitmanLLM #graph
New Layouts for the Shuffle-Exchange Graph (Extended Abstract) (DJK, FTL, ML, GLM), pp. 278–292.
DACDAC-1980-ChaoHY #approach #consistency #layout
A hierarchical approach for layout versus circuit consistency check (SPC, YSH, LMY), p. 269.
DACDAC-1980-ChaoHY80a #approach #consistency #layout
A hierarchical approach for layout versus circuit consistency check (SPC, YSH, LMY), pp. 270–276.
DACDAC-1980-Dunlop
SLIM-the translation of symbolic layouts into mask data (AED), pp. 595–602.
DACDAC-1980-McGrathW #design #layout #verification
Design integrity and immunity checking: A new look at layout verification and design rule checking (EJM, TW), pp. 263–268.
DACDAC-1980-ShirakawaOHTO #layout #logic #random
A layout system for the random logic portion of MOS LSI (IS, NO, TH, ST, HO), pp. 92–99.
DACDAC-1980-SoukupR #layout #representation
Cell map representation for hierarchical layout (JS, JR), pp. 591–594.
DACDAC-1980-SzepieniecO #approach #layout #problem
The genealogical approach to the layout problem (AAS, RHJMO), pp. 535–542.
STOCSTOC-1980-FischerP #layout
Optimal Tree Layout (Preliminary Version) (MJF, MP), pp. 177–189.
DACDAC-1979-BekeS #automation #interactive #layout #named
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI (HB, WS), pp. 102–108.
DACDAC-1979-Chang #layout #recognition #using
LSI layout checking using bipolar device recognition technique (CSC), pp. 95–101.
DACDAC-1979-Goto #2d #algorithm #layout #problem #slicing
A two-dimensional placement algorithm for the master slice LSI layout problem (SG), pp. 11–17.
DACDAC-1979-Johnson79a #layout
PC board layout techniques (DRJ), pp. 337–343.
DACDAC-1979-KawamotoK
The minimum width routing of A 2-row 2-layer polycell-layout (TK, YK), pp. 290–296.
DACDAC-1979-Rath
Hughes S&CG custom LSI layouts — “we did it our way” (RRR), pp. 392–397.
DACDAC-1979-SaharaKN #interactive #layout
An interactive layout system of analog printed wiring boards (KiS, KiK, IN), pp. 506–512.
DACDAC-1979-SatoNSY #design #layout #named
MIRAGE — a simple-model routing program for the hierarchical layout design of IC masks (KS, TN, HS, TY), pp. 297–304.
DACDAC-1979-UeharaC #array #functional #layout
Optimal layout of CMOS functional arrays (TU, WMvC), pp. 287–289.
DACDAC-1979-Wilmore #database #design #interactive #layout #performance
The design of an efficient data base to support an interactive LSI layout system (JAW), pp. 445–451.
DACDAC-1978-BayeganA #design #editing #interactive #layout #logic #simulation
An integrated system for interactive editing of schematics, logic simulation and PCB layout design (HMB, EJA), pp. 1–8.
DACDAC-1978-FairbairnR #interactive #layout #named
ICARUS: An interactive integrated circuit layout program (DGF, JAR), pp. 188–192.
DACDAC-1978-PreasG #automation #layout
Methods for hierarchical automatic layout of custom LSI circuit masks (BP, CWG), pp. 206–212.
DACDAC-1978-Ruch #approach #graph #interactive #layout
Interactive space layout: A graph theoretical approach (JR), pp. 152–157.
DACDAC-1977-BedardFSS #layout
A production PCB layout system on a minicomputer (KB, SF, BS, US), pp. 168–173.
DACDAC-1977-ChenFKNS #automation #layout #problem
The chip layout problem: An automatic wiring procedure (KAC, MF, KHK, NN, SS), pp. 298–302.
DACDAC-1977-ChoKS #approach #automation #design #layout #named
Floss: An approach to automated layout for high-volume designs (YEC, AJK, DES), pp. 138–141.
DACDAC-1977-KhokhaniP #layout #problem
The chip layout problem: A placement procedure for lsi (KHK, AMP), pp. 291–297.
DACDAC-1977-Larsen #effectiveness #layout
Cost effective layout digitizing and mask pen plotting of custom microelectronic devices (RPL), pp. 386–390.
DACDAC-1977-NishiokaKN #automation #layout
A minicomputerized automatic layout system for two-layer printed wiring boards (IN, TK, HN), pp. 1–11.
DACDAC-1977-YoshidaMNCON #layout #scalability
A layout checking system for large scale integrated circuits (KY, TM, YN, TC, KO, SN), pp. 322–330.
DACDAC-1976-Cleemput #aspect-oriented #layout #on the #problem
On the topological aspects of the circuit layout problem (WMvC), pp. 441–450.
DACDAC-1976-Feller #automation #layout #low cost
Automatic layout of low-cost quick-turnaround random-logic custom LSI devices (AF), pp. 79–85.
DACDAC-1976-GibsonN #layout #named
SLIC — Symbolic Layout of Integrated Circuits (DG, SN), pp. 434–440.
DACDAC-1976-Persky #automation #layout #named #string
PRO — an automatic string placement program for polycell layout (GP), pp. 417–424.
DACDAC-1976-RabideauF #interactive #layout
Interactive graphics package for human engineering and layout of vehicle workspace (GFR, JF), pp. 34–41.
DACDAC-1976-Schweikert #2d #algorithm #layout
A 2-dimensional placement algorithm for the layout of electrical circuits (DGS), pp. 408–416.
DACDAC-1975-ChienSTR #design #layout
A computer-aided minimum cost transfer machine layout design (TTC, SS, WAT, PR), pp. 202–209.
DACDAC-1975-GiuglianoB #automation #design #layout
Present and future on P.C.B. layout design automation system at SIT-Siemens (AG, FB), pp. 134–143.
DACDAC-1975-Valle #layout #relational
Relational data handling techniques in integrated circuit mask layout procedures (GV), pp. 407–413.
DACDAC-1975-Welt #layout #named
NOMAD: A printed wiring board layout system (MJW), pp. 152–161.
DACDAC-1974-CalafioreF #layout #multi
A system for multilayer printed wiring layout (RLC, JCF), pp. 322–326.
DACDAC-1974-CleemputL #formal method #graph #layout #problem
An improved graph-theoretic model for the circuit layout problem (WMvC, JGL), pp. 82–90.
DACDAC-1974-KozawaHISS #automation #generative #layout
Advanced LILAC — an Automated Layout Generation system for MOS/LSIs (TK, HH, TI, JS, SS), pp. 26–46.
DACDAC-1973-KernighanSP #algorithm
An optimum channel-routing algorithm for polycell layouts of integrated circuits (BWK, DGS, GP), pp. 50–59.
DACDAC-1973-Veit
T. A. G. traffic study in building layouts (FSV), pp. 139–144.
DACDAC-1972-FrewR #approach #layout #problem
Building polyonimoes; an approach to the space layout problem (RSF, PHR), p. 238.
DACDAC-1972-Harvey #automation #layout
Automated board layout (JGH), pp. 264–271.
DACDAC-1971-LarsenM #clustering #equation #layout #logic
Partitioning and ordering of logic equations for optimum MOS LSI device layout (RPL, LM), pp. 131–142.
DACDAC-1971-White #layout #named
RELATE: Relationship layout technique (RNW), p. 221.
DACDAC-1970-AkersGR #layout
IC mask layout with a single conductor layer (SBA, JMG, DLR), pp. 7–16.
DACDAC-1970-SassK #evaluation #layout #logic
An 1130-based logic, layout and evaluation system (WHS, SPK), pp. 64–70.
DACDAC-1970-Smith #layout
Computer-assisted template layout (KES), pp. 145–157.
DACDAC-1968-KadisTVHG #layout #source code
Building block programs for the layout of printed circuit boards utilizing integrated circuit packs (DAPSYS V.2) (RWK, KLT, WJVJ, WLH, CEG).
DACDAC-1968-Martin #design #layout
Computer-aided circuit layout and design (LCM).
DACDAC-1968-Silverberg #layout #named
CLIC — computer layout of integrated circuits (MS).
DACSHARE-1965-FiskI #automation #layout #quote
“ACCEL”: automated circuit card etching layout (CJF, DDI).

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