BibSLEIGH corpus
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Open Knowledge
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Travelled to:
1 × USA
Collaborated with:
V.S.Iyengar P.Bose W.H.J.Jr. D.Brand T.A.Nix S.C.Gundersen
Talks about:
synthesi (2) logic (2) technolog (1) processor (1) overview (1) infinit (1) system (1) repres (1) trace (1) model (1)

Person: Louise Trevillyan

DBLP DBLP: Trevillyan:Louise

Contributed to:

HPCA 19961996
DAC 19871987
DAC 19861986

Wrote 3 papers:

HPCA-1996-IyengarTB #infinity #modelling
Representative Traces for Processor Models with Infinite Cache (VSI, LT, PB), pp. 62–72.
DAC-1987-Trevillyan #logic #overview #synthesis
An Overview of Logic Synthesis Systems (LT), pp. 166–172.
DAC-1986-JoynerTBNG #adaptation #logic #synthesis
Technology adaption in logic synthesis (WHJJ, LT, DB, TAN, SCG), pp. 94–100.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.