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Travelled to:
1 × Germany
Collaborated with:
C.Armat G.B.Steven A.Gellert G.Palermo V.Zaccaria A.Florea C.Silvano
Talks about:
superscalar (1) architectur (1) processor (1) instruct (1) predict (1) perform (1) organis (1) exploit (1) select (1) impact (1)

Person: Lucian N. Vintan

DBLP DBLP: Vintan:Lucian_N=

Contributed to:

DATE 20102010
PDP 19991999

Wrote 2 papers:

DATE-2010-GellertPZFVS #architecture #design #energy #predict #smt
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions (AG, GP, VZ, AF, LNV, CS), pp. 271–274.
The impact of cache organisation on the instruction issue rate of a superscalar processor (LNV, CA, GBS), pp. 58–65.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.