BibSLEIGH — Cristina

Travelled to:

1 × Brazil
1 × Cyprus
3 × USA
5 × France
7 × Germany

Collaborated with:

G.Palermo V.Zaccaria D.Sciuto S.Xydis G.Mariani M.Sami R.Zafalon G.Agosta L.Fiorin M.Sykora A.Bona W.Fornaciari E.Paone I.S.Stamelakos M.Monchiero O.Villa G.Beltrame D.Lyonnard C.Pilkington L.Benini G.D.Micheli E.Macii F.Robino I.Sander V.M.Sima K.Bertels A.Brankovic J.Jovic A.Gellert A.Florea L.N.Vintan L.Salvemini N.Vahabi D.Melpignano G.Haugou T.Lepley P.Avasare G.Vanmeerbeeck C.Ykman-Couvreur

Talks about:

system (9) embed (9) explor (8) architectur (7) power (7) design (6) space (6) processor (5) level (5) optim (4)

Person: Cristina Silvano

DBLP: Silvano:Cristina

Contributed to:

2015

2014

2013

2012

2010

2009

2008

2006

2004

2003

2002

2001

1999

1998

Wrote 22 papers:

DATE-2015-PaoneRPZSS #constraints #framework #performance #platform: Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints (EP, FR, GP, VZ, IS, CS), pp. 736–741.
DATE-2014-MarianiPZS #design #named #predict #scheduling #simulation #using: DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling (GM, GP, VZ, CS), pp. 1–4.
DATE-2014-SilvanoPXS #architecture #manycore: Voltage island management in near threshold manycore architectures to mitigate dark silicon (CS, GP, SX, ISS), pp. 1–6.
DATE-2013-PaoneVZSMHL #embedded #manycore #modelling #platform #simulation: Improving simulation speed and accuracy for many-core embedded platforms with ensemble models (EP, NV, VZ, CS, DM, GH, TL), pp. 671–676.
DATE-2013-XydisPS #configuration management: Thermal-aware datapath merging for coarse-grained reconfigurable processors (SX, GP, CS), pp. 1649–1654.
DATE-2013-XydisPZS #architecture #compilation #framework #metamodelling #parametricity #synthesis: A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization (SX, GP, VZ, CS), pp. 659–664.
DATE-2012-MarianiSPZSB #architecture #configuration management #design #multi #resource management #runtime #using: Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures (GM, VMS, GP, VZ, CS, KB), pp. 1379–1384.
DAC-2010-MarianiBPJZS #design #multi: A correlation-based design space exploration methodology for multi-processor systems-on-chip (GM, AB, GP, JJ, VZ, CS), pp. 120–125.
DATE-2010-GellertPZFVS #architecture #design #energy #predict #smt: Energy-performance design space exploration in SMT architectures exploiting selective load value predictions (AG, GP, VZ, AF, LNV, CS), pp. 271–274.
DATE-2010-MarianiAVYPSZ #design #framework #industrial #manycore #resource management #runtime: An industrial design space exploration framework for supporting run-time resource management on multi-core systems (GM, PA, GV, CYC, GP, CS, VZ), pp. 196–201.
DATE-2009-FiorinPS #monitoring #runtime: MPSoCs run-time monitoring through Networks-on-Chip (LF, GP, CS), pp. 558–561.
SAC-2008-SykoraAS #embedded #pipes and filters: Dynamic configuration of application-specific implicit instructions for embedded pipelined processors (MS, GA, CS), pp. 1509–1516.
DATE-2006-BeltrameSSLP #simulation: Exploiting TLM and object introspection for system-level simulation (GB, DS, CS, DL, CP), pp. 100–105.
DATE-2006-MonchieroPSV #hardware #optimisation #performance: Power/performance hardware optimization for synchronization intensive applications in MPSoCs (MM, GP, CS, OV), pp. 606–611.
SAC-2004-AgostaPS #architecture #design #embedded #multi #power management #program transformation #source code: Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems (GA, GP, CS), pp. 891–896.
DATE-2003-PalermoSZ #architecture #embedded: Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture (GP, CS, VZ), pp. 20182–20187.
SAC-2003-SalveminiSSSZZ #architecture #embedded #energy #performance #trade-off: A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems (LS, MS, DS, CS, VZ, RZ), pp. 672–678.
DAC-2002-BonaSSZSZ #clustering #embedded #energy #estimation #optimisation: Energy estimation and optimization of embedded VLIW processors based on instruction clustering (AB, MS, DS, VZ, CS, RZ), pp. 886–891.
DATE-2002-BonaSSZSZ #embedded #estimation #optimisation: An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores (AB, MS, DS, VZ, CS, RZ), p. 1128.
DATE-2001-SamiSSZZ #embedded: Exploiting data forwarding to reduce the power budget of VLIW embedded processors (MS, DS, CS, VZ, RZ), pp. 252–257.
DATE-1999-FornaciariSS #embedded #encoding: Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems (WF, DS, CS), pp. 762–763.
DATE-1998-BeniniMSMS #encoding #optimisation: Address Bus Encoding Techniques for System-Level Power Optimization (LB, GDM, DS, EM, CS), pp. 861–866.