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Travelled to:
1 × France
Collaborated with:
B.F.Cockburn J.Han W.Pedrycz
Talks about:
process (1) number (1) design (1) corner (1) verif (1) simul (1) minim (1) dure (1)

Person: Michael Shoniker

DBLP DBLP: Shoniker:Michael

Contributed to:

DATE 20152015

Wrote 1 papers:

DATE-2015-ShonikerCHP #design #process #simulation #verification
Minimizing the number of process corner simulations during design verification (MS, BFC, JH, WP), pp. 289–292.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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