Proceedings of the 19th Conference and Exhibition on Design, Automation and Test in Europe
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Wolfgang Nebel, David Atienza
Proceedings of the 19th Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2015.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DATE-2015,
	acmid         = "2755753",
	address       = "Grenoble, France",
	editor        = "Wolfgang Nebel and David Atienza",
	isbn          = "978-3-9815370-4-8",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 19th Conference and Exhibition on Design, Automation and Test in Europe}",
	year          = 2015,
}

Contents (320 items)

DATE-2015-LiuHDCPKKTR
Clock domain crossing aware sequential clock gating (JL, MSH, KTD, JYC, JP, MK, MK, NT, AR), pp. 1–6.
DATE-2015-LiLZGSSZCLY #energy #performance
An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes (HL, YL, QZ, YG, XS, GS, CZ, MFC, RL, HY), pp. 7–12.
DATE-2015-FuLX #energy #memory management
Race to idle or not: balancing the memory sleep time with DVS for energy minimization (CF, ML, CJX), pp. 13–18.
DATE-2015-LinWPKC #configuration management
Event-driven and sensorless photovoltaic system reconfiguration for electric vehicles (XL, YW, MP, JK, NC), pp. 19–24.
DATE-2015-SamieBHH #multi #online
Online binding of applications to multiple clock domains in shared FPGA-based systems (FS, LB, CMH, JH), pp. 25–30.
DATE-2015-HadjisCSHTA #multi #synthesis
Profiling-driven multi-cycling in FPGA high-level synthesis (SH, AC, RS, YHA, HT, JA), pp. 31–36.
DATE-2015-KimAS #bound #composition #scheduling
Schedulability bound for integrated modular avionics partitions (JEK, TFA, LS), pp. 37–42.
DATE-2015-0001KVSMA #adaptation #embedded #energy #nondeterminism #scalability
Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems (AD, AK, BV, RAS, GVM, BMAH), pp. 43–48.
DATE-2015-SeylerSGNT #analysis #formal method
Formal analysis of the startup delay of SOME/IP service discovery (JRS, TS, MG, NN, JT), pp. 49–54.
DATE-2015-ThangamuthuCCL #analysis #network
Analysis of ethernet-switch traffic shapers for in-vehicle networking applications (ST, NC, PJLC, JJL), pp. 55–60.
DATE-2015-HerberRWH #realtime #scheduling #using
Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling (CH, AR, TW, AH), pp. 61–66.
DATE-2015-DaneseGP #automation #behaviour #execution #modelling
Automatic extraction of assertions from execution traces of behavioural models (AD, TG, GP), pp. 67–72.
DATE-2015-TaatizadehN #automation #design #detection #embedded #validation
A methodology for automated design of embedded bit-flips detectors in post-silicon validation (PT, NN), pp. 73–78.
DATE-2015-FarkashHS #data mining #debugging #locality #mining
Data mining diagnostics and bug MRIs for HW bug localization (MF, BGH, BS), pp. 79–84.
DATE-2015-BombieriFPS #abstraction #verification
RTL property abstraction for TLM assertion-based verification (NB, RF, GP, FS), pp. 85–90.
DATE-2015-HernandezA #low cost #safety
Low-cost checkpointing in automotive safety-relevant systems (CH, JA), pp. 91–96.
DATE-2015-KhosraviMGT #analysis #optimisation #reliability
Uncertainty-aware reliability analysis and optimization (FK, MM, MG, JT), pp. 97–102.
DATE-2015-MirkhaniMCA #design #estimation #fault #performance
Efficient soft error vulnerability estimation of complex designs (SM, SM, CYC, JA), pp. 103–108.
DATE-2015-RenTB #detection #learning #statistics
Detection of illegitimate access to JTAG via statistical learning in chip (XR, VGT, RD(B), pp. 109–114.
DATE-2015-YinLLWG #pipes and filters
Joint affine transformation and loop pipelining for mapping nested loop on CGRAs (SY, DL, LL, SW, YG), pp. 115–120.
DATE-2015-RajendranRadhika
Path selection based acceleration of conditionals in CGRAs (SR, AS, MH), pp. 121–126.
DATE-2015-KainthKNVT #obfuscation
Hardware-assisted code obfuscation for FPGA soft microprocessors (MK, LK, CN, SGV, RT), pp. 127–132.
DATE-2015-BanciuOW #information management #reliability
Reliable information extraction for single trace attacks (VB, EO, CW), pp. 133–138.
DATE-2015-StrobelBOSP #named #using
Scandalee: a side-channel-based disassembler using local electromagnetic emanations (DS, FB, DO, FS, CP), pp. 139–144.
DATE-2015-PozoSKM #question
Side-channel attacks from static power: when should we care? (SMDP, FXS, DK, AM), pp. 145–150.
DATE-2015-LeeLMHP #monitoring #named #security
Extrax: security extension to extract cache resident information for snoop-based external monitors (JL, YL, HM, IH, YP), pp. 151–156.
DATE-2015-KhanhSKA #dependence #design #synthesis
Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis (PNK, AKS, AK, KMMA), pp. 157–162.
DATE-2015-CilardoG #clustering #memory management #multi
Interplay of loop unrolling and multidimensional memory partitioning in HLS (AC, LG), pp. 163–168.
DATE-2015-PeemenMC #embedded #optimisation #reuse
Inter-tile reuse optimization applied to bandwidth constrained embedded accelerators (MP, BM, HC), pp. 169–174.
DATE-2015-YaoWGMCZ #architecture #manycore #named
SelectDirectory: a selective directory for cache coherence in many-core architectures (YY, GW, ZG, TM, WC, NZ), pp. 175–180.
DATE-2015-RanjanRVPRR #configuration management #memory management #named #using
DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes (AR, SGR, RV, VSP, KR, AR), pp. 181–186.
DATE-2015-YinLLWG15a #policy
Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache (SY, JL, LL, SW, YG), pp. 187–192.
DATE-2015-GomonyGAAG #memory management #realtime #scalability
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems (MDG, JG, BA, NCA, KGWG), pp. 193–198.
DATE-2015-ChenYQFM #evaluation #model checking #scheduling #statistics #using
Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking (MC, DY, XQ, XF, PM), pp. 199–204.
DATE-2015-ChenWY #parallel #performance
A fast parallel sparse solver for SPICE-based circuit simulators (XC, YW, HY), pp. 205–210.
DATE-2015-ChenZWWWZ #multi #named #pseudo #simulation
MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation (XC, GZ, HW, RW, PW, LZ), pp. 211–216.
DATE-2015-GerumBR #gpu #performance #simulation
Source level performance simulation of GPU cores (CG, OB, WR), pp. 217–222.
DATE-2015-GuanTW0 #analysis #realtime
Delay analysis of structural real-time workload (NG, YT, YW, WY), pp. 223–228.
DATE-2015-KroeningLMST #bytecode #effectiveness #low level #verification
Effective verification of low-level software with nested interrupts (DK, LL, TM, PS, MT), pp. 229–234.
DATE-2015-KimFPSL #framework #implementation #modelling #platform #verification
Platform-specific timing verification framework in model-based implementation (BK, LF, LTXP, OS, IL), pp. 235–240.
DATE-2015-Ibing #architecture #execution #symbolic computation
Architecture description language based retargetable symbolic execution (AI), pp. 241–246.
DATE-2015-IbrahimC #fault #personalisation
Error recovery in digital microfluidics for personalized medicine (MI, KC), pp. 247–252.
DATE-2015-Bogdan #approach #challenge #cyber-physical #manycore #personalisation #platform
A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms (PB), pp. 253–258.
DATE-2015-MajumderPK #architecture #biology #manycore
On-chip network-enabled many-core architectures for computational biology applications (TM, PPP, AK), pp. 259–264.
DATE-2015-OborilET #monitoring #online
High-resolution online power monitoring for modern microprocessors (FO, JE, MBT), pp. 265–268.
DATE-2015-GomezPBRBFG #design #energy #platform
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors (AG, CP, AB, DR, LB, HF, JPdG), pp. 269–272.
DATE-2015-MamaghaniGE #named
De-elastisation: from asynchronous dataflows to synchronous circuits (MJM, JDG, DAE), pp. 273–276.
DATE-2015-StoppeWD #automation #design #locality
Automated feature localization for dynamically generated SystemC designs (JS, RW, RD), pp. 277–280.
DATE-2015-KauerNLSC #geometry #optimisation #programming #using
Inductor optimization for active cell balancing using geometric programming (MK, SN, ML, SS, SC), pp. 281–284.
DATE-2015-MundhenkSLFC #authentication #lightweight #network
Lightweight authentication for secure automotive networks (PM, SS, ML, SAF, SC), pp. 285–288.
DATE-2015-ShonikerCHP #design #process #simulation #verification
Minimizing the number of process corner simulations during design verification (MS, BFC, JH, WP), pp. 289–292.
DATE-2015-ChenLH #approximate #reliability
An approximate voting scheme for reliable computing (KC, FL, JH), pp. 293–296.
DATE-2015-NowosielskiGBVB #design #fault tolerance #named
FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design (RN, LG, SB, GPV, HB), pp. 297–300.
DATE-2015-SkalickySLF #framework #hardware #runtime
A unified hardware/software MPSoC system construction and run-time framework (SS, AGS, SL, MF), pp. 301–304.
DATE-2015-FernandoWNKC #agile #algorithm #design #synthesis #using
(AS)2: accelerator synthesis using algorithmic skeletons for rapid design space exploration (SF, MW, CN, AK, HC), pp. 305–308.
DATE-2015-NiemannHGW #formal method #generative #modelling
Assisted generation of frame conditions for formal models (PN, FH, MG, RW), pp. 309–312.
DATE-2015-DeAntoniDTCC #concurrent #domain-specific language #metalanguage #towards
Towards a meta-language for the concurrency concern in DSLs (JD, PID, CT, JC, BC), pp. 313–316.
DATE-2015-FaravelonFP #branch #performance #predict #simulation
Fast and accurate branch predictor simulation (AF, NF, FP), pp. 317–320.
DATE-2015-KadryKMNSPPJS #case study #comparative #generative #simulation #testing
Comparative study of test generation methods for simulation accelerators (WK, DK, AM, AN, VS, JSP, SBP, WJ, JCS), pp. 321–324.
DATE-2015-WengCCHW #using
Using structural relations for checking combinationality of cyclic circuits (WCW, YCC, JHC, CYH, CYW), pp. 325–328.
DATE-2015-VieiraFCC #estimation #metric
NFRs early estimation through software metrics (AV, PF, LC, ÉFC), pp. 329–332.
DATE-2015-KonstantinouKM #encryption #functional #privacy #verification
Privacy-preserving functional IP verification utilizing fully homomorphic encryption (CK, AK, MM), pp. 333–338.
DATE-2015-ClercqRVV #encryption #implementation #performance
Efficient software implementation of ring-LWE encryption (RdC, SSR, FV, IV), pp. 339–344.
DATE-2015-YangRMDV #embedded #framework #generative #on the fly #platform #random #testing
Embedded HW/SW platform for on-the-fly testing of true random number generators (BY, VR, NM, WD, IV), pp. 345–350.
DATE-2015-LiaoWC #3d #manycore #online
An online thermal-constrained task scheduler for 3D multi-core processors (CHL, CHPW, KC), pp. 351–356.
DATE-2015-BiewerAGSH #approach #coordination #realtime #synthesis
A symbolic system synthesis approach for hard real-time systems based on coordinated SMT-solving (AB, BA, JG, TS, CH), pp. 357–362.
DATE-2015-ZhangJSPHP #hardware #manycore #named #pipes and filters
E-pipeline: elastic hardware/software pipelines on a many-core fabric (XZ, HJ, MS, JP, JH, SP), pp. 363–368.
DATE-2015-TanLF #memory management #reliability #using
Soft-error reliability and power co-optimization for GPGPUS register file using resistive memory (JT, ZL, XF), pp. 369–374.
DATE-2015-YanF #design #energy #mobile #optimisation #platform
Energy-efficient cache design in emerging mobile platforms: the implications and optimizations (KY, XF), pp. 375–380.
DATE-2015-ConstantinWKCB
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment (JC, LW, GK, AC, AB), pp. 381–386.
DATE-2015-ShafiqueGGH #manycore #variability
Variability-aware dark silicon management in on-chip many-core systems (MS, DG, SG, JH), pp. 387–392.
DATE-2015-RuizMK #approach #reuse
Systematic application of ISO 26262 on a SEooC: Support by applying a systematic reuse approach (AR, AM, TK), pp. 393–396.
DATE-2015-WartelKGBSTQLMB #analysis #case study #hardware #platform
Timing analysis of an avionics case study on complex hardware/software platforms (FW, LK, AG, AB, ZRS, BT, EQ, CL, EM, IB, JA, LCG, TV, FJC), pp. 397–402.
DATE-2015-ReichPEB #component #design #flexibility #proving
Silicon proof of the intelligent analog IP design flow for flexible automotive components (TR, HDBP, UE, RB), pp. 403–404.
DATE-2015-TeysseyreNOCCG #performance #set #simulation #using
Fast optical simulation from a reduced set of impulse responses using SystemC-AMS (FT, DN, IO, FC, FC, OG), pp. 405–409.
DATE-2015-BergmanBKKMNOPR #experience #industrial #verification
Designer-level verification: an industrial experience story (SB, GB, WK, SK, SM, ZN, AO, VP, WR, GS, VV), pp. 410–411.
DATE-2015-Sharma #optimisation #power management
Minimum current consumption transition time optimization methodology for low power CTS (VS), pp. 412–416.
DATE-2015-MavropoulosKN #architecture #configuration management
A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems (MM, GK, DN), pp. 417–422.
DATE-2015-ZhangPJLF #fault #self
Temperature-aware software-based self-testing for delay faults (YZ, ZP, JJ, HL, MF), pp. 423–428.
DATE-2015-KumarAL #detection #fault #monitoring
Operational fault detection and monitoring of a memristor-based LUT (TNK, HAFA, FL), pp. 429–434.
DATE-2015-HaghbayanRFLPNT #manycore #online #power management #testing
Power-aware online testing of manycore systems in the dark silicon era (MHH, AMR, MF, PL, JP, ZN, HT), pp. 435–440.
DATE-2015-SalivaCHFABBA #monitoring #reliability
Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI (MS, FC, VH, XF, DA, AB, AB, LA), pp. 441–446.
DATE-2015-VatajeluRIRPF #estimation #metric #robust
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell (EIV, RRM, MI, MR, PP, JF), pp. 447–452.
DATE-2015-MohammadiGM #fault #modelling
Fault modeling in controllable polarity silicon nanowire circuits (HGM, PEG, GDM), pp. 453–458.
DATE-2015-DeyCAM #analysis #difference #fault
Improved practical differential fault analysis of grain-128 (PD, AC, AA, DM), pp. 459–464.
DATE-2015-OyaSYT #classification #identification
A score-based classification method for identifying hardware-trojans at gate-level netlists (MO, YS, MY, NT), pp. 465–470.
DATE-2015-CakirM #clustering #correlation #detection #hardware #using
Hardware Trojan detection for gate-level ICs using signal correlation based clustering (, SM), pp. 471–476.
DATE-2015-ZhangZCY #scalability
Exploiting DRAM restore time variations in deep sub-micron scaling (XZ, YZ, BRC, JY), pp. 477–482.
DATE-2015-WangWXWWYDLMW #adaptation #process
Adaptively tolerate power-gating-induced power/ground noise under process variations (ZW, XW, JX, XW, ZW, PY, LHKD, HL, RKVM, ZW), pp. 483–488.
DATE-2015-TemanKGMB #embedded #energy #logic #trade-off
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories (AT, GK, RG, PAM, APB), pp. 489–494.
DATE-2015-Weis0ESVGKW #fault #metric #modelling
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs (CW, MJ, PE, CS, PV, SG, MK, NW), pp. 495–500.
DATE-2015-DuongNXWTBYWW #analysis
Coherent crosstalk noise analyses in ring-based optical interconnects (LHKD, MN, JX, ZW, YT, SLB, PY, XW, ZW), pp. 501–506.
DATE-2015-ChenEC #3d #hybrid
Enabling vertical wormhole switching in 3D NoC-bus hybrid systems (CC, ME, SDC), pp. 507–512.
DATE-2015-MineoRPACM #architecture #energy #performance #self
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures (AM, MSR, MP, GA, VC, MNM), pp. 513–518.
DATE-2015-FeldS #analysis #dependence
Sufficient response time analysis considering dependencies between rate-dependent tasks (TF, FS), pp. 519–524.
DATE-2015-BiondiB #analysis #modelling
Engine control: task modeling and analysis (AB, GCB), pp. 525–530.
DATE-2015-HollerKRRK #compilation #detection #evaluation
Evaluation of diverse compiling for software-fault detection (AH, NK, TR, KR, CK), pp. 531–536.
DATE-2015-RamboE #analysis #communication #worst-case
Worst-case communication time analysis of networks-on-chip with shared virtual channels (EAR, RE), pp. 537–542.
DATE-2015-AntoniadisKEBS #architecture #memory management #on the #optimisation #statistics
On the statistical memory architecture exploration and optimization (CA, GK, NEE, APB, GIS), pp. 543–548.
DATE-2015-AwanoHS #named #performance #probability
ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell (HA, MH, TS), pp. 549–554.
DATE-2015-KimKK #memory management #programming
Subpage programming for extending the lifetime of NAND flash memory (JHK, SHK, JSK), pp. 555–560.
DATE-2015-BajajNMS #architecture #cyber-physical #effectiveness #reliability
Optimized selection of reliable and cost-effective cyber-physical system architectures (NB, PN, MM, ALSV), pp. 561–566.
DATE-2015-ZhaoLXLHX #cyber-physical #energy #reduction
Software assisted non-volatile register reduction for energy harvesting based cyber-physical system (MZ, QL, MX, YL, JH, CJX), pp. 567–572.
DATE-2015-WaqasGKSBSVC #heuristic #online #scalability #scheduling
A re-entrant flowshop heuristic for online scheduling of the paper path in a large scale printer (UW, MG, JK, LJS, TB, SS, PV, HC), pp. 573–578.
DATE-2015-MunchPHH #embedded #manycore #named #realtime #scalability #using
MPIOV: scaling hardware-based I/O virtualization for mixed-criticality embedded real-time systems using non transparent bridges to (multi-core) multi-processor systems (DM, MP, OH, AH), pp. 579–584.
DATE-2015-YallaHK #comparison #multi
Comparison of multi-purpose cores of Keccak and AES (PY, EH, JPK), pp. 585–588.
DATE-2015-BaranowskiFKLTW #online #predict
On-line prediction of NBTI-induced aging rates (RB, FF, SK, CL, MBT, HJW), pp. 589–592.
DATE-2015-DengFDWLTINLCW #fault #hardware #network
Retraining-based timing error mitigation for hardware neural networks (JD, YF, ZD, YW, HL, OT, PI, DN, XL, YC, CW), pp. 593–596.
DATE-2015-CilingirogluZUK #representation
Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits (TBC, MZ, AU, WCK, JK, AJ, BBG, MSÜ), pp. 597–600.
DATE-2015-JovanovicP #product line
Fault-based attacks on the Bel-T block cipher family (PJ, IP), pp. 601–604.
DATE-2015-YeYZX #on the
On the premises and prospects of timing speculation (RY, FY, JZ, QX), pp. 605–608.
DATE-2015-KarageorgosSRRT #multi #variability
Impact of interconnect multiple-patterning variability on SRAMs (IK, MS, PR, JR, ZT, DV, RB, SS, WD), pp. 609–612.
DATE-2015-LaerEMWJ #multi #predict
Coherence based message prediction for optically interconnected chip multiprocessors (AVL, CE, MRM, PMW, TMJ), pp. 613–616.
DATE-2015-VargasQM #predict #question
OpenMP and timing predictability: a possible union? (RV, EQ, AM), pp. 617–620.
DATE-2015-MacherSBAK #analysis #named
SAHARA: a security-aware hazard and risk analysis method (GM, HS, RB, EA, CK), pp. 621–624.
DATE-2015-SarmaDGVN #paradigm #self
Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation (SS, NDD, PG, NV, AN), pp. 625–628.
DATE-2015-CornaFNS #android #detection
Occupancy detection via iBeacon on Android devices for smart building management (AC, LF, AAN, DS), pp. 629–632.
DATE-2015-KaneYHSS #architecture #interface #realtime
A neural machine interface architecture for real-time artificial lower limb control (JK, QY, RH, WS, MS), pp. 633–636.
DATE-2015-Rabaey #intranet
The human intranet: where swarms and humans meet (JMR), pp. 637–640.
DATE-2015-NguyenSCM #performance #robust #set
Efficient attacks on robust ring oscillator PUF with enhanced challenge-response set (PHN, DPS, RSC, DM), pp. 641–646.
DATE-2015-HashemianSWWCP #array #authentication #robust #using
A robust authentication methodology using physically unclonable functions in DRAM arrays (MSH, BPS, FGW, DJW, SC, CAP), pp. 647–652.
DATE-2015-VijayakumarK #design #modelling #novel
A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics (AV, SK), pp. 653–658.
DATE-2015-GoudVRR #design #robust #symmetry
Asymmetric underlapped FinFET based robust SRAM design at 7nm node (AAG, RV, AR, KR), pp. 659–664.
DATE-2015-RahaVRR #approximate #configuration management #energy #performance #quality
Quality configurable reduce-and-rank for energy efficient approximate computing (AR, SV, VR, AR), pp. 665–670.
DATE-2015-MamaghanianV #design #power management
Ultra-low-power ECG front-end design based on compressed sensing (HM, PV), pp. 671–676.
DATE-2015-CasagrandeR #algorithm #fuzzy #game studies #named #novel #optimisation #robust
GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games (TC, NR), pp. 677–682.
DATE-2015-0001B #clustering #energy #manycore #performance
A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters (FC, LB), pp. 683–688.
DATE-2015-WangLWY #gpu
Eliminating intra-warp conflict misses in GPU (BW, ZL, XW, WY), pp. 689–694.
DATE-2015-TuYOLW #architecture #configuration management #hardware #named
RNA: a reconfigurable architecture for hardware neural acceleration (FT, SY, PO, LL, SW), pp. 695–700.
DATE-2015-ZhangWTYX #approximate #framework #named #network
ApproxANN: an approximate computing framework for artificial neural network (QZ, TW, YT, FY, QX), pp. 701–706.
DATE-2015-SchaffnerGSB #architecture #image #linear
DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS (MS, FKG, AS, LB), pp. 707–712.
DATE-2015-SonLKYL #smarttech
A small non-volatile write buffer to reduce storage writes in smartphones (MS, SL, KK, SY, SL), pp. 713–718.
DATE-2015-HuangHC #algorithm #clustering #framework #multi #problem #scalability
Clustering-based multi-touch algorithm framework for the tracking problem with a large number of points (SLH, SYH, CPC), pp. 719–724.
DATE-2015-KalaliH #2d #adaptation #energy #hardware
A low energy 2D adaptive median filter hardware (EK, IH), pp. 725–729.
DATE-2015-KobbeBH #adaptation #modelling #on the fly #performance
Adaptive on-the-fly application performance modeling for many cores (SK, LB, JH), pp. 730–735.
DATE-2015-PaoneRPZSS #constraints #framework #performance #platform
Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints (EP, FR, GP, VZ, IS, CS), pp. 736–741.
DATE-2015-RawatS #architecture #concurrent #hybrid #manycore #memory management #thread
Enabling multi-threaded applications on hybrid shared memory manycore architectures (TR, AS), pp. 742–747.
DATE-2015-VenkataramaniCR #approximate
Computing approximately, and efficiently (SV, STC, KR, AR), pp. 748–751.
DATE-2015-ArumugamSAPUBPY #algorithm #co-evolution #design #energy #memory management #novel #performance
Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles (GPA, PS, JA, KVP, EU, AB, P, SY), pp. 752–757.
DATE-2015-VenkataramanKSE #design #heuristic #using
Designing inexact systems efficiently using elimination heuristics (SV, AK, JS, CCE), pp. 758–763.
DATE-2015-DubenSPYAEPP #big data #case study #energy #performance
Opportunities for energy efficient computing: a study of inexact general purpose processors for high-performance and big-data applications (PDD, JS, P, SY, JA, CCE, KVP, TNP), pp. 764–769.
DATE-2015-FrancqF #detection #hardware
Introduction to hardware trojan detection methods (JF, FF), pp. 770–775.
DATE-2015-DupuisBFNR #hardware #testing
New testing procedure for finding insertion sites of stealthy hardware trojans (SD, PSB, MLF, GDN, BR), pp. 776–781.
DATE-2015-NgoEBDGNRR #detection #hardware #metric
Hardware trojan detection by delay and electromagnetic measurements (XTN, IE, SB, JLD, SG, ZN, JBR, BR), pp. 782–787.
DATE-2015-CourbonLFT #detection #hardware #performance
A high efficiency hardware trojan detection technique based on fast SEM imaging (FC, PLM, JJAF, AT), pp. 788–793.
DATE-2015-KarkarTMY #communication #distributed #multi
Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting (AK, KFT, TSTM, AY), pp. 794–799.
DATE-2015-BishnoiLGF #2d #named
d2-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs (RB, VL, MSG, JF), pp. 800–805.
DATE-2015-BalboniFB #configuration management #distributed #latency #multi #network #scalability #using
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration (MB, JF, DB), pp. 806–811.
DATE-2015-YazdanbakhshMTP #approximate #design #hardware #named
Axilog: language support for approximate hardware design (AY, DM, BT, JP, AN, SS, KR, NR, RJ, AR, HE, KB), pp. 812–817.
DATE-2015-DuqueDY #adaptation #behaviour #fault #reliability #runtime
Improving MPSoC reliability through adapting runtime task schedule based on time-correlated fault behavior (LARD, JMMD, CY), pp. 818–823.
DATE-2015-KriebelRSASH #analysis #combinator #configuration management #fault #named #performance
ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits (FK, SR, DS, PVA, MS, JH), pp. 824–829.
DATE-2015-HanFNQ #energy #fault tolerance #multi #platform #scheduling
Energy minimization for fault tolerant scheduling of periodic fixed-priority applications on multiprocessor platforms (QH, MF, LN, GQ), pp. 830–835.
DATE-2015-TrinadhBSPK #approach #named #programming #testing
DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests (ST, CSB, SGS, SP, VK), pp. 836–841.
DATE-2015-LiDC #algorithm #clustering #power of
A scan partitioning algorithm for reducing capture power of delay-fault LBIST (NL, ED, GC), pp. 842–847.
DATE-2015-LoCH #architecture #clustering #fault
Architecture of ring-based redundant TSV for clustered faults (WHL, KC, TH), pp. 848–853.
DATE-2015-ChenKXMLYVSCY #algorithm #array #learning
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip (PYC, DK, ZX, AM, BL, JY, SBKV, JsS, YC, SY), pp. 854–859.
DATE-2015-TangXLLCWY #network #question
Spiking neural network with RRAM: can we use it for real-world application? (TT, LX, BL, RL, YC, YW, HY), pp. 860–865.
DATE-2015-ShutoYS #architecture #case study #comparative #using
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology (YS, SY, SS), pp. 866–871.
DATE-2015-VatajeluNIP
STT MRAM-Based PUFs (EIV, GDN, MI, PP), pp. 872–875.
DATE-2015-KuhnPABR
Spatial and temporal granularity limits of body biasing in UTBB-FDSOI (JMK, DP, HA, OB, WR), pp. 876–879.
DATE-2015-JiRML #hardware #implementation #logic #network #probability #using
A hardware implementation of a radial basis function neural network using stochastic logic (YJ, FR, CM, DJL), pp. 880–883.
DATE-2015-WangLZ #big data #named
SODA: software defined FPGA based accelerators for big data (CW, XL, XZ), pp. 884–887.
DATE-2015-TangAKP #communication #configuration management
Dynamic reconfigurable puncturing for secure wireless communication (LT, JAA, AK, SP), pp. 888–891.
DATE-2015-RustLP #approximate #architecture
QR-decomposition architecture based on two-variable numeric function approximation (JR, FL, SP), pp. 892–895.
DATE-2015-ReehmanCCS #approach #architecture #hardware #memory management #parallel
In-place memory mapping approach for optimized parallel hardware interleaver architectures (SUR, CC, PC, AS), pp. 896–899.
DATE-2015-FuZLX #manycore #memory management
Maximizing common idle time on multi-core processors with shared memory (CF, YZ, ML, CJX), pp. 900–903.
DATE-2015-LiSGWXZS #memory management #performance #reduction
Maximizing IO performance via conflict reduction for flash memory storage systems (QL, LS, CG, KW, CJX, QZ, EHMS), pp. 904–907.
DATE-2015-MazloumiM #hybrid #memory management #multi
A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors (AM, MM), pp. 908–911.
DATE-2015-RosenMH #architecture #implementation #multi #reliability
Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores (JvR, MM, LH), pp. 912–915.
DATE-2015-KhanSH #adaptation #manycore #power management
Power-efficient accelerator allocation in adaptive dark silicon many-core systems (MUKK, MS, JH), pp. 916–919.
DATE-2015-PaganoVRCSS #configuration management
Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems (DP, MV, MR, RC, DS, MDS), pp. 920–923.
DATE-2015-HuangTTC #architecture
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects (SYH, MTT, KHHT, WTC), pp. 924–927.
DATE-2015-CalayirDWP #multi #programmable
Analog neuromorphic computing enabled by multi-gate programmable resistive devices (VC, MD, JAW, LP), pp. 928–931.
DATE-2015-WangHNYYWYZ #energy #in memory #recognition
An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition (YW, HH, LN, HY, MY, CW, WY, JZ), pp. 932–935.
DATE-2015-LinH #memory management #named
HLC: software-based half-level-cell flash memory (HYL, JWH), pp. 936–941.
DATE-2015-SonghoriMLK #automation #data analysis #framework #hardware #named
AHEAD: automated framework for hardware accelerated iterative data analysis (EMS, AM, XL, FK), pp. 942–947.
DATE-2015-RustP #approximate #design #multi
Design method for multiplier-less two-variable numeric function approximation (JR, SP), pp. 948–953.
DATE-2015-KamalIAP #algorithm
A thermal stress-aware algorithm for power and temperature management of MPSoCs (MK, AI, AAK, MP), pp. 954–959.
DATE-2015-SinglaKUO #mobile #platform #power management #predict
Predictive dynamic thermal and power management for heterogeneous mobile platforms (GS, GK, AKU, ÜYO), pp. 960–965.
DATE-2015-DoustiP #distributed #power management
Power-efficient control of thermoelectric coolers considering distributed hot spots (MJD, MP), pp. 966–971.
DATE-2015-LeeSLKKL #programmable
DSP based programmable FHD HEVC decoder (SL, JS, WL, DHK, JK, SL), pp. 972–973.
DATE-2015-NguyenASS #gpu #platform #simulation
Accelerating complex brain-model simulations on GPU platforms (HADN, ZAA, GS, CS), pp. 974–979.
DATE-2015-MaHJ #manycore
A packet-switched interconnect for many-core systems with BE and RT service (RM, ZH, AJ), pp. 980–983.
DATE-2015-TchagouTMVSQ #multi #testing
Reducing trace size in multimedia applications endurance tests (SVET, AT, JFM, BV, MS, RQ), pp. 984–985.
DATE-2015-PhilippeCBP #algorithm #design #embedded
Exploration and design of embedded systems including neural algorithms (JMP, AC, OB, MP), pp. 986–991.
DATE-2015-BrunduPAGRRM #distributed #energy #framework #integration #strict
A new distributed framework for integration of district energy data from heterogeneous devices (FGB, EP, AA, MG, GR, SR, EM), pp. 992–993.
DATE-2015-LocatelliVMFVKK #architecture #energy
Spintronic devices as key elements for energy-efficient neuroinspired architectures (NL, AFV, AM, JSF, DV, JVK, JOK, WZ, JG, DQ), pp. 994–999.
DATE-2015-ZhangYWLC #design #logic #power management
Giant spin hall effect (GSHE) logic design for low power application (YZ, BY, WW, HL, YC), pp. 1000–1005.
DATE-2015-HanyuSOMNM #architecture #in memory #paradigm #power management #reliability #towards
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm (TH, DS, NO, SM, MN, AM), pp. 1006–1011.
DATE-2015-SenniBTSGM
Potential applications based on NVM emerging technologies (SS, RMB, LT, GS, AG, BM), pp. 1012–1017.
DATE-2015-SunZLZZGSKRLZY #design #memory management
From device to system: cross-layer design exploration of racetrack memory (GS, CZ, HL, YZ, WZ, YG, YS, JOK, DR, YL, WZ, HY), pp. 1018–1023.
DATE-2015-FangHYZLG #estimation #fault #performance
Efficient bit error rate estimation for high-speed link by Bayesian model fusion (CF, QH, FY, XZ, XL, CG), pp. 1024–1029.
DATE-2015-LiaperdosSATAL #deployment #performance #using
Fast deployment of alternate analog test using Bayesian model fusion (JL, HGDS, LA, YT, AA, XL), pp. 1030–1035.
DATE-2015-DoblerHRPRB #adaptation #identification #named
Bordersearch: an adaptive identification of failure regions (MD, MH, MR, GP, WR, MB), pp. 1036–1041.
DATE-2015-GoncalvesLCTCB #algorithm #modelling #performance #reduction
A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits (HRG, XL, MVC, VT, JMCJ, KMB), pp. 1042–1047.
DATE-2015-OhYM #android #compilation #virtual machine
Bytecode-to-C ahead-of-time compilation for Android Dalvik virtual machine (HSO, JHY, SMM), pp. 1048–1053.
DATE-2015-KyrtatasSP #algebra #compilation #embedded #linear
A basic linear algebra compiler for embedded processors (NK, DGS, MP), pp. 1054–1059.
DATE-2015-KapadiaP #adaptation #named #parallel #scheduling
VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era (NAK, SP), pp. 1060–1065.
DATE-2015-PaulinoFBC #configuration management #execution #hardware #using
Transparent acceleration of program execution using reconfigurable hardware (NMCP, JCF, JB, JMPC), pp. 1066–1071.
DATE-2015-GiefersPH #kernel
Accelerating arithmetic kernels with coherent attached FPGA coprocessors (HG, RP, CH), pp. 1072–1077.
DATE-2015-DamschenRVP
Transparent offloading of computational hotspots from binary code to Xeon Phi (MD, HR, GV, CP), pp. 1078–1083.
DATE-2015-ThomasFCG #hardware
Transparent linking of compiled software and synthesized hardware (DBT, STF, GAC, DRG), pp. 1084–1089.
DATE-2015-PsarrasSND #named #network #performance #scheduling
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation (AP, IS, CN, GD), pp. 1090–1095.
DATE-2015-CasuG
Rate-based vs delay-based control for DVFS in NoC (MRC, PG), pp. 1096–1101.
DATE-2015-MajumderLBP #analysis #architecture #manycore #probability
NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions (TM, XL, PB, PP), pp. 1102–1107.
DATE-2015-AhsanK #architecture #optimisation #quantum #using
Optimization of quantum computer architecture using a resource-performance simulator (MA, JK), pp. 1108–1113.
DATE-2015-HuangLH #multi
Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers (CMH, CHL, JDH), pp. 1114–1119.
DATE-2015-LiFBLON #design
Thermal aware design method for VCSEL-based on-chip optical interconnect (HL, AF, SLB, XL, IO, GN), pp. 1120–1125.
DATE-2015-LeeJG #functional #hardware #performance #simulation
Dynamic power and performance back-annotation for fast and accurate functional hardware simulation (DL, LKJ, AG), pp. 1126–1131.
DATE-2015-DoumaAP #estimation #execution #performance #precise
Fast and precise cache performance estimation for out-of-order execution (RD, SA, ADP), pp. 1132–1137.
DATE-2015-RaiT #manycore #modelling
A calibration based thermal modeling technique for complex multicore systems (DR, LT), pp. 1138–1143.
DATE-2015-JiaoMD #reasoning #synthesis
Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications (FJ, SM, AD), pp. 1144–1149.
DATE-2015-SedighiPHNN
A CNN-inspired mixed signal processor based on tunnel transistors (BS, IP, XSH, JN, MTN), pp. 1150–1155.
DATE-2015-LourencoMH #using
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction (NCL, RM, NH), pp. 1156–1161.
DATE-2015-BrachtendorfB
Initial transient response of oscillators with long settling time (HGB, KB), pp. 1162–1167.
DATE-2015-LinSKRM #debugging #detection #effectiveness #fault #performance #testing #validation
Quick error detection tests with fast runtimes for effective post-silicon validation and debug (DL, ES, SK, ER, SM), pp. 1168–1173.
DATE-2015-SchneiderHKWW #fault #simulation
GPU-accelerated small delay fault simulation (ES, SH, MAK, XW, HJW), pp. 1174–1179.
DATE-2015-GorevUD #fault #parallel #simulation
Fault simulation with parallel exact critical path tracing in multiple core environment (MG, RU, SD), pp. 1180–1185.
DATE-2015-RiefertCSRB #automation #generative #on the #source code
On the automatic generation of SBST test programs for in-field test (AR, RC, MS, MSR, BB), pp. 1186–1191.
DATE-2015-BillointSRVBFRC #2d #3d #design #using
A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool (OB, HS, IR, MV, PB, CFB, OR, GC, FD, AF, JM, OF, OT, JFC, ST, FC), pp. 1192–1196.
DATE-2015-ShulakerWSWWM #3d #concept #integration
Monolithic 3D integration: a path from concept to reality (MMS, TFW, MMS, HW, HSPW, SM), pp. 1197–1202.
DATE-2015-GaillardonTSTOS #power management
A ultra-low-power FPGA based on monolithically integrated RRAMs (PEG, XT, JS, MT, SRO, DS, YL, GDM), pp. 1203–1208.
DATE-2015-ChenYCK #migration #named
PWL: a progressive wear leveling to minimize data migration overheads for nand flash devices (FHC, MCY, YHC, TWK), pp. 1209–1212.
DATE-2015-CuiZSW #towards #using
Towards trustable storage using SSDs with proprietary FTL (XC, MZ, LS, KW), pp. 1213–1216.
DATE-2015-EgilmezMME #smarttech
User-specific skin temperature-aware DVFS for smartphones (BE, GM, SOM, OE), pp. 1217–1220.
DATE-2015-IqtedarHSH #analysis #distributed #probability
Formal probabilistic analysis of distributed dynamic thermal management (SI, OH, MS, JH), pp. 1221–1224.
DATE-2015-AfacanBPDB #hybrid #monte carlo
A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool (EA, GB, AEP, GD, IFB), pp. 1225–1228.
DATE-2015-BarraganL #case study #feature model #using
Feature selection for alternate test using wrappers: application to an RF LNA case study (MJB, GL), pp. 1229–1232.
DATE-2015-FuWH #code generation
Improving SIMD code generation in QEMU (SYF, JJW, WCH), pp. 1233–1236.
DATE-2015-LezosDM #analysis #distance #locality #optimisation #reuse
Reuse distance analysis for locality optimization in loop-dominated applications (CL, GD, KM), pp. 1237–1240.
DATE-2015-ZhuCPP #manycore #named
TAPP: temperature-aware application mapping for NoC-based many-core processors (DZ, LC, TMP, MP), pp. 1241–1244.
DATE-2015-BokhariJSHP #adaptation
Malleable NoC: dark silicon inspired adaptable Network-on-Chip (HB, HJ, MS, JH, SP), pp. 1245–1248.
DATE-2015-SteinhorstL #composition #identification
Topology identification for smart cells in modular batteries (SS, ML), pp. 1249–1252.
DATE-2015-CaoBFCCAO #feature model #validation
LVS check for photonic integrated circuits: curvilinear feature extraction and validation (RC, JB, JF, LC, JC, AA, IO), pp. 1253–1256.
DATE-2015-LeleMB #case study #data flow
FP-scheduling for mode-controlled dataflow: a case study (AL, OM, KvB), pp. 1257–1260.
DATE-2015-SalfelderH #adaptation #evaluation #simulation #using
Ageing simulation of analogue circuits and systems using adaptive transient evaluation (FS, LH), pp. 1261–1264.
DATE-2015-BrennaBBL #design
A tool for the assisted design of charge redistribution SAR ADCs (SB, AB, AB, ALL), pp. 1265–1268.
DATE-2015-ZwergerG #detection #symmetry
Detection of asymmetric aging-critical voltage conditions in analog power-down mode (MZ, HEG), pp. 1269–1272.
DATE-2015-GarciaMSN #multi #performance
High performance single supply CMOS inverter level up shifter for multi: supply voltages domains (JCG, JAMN, JS, SN), pp. 1273–1276.
DATE-2015-TouatiBDGVBR #functional #power management #source code #testing
Exploring the impact of functional test programs re-used for power-aware testing (AT, AB, LD, PG, AV, PB, MSR), pp. 1277–1280.
DATE-2015-ChenWLL #debugging
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC (HCC, CRW, KSML, KJL), pp. 1281–1284.
DATE-2015-KunduBK #design #fault #testing
Fault diagnosis in designs with extreme low pin test data compressors (SK, PB, RK), pp. 1285–1288.
DATE-2015-ZhuM #linear #machine learning #optimisation #programming #using
Optimizing dynamic trace signal selection using machine learning and linear programming (CSZ, SM), pp. 1289–1292.
DATE-2015-BaldwinBRPB #analysis #array #predict #using
Gait analysis for fall prediction using hierarchical textile-based capacitive sensor arrays (RB, SB, RR, CP, NB), pp. 1293–1298.
DATE-2015-Lastras-Montano #configuration management #hybrid #memory management #named
HReRAM: a hybrid reconfigurable resistive random-access memory (MALM, AG, KTC), pp. 1299–1304.
DATE-2015-ZhongLLZLZS #mobile #named
nCode: limiting harmful writes to emerging mobile NVRAM through code swapping (KZ, DL, LL, XZ, WL, QZ, EHMS), pp. 1305–1310.
DATE-2015-KomalanTPFC
System level exploration of a STT-MRAM based level 1 data-cache (MPK, CT, JIGP, FTF, FC), pp. 1311–1316.
DATE-2015-AzarkhishRLB #memory management #performance
High performance AXI-4.0 based interconnect for extensible smart memory cubes (EA, DR, IL, LB), pp. 1317–1322.
DATE-2015-Baruah #graph #scheduling
The federated scheduling of constrained-deadline sporadic DAG task systems (SB), pp. 1323–1328.
DATE-2015-HuangKGT #scheduling
Run and be safe: mixed-criticality scheduling with temporary processor speedup (PH, PK, GG, LT), pp. 1329–1334.
DATE-2015-WangNRQ #manycore #realtime #scheduling #statistics
Multi-core fixed-priority scheduling of real-time tasks with statistical deadline guarantee (TW, LN, SR, GQ), pp. 1335–1340.
DATE-2015-ParkAHYL #big data #energy #gpu #low cost #memory management #performance
Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing (EP, JA, SH, SY, SL), pp. 1341–1346.
DATE-2015-LiuHFRQR #power management
Power minimization for data center with guaranteed QoS (SL, SH, MF, SR, GQ, SR), pp. 1347–1352.
DATE-2015-ConficoniBTTB #energy
Energy-aware cooling for hot-water cooled supercomputers (CC, AB, AT, GT, LB), pp. 1353–1358.
DATE-2015-GheolbanoiuPC #adaptation #hybrid
Hybrid adaptive clock management for FPGA processor acceleration (AG, LP, SC), pp. 1359–1364.
DATE-2015-WeiDC #architecture #memory management #multi #scalability
A scalable and high-density FPGA architecture with multi-level phase change memory (CW, AD, DC), pp. 1365–1370.
DATE-2015-RamachandranHHM #fault
FPGA accelerated DNA error correction (AR, YH, WmWH, JM, DC), pp. 1371–1376.
DATE-2015-AhmadyanGNCV #analysis #diagrams #performance
Fast eye diagram analysis for high-speed CMOS circuits (SNA, CG, SN, EC, SV), pp. 1377–1382.
DATE-2015-YuSHEAB #library #multi #statistics #using
Statistical library characterization using belief propagation across multiple technology nodes (LY, SS, CH, IME, DAA, DSB), pp. 1383–1388.
DATE-2015-Leger #adaptation #multi
Combining adaptive alternate test and multi-site (GL), pp. 1389–1394.
DATE-2015-LiaperdosAT #detection #estimation #fault #probability #testing
A method for the estimation of defect detection probability of analog/RF defect-oriented tests (JL, AA, YT), pp. 1395–1400.
DATE-2015-BerryhillV #automation #functional
Automated rectification methodologies to functional state-space unreachability (RB, AGV), pp. 1401–1406.
DATE-2015-DarkeCVSM #approximate #bound #model checking #using
Over-approximating loops to prove properties using bounded model checking (PD, BC, RV, US, RM), pp. 1407–1412.
DATE-2015-JoostenS #architecture #automation #communication #design #modelling
Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs (SJCJ, JS), pp. 1413–1418.
DATE-2015-BurnsSY #modelling #synthesis #verification
GALS synthesis and verification for xMAS models (FPB, DS, AY), pp. 1419–1424.
DATE-2015-LiJHWCGLKW #design #optimisation #using
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model (HL, ZJ, PH, YW, HYC, BG, XYL, JFK, HSPW), pp. 1425–1430.
DATE-2015-MotamanGR #adaptation #robust
Impact of process-variations in STTRAM and adaptive boosting for robustness (SM, SG, NR), pp. 1431–1436.
DATE-2015-PajouhiFR #architecture #co-evolution #design #reliability
Device/circuit/architecture co-design of reliable STT-MRAM (ZP, XF, KR), pp. 1437–1442.
DATE-2015-SharmaGR
Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems (AS, AAG, KR), pp. 1443–1448.
DATE-2015-HuQ #approximate #fault
A new approximate adder with low relative error and correct sign calculation (JH, WQ), pp. 1449–1454.
DATE-2015-FuggerNNS #modelling #physics #towards
Towards binary circuit models that faithfully capture physical solvability (MF, RN, TN, US), pp. 1455–1460.
DATE-2015-DiaoLWW #reduction
A coupling area reduction technique applying ODC shifting (YD, TKL, XW, YLW), pp. 1461–1466.
DATE-2015-ZhaoQ #design #probability #synthesis
A general design of stochastic circuit and its synthesis (ZZ, WQ), pp. 1467–1472.
DATE-2015-GuardatiCFB #framework
Paper, pen and ink: an innovative system and software framework to assist writing rehabilitation (LG, FC, EF, LB), pp. 1473–1478.
DATE-2015-AmirhosseinRBCM #power management
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission (MSA, PMR, AB, MC, MM, DD, GM), pp. 1479–1484.
DATE-2015-MuzaffarYSE #power management
A pulsed-index technique for single-channel, low-power, dynamic signaling (SM, JY, AS, IAME), pp. 1485–1490.
DATE-2015-VenkataramaniBH #named
SAPPHIRE: an always-on context-aware computer vision system for portable devices (SV, VB, XSH, JL, JL, MP, BP, MS), pp. 1491–1496.
DATE-2015-RahimiGCBG #approximate #energy #memory management
Approximate associative memristive memory for energy-efficient GPUs (AR, AG, KTC, LB, RKG), pp. 1497–1502.
DATE-2015-ParkTNII #performance #platform
Platform-aware dynamic configuration support for efficient text processing on heterogeneous system (MSP, OT, VN, MJI, RI), pp. 1503–1508.
DATE-2015-DinizSDBH #architecture #hardware #performance #standard #video
A deblocking filter hardware architecture for the high efficiency video coding standard (CMD, MS, FVD, SB, JH), pp. 1509–1514.
DATE-2015-PaganiCSH #modelling #named #performance
MatEx: efficient transient and peak temperature computation for compact thermal models (SP, JJC, MS, JH), pp. 1515–1520.
DATE-2015-ChenM #distributed #learning #manycore #optimisation #performance
Distributed reinforcement learning for power limited many-core system performance optimization (ZC, DM), pp. 1521–1526.
DATE-2015-MirhosseiniSFMS #energy #network
An energy-efficient virtual channel power-gating mechanism for on-chip networks (AM, MS, AF, MM, HSA), pp. 1527–1532.
DATE-2015-KimKKC #manycore #mobile #named
M-DTM: migration-based dynamic thermal management for heterogeneous mobile multi-core processors (YGK, MK, JMK, SWC), pp. 1533–1538.
DATE-2015-PerriconeZSHN #3d #design #towards
Towards systematic design of 3D pNML layouts (RP, YZ, KMS, XSH, MTN), pp. 1539–1542.
DATE-2015-PorembaMLVX #3d #modelling #named
DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches (MP, SM, DL, JSV, YX), pp. 1543–1546.
DATE-2015-KanounS #big data #concept #data type #detection #learning #online #scheduling #streaming
Big-data streaming applications scheduling with online learning and concept drift detection (KK, MvdS), pp. 1547–1550.
DATE-2015-HuriauxCS #design #runtime
Design flow and run-time management for compressed FPGA configurations (CH, AC, OS), pp. 1551–1554.
DATE-2015-DghaisR #empirical #modelling #simulation
Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation (WD, JR), pp. 1555–1558.
DATE-2015-ErolOSPB #metric #using
On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC (OEE, SO, CKHS, RAP, LB), pp. 1559–1562.
DATE-2015-SaifhashemiHBB #equivalence #logic #tool support #using
Logical equivalence checking of asynchronous circuits using commercial tools (AS, HHH, PB, PAB), pp. 1563–1566.
DATE-2015-ChangD #analysis #model checking #modelling #using
May-happen-in-parallel analysis of ESL models using UPPAAL model checking (CWC, RD), pp. 1567–1570.
DATE-2015-MadhukarSWKM #abstraction #lazy evaluation #using #verification
Verifying synchronous reactive systems using lazy abstraction (KM, MS, BW, DK, RM), pp. 1571–1574.
DATE-2015-VenkatesanVFRR #energy #logic #named
Spintastic: spin-based stochastic logic for energy-efficient computing (RV, SV, XF, KR, AR), pp. 1575–1578.
DATE-2015-LiXWNP #fine-grained #multi #power management #reduction #using
Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique (JL, QX, YW, SN, MP), pp. 1579–1582.
DATE-2015-SuHL #encoding #named #recognition #scalability
SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding (HYS, CHH, YLL), pp. 1583–1586.
DATE-2015-KumarLSSH #adaptation #verification
Timing verification for adaptive integrated circuits (RK, BL, YS, US, JH), pp. 1587–1590.
DATE-2015-0001CY #approach #optimisation #process #robust
A robust approach for process variation aware mask optimization (JK, WKC, EFYY), pp. 1591–1594.
DATE-2015-LiuDNL #hardware #named #realtime
FastTree: a hardware KD-tree construction acceleration engine for real-time ray tracing (XL, YD, YN, ZL), pp. 1595–1598.
DATE-2015-BruggerVWTK #cpu #hybrid
Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems (CB, JAV, NW, ST, RK), pp. 1599–1602.
DATE-2015-DoustiPP #generative #modelling
Accurate electrothermal modeling of thermoelectric generators (MJD, AP, MP), pp. 1603–1606.
DATE-2015-XieKBWPC #design #energy #hybrid #optimisation
Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect (QX, YK, DB, YW, MP, NC), pp. 1607–1610.
DATE-2015-BortolottiMBRSB #monitoring #power management
An ultra-low power dual-mode ECG monitor for healthcare and wellness (DB, MM, AB, RR, GS, LB), pp. 1611–1616.
DATE-2015-GitinaWRSSB #quantifier
Solving DQBF through quantifier elimination (KG, RW, SR, MS, CS, BB), pp. 1617–1622.
DATE-2015-SunKPE #algebra #geometry #using #verification
Formal verification of sequential Galois field arithmetic circuits using algebraic geometry (XS, PK, TP, FE), pp. 1623–1628.
DATE-2015-WeiDLW #metaprogramming
A universal macro block mapping scheme for arithmetic circuits (XW, YD, TKL, YLW), pp. 1629–1634.
DATE-2015-HoqueMS #analysis #approach #maintenance #model checking #probability #reliability #towards
Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking (KAH, OAM, YS), pp. 1635–1640.
DATE-2015-LiuLY #approach #effectiveness
An effective triple patterning aware grid-based detailed routing approach (ZL, CL, EFYY), pp. 1641–1646.
DATE-2015-LuLJLHCL #standard
Simultaneous transistor pairing and placement for CMOS standard cells (AL, HJL, EJJ, YPL, CHH, CCC, RBL), pp. 1647–1652.
DATE-2015-LeeCSP #3d
A TSV noise-aware 3-D placer (YML, CC, JS, KTP), pp. 1653–1658.
DATE-2015-ChungSS #identification
Identifying redundant inter-cell margins and its application to reducing routing congestion (WC, SS, YS), pp. 1659–1664.
DATE-2015-PoplavkoSBBB #execution #modelling #multi #realtime
Models for deterministic execution of real-time multiprocessor applications (PP, DS, PB, SB, MB), pp. 1665–1670.
DATE-2015-AndradeMVAPL #analysis #data flow #modelling
Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation (LA, TM, AV, CBA, FP, MML), pp. 1671–1676.
DATE-2015-YanCC #consistency #natural language #specification
Formal consistency checking over specifications in natural languages (RY, CHC, YC), pp. 1677–1682.
DATE-2015-IbrahimHBAABM #3d
Tackling the bottleneck of delay tables in 3D ultrasound imaging (AI, PH, AB, FA, MA, LB, GDM), pp. 1683–1688.
DATE-2015-SporrerBVMRMBBP #array #smarttech
Integrated CMOS receiver for wearable coil arrays in MRI applications (BS, LB, CV, AM, JR, JM, DOB, TB, KPP, GT, QH), pp. 1689–1694.
DATE-2015-FarserotuDBVQKE
Tactile prosthetics in WiseSkin (JF, JDD, JB, PNV, CRQ, VK, CCE, SL, HM, RM, VK, HH, TL, CA), pp. 1695–1697.
DATE-2015-BringmannEGGMSS #generative #prototype #simulation
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems (OB, WE, AG, AG, DMG, PS, SS), pp. 1698–1707.
DATE-2015-CastrillonTSSJA #manycore #programming #question
Multi/many-core programming: where are we standing? (JC, LT, LS, WS, BHHJ, MAM, AP, RJ, VR, RL), pp. 1708–1717.
DATE-2015-HamdiouiXNTBCJC #architecture #data-driven #in memory
Memristor based computation-in-memory architecture for data-intensive applications (SH, LX, HADN, MT, KB, HC, HJ, FC, DW, LE, JvL), pp. 1718–1725.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.