Travelled to:
1 × USA
Collaborated with:
A.Stoll
Talks about:
constraint (1) synthesi (1) level (1) exact (1) vhdl (1) time (1) high (1)
Person: Peter Duzy
DBLP: Duzy:Peter
Contributed to:
Wrote 1 papers:
- DAC-1992-StollD #constraints #synthesis
- High-Level Synthesis from VHDL with Exact Timing Constraints (AS, PD), pp. 188–193.