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Travelled to:
3 × USA
Collaborated with:
S.Sahni E.Shragowitz C.Lo K.Chiang S.Yao C.Cheng D.Dutt
Talks about:
effici (2) anneal (2) simul (2) time (2) combinatori (1) pitchmatch (1) extractor (1) algorithm (1) hierarch (1) compact (1)

Person: Surendra Nahar

DBLP DBLP: Nahar:Surendra

Contributed to:

DAC 19931993
DAC 19881988
DAC 19861986
DAC 19851985

Wrote 5 papers:

DAC-1993-YaoCDNL #using
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP (SZY, CKC, DD, SN, CYL), pp. 395–400.
DAC-1988-ChiangNL #algorithm #analysis #performance
Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2 (KWC, SN, CYL), pp. 471–475.
DAC-1986-NaharS #performance
A time and space efficient net extractor (SN, SS), pp. 411–417.
DAC-1986-NaharSS #combinator #optimisation
Simulated annealing and combinatorial optimization (SN, SS, ES), pp. 293–299.
Experiments with simulated annealing (SN, SS, ES), pp. 748–752.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.