BibSLEIGH — Proceedings of the 25th Design Automation Conference

Dennis W. Shaklee, A. Richard Newton
Proceedings of the 25th Design Automation Conference
DAC, 1988.

SYS

@proceedings{DAC-1988,
	acmid         = "285730",
	address       = "Anaheim, California, USA",
	editor        = "Dennis W. Shaklee and A. Richard Newton",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 25th Design Automation Conference}",
	year          = 1988,
}

Contents (129 items)

DAC-1988-Ross: Future Developments in Information Technology (IMR), p. 1.
DAC-1988-Newton #automation #design: Twenty-Five Years of Electronic Design Automation (ARN), p. 2.
DAC-1988-Stroud #approach #automation #logic #synthesis: An Automated BIST Approach for General Sequential Logic Synthesis (CES), pp. 3–8.
DAC-1988-KimTH #automation #hardware #using: Automatic Insertion of BIST Hardware Using VHDL (KK, JGT, DSH), pp. 9–15.
DAC-1988-GebotysE #design #synthesis #testing: VLSI Design Synthesis with Testability (CHG, MIE), pp. 16–21.
DAC-1988-WehnGCMR: A Defect-Tolerant and Fully Testable PLA (NW, MG, KC, PM, AR), pp. 22–33.
DAC-1988-AcostaAIR: The Role of VHDL in the MCC CAD System (RDA, MA, GI, BR), pp. 34–39.
DAC-1988-Coelho #named #standard: VHDL: A Call for Standards (DRC), pp. 40–47.
DAC-1988-AugustinGHLS #design #using #verification: Verification of VHDL Designs Using VAL (LMA, BAG, YH, DCL, AGS), pp. 48–53.
DAC-1988-ChenB #layout: A Module Area Estimator for VLSI Layout (XC, MLB), pp. 54–59.
DAC-1988-Zimmerman #estimation: A New Area and Shape Function Estimation Technique for VLSI Layouts (GZ), pp. 60–65.
DAC-1988-WimerKC: Optimal Aspect Ratios of Building Blocks in VLSI (SW, IK, IC), pp. 66–72.
DAC-1988-Sechen #metaprogramming #using: Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing (CS), pp. 73–80.
DAC-1988-Whalen #automation #delivery #design: Automating the Design of Electronic Packaging (BW), p. 81.
DAC-1988-Hodges: Opportunities in Computer Integrated Manufacturing (DAH), pp. 82–83.
DAC-1988-AgrawalCA #concurrent #contest #generative #named: Contest: A Concurrent Test Generator for Sequential Circuits (VDA, KTC, PA), pp. 84–89.
DAC-1988-GloverM #fault #generative #testing: A Method of Delay Fault Test Generation (CTG, MRM), pp. 90–95.
DAC-1988-Cheng #generative #testing: Split Circuit Model for Test Generation (WTC), pp. 96–101.
DAC-1988-BaerLMNSW #multi: A Notation for Describing Multiple Views of VLSI Circuits (JLB, MCL, LM, RN, LS, WW), pp. 102–107.
DAC-1988-DrongowskiBRIW #design #hardware #visual notation: A Graphical Hardware Design Language (PJD, JRB, RR, SI, THW), pp. 108–114.
DAC-1988-OdawaraTHOHO #compilation #interface: A Human Machine Interface for Silicon Compilation (GO, MT, KH, OO, TH, MO), pp. 115–120.
DAC-1988-KumarS #architecture #array #parallel: Parallel Placement on Reduced Array Architecture (CPR, SS), pp. 121–127.
DAC-1988-Zargham #parallel: Parallel Channel Routing (MRZ), pp. 128–133.
DAC-1988-CarlsonR #verification: Mask Verification on the Connection Machine (ECC, RAR), pp. 134–140.
DAC-1988-LiRS #logic #on the: On Path Selection in Combinational Logic Circuits (WNL, SMR, SS), pp. 142–147.
DAC-1988-Cherry #named: Pearl: A CMOS Timing Analyzer (JJC), pp. 148–153.
DAC-1988-WallaceS #named #verification: ATV: An Abstract Timing Verifier (DEW, CHS), pp. 154–159.
DAC-1988-BaileyS #empirical #parallel: An Empirical Study of On-chip Parallelism (MLB, LS), pp. 160–165.
DAC-1988-SouleB #logic #parallel #simulation: Parallel Logic Simulation on General Purpose Machines (LS, TB), pp. 166–171.
DAC-1988-Lewis #hardware #programmable #simulation: A Programmable Hardware Accelerator for Compiled Electrical Simulation (DML), pp. 172–177.
DAC-1988-HeynsN #recursion: Recursive Channel Router (WH, KVN), pp. 178–182.
DAC-1988-Cai #multi: Multi-Pads, Single Layer Power Net Routing in VLSI Circuits (HC), pp. 183–188.
DAC-1988-Rose #named #parallel #standard: LocusRoute: A Parallel Global Router for Standard Cells (JR), pp. 189–195.
DAC-1988-StavridouBE #case study #comparative #hardware #specification #verification: Formal Specification and Verification of Hardware: A Comparative Case Study (VS, HB, DAE), pp. 197–204.
DAC-1988-MadreB #behaviour #comparison #correctness #proving #using: Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour (JCM, JPB), pp. 205–210.
DAC-1988-NarendranS #image #verification: Formal Verification of the Sobel Image Processing Chip (PN, JS), pp. 211–217.
DAC-1988-BeeceDPV #verification: The IBM Engineering Verification Engine (DKB, GD, GP, FV), pp. 218–224.
DAC-1988-SaitohINKMHHK #logic #simulation #using: Logic Simulation System Using Simulation Processor (SP) (MS, KI, AN, MK, JM, HH, FH, NK), pp. 225–230.
DAC-1988-KazamaKNM #algorithm #evaluation #logic #performance #simulation: Algorithm for Vectorizing Logic Simulation and Evaluation of “VELVET” Performance (YK, YK, MN, HM), pp. 231–236.
DAC-1988-BarthS #design #representation: A Structural Representation for VLSI Design (RB, BS), pp. 237–242.
DAC-1988-BarthSS: Parameterized Schematics (RB, BS, PSS), pp. 243–249.
DAC-1988-BarthMS #layout #named: Patchwork: Layout from Schematic Annotations (RB, LM, BS), pp. 250–255.
DAC-1988-ChenP #database #design: A Database Management System for a VLSI Design System (GDC, TMP), pp. 257–262.
DAC-1988-Yang #database: An Enhanced Data Model for CAD/CAM Database Systems (YKY), pp. 263–268.
DAC-1988-GedyeK #database #design: Browsing in Chip Design Database (DG, RHK), pp. 269–274.
DAC-1988-ChouK #database #object-oriented: Versions and Change Notification in an Object-Oriented Database System (HTC, WK), pp. 275–281.
DAC-1988-ChangCS #performance: An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits (FCC, CFC, PS), pp. 282–287.
DAC-1988-SaabYH #modelling: Delay Modeling and Time of Bipolar Digital Circuits (DGS, ATY, INH), pp. 288–293.
DAC-1988-BurchNYH #analysis #estimation #independence #reliability: Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits (RB, FNN, PY, DEH), pp. 294–299.
DAC-1988-GuraA #simulation: Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics (CVG, JAA), pp. 300–305.
DAC-1988-LamD #performance: Performance of a New Annealing Schedule (JL, JMD), pp. 306–311.
DAC-1988-MallelaG #clustering #standard: Clustering Based Simulated Annealing for Standard Cell Placement (SM, LKG), pp. 312–317.
DAC-1988-TsayKH #algorithm #named #performance: Proud: A Fast Sea-of-Gates Placement Algorithm (RST, ESK, CPH), pp. 318–323.
DAC-1988-PillageR #metric #polynomial: A Quadratic Metric with a Simple Solution Scheme for Initial Placement (LTP, RAR), pp. 324–329.
DAC-1988-McFarlandPC #synthesis #tutorial: Tutorial on High-Level Synthesis (MCM, ACP, RC), pp. 330–336.
DAC-1988-ThomasDWRNB #architecture: The System Architect’s Workbench (DET, EMD, RAW, JVR, JAN, RLB), pp. 337–343.
DAC-1988-EklundT #database #design: A Context Mechanism to Control Sharing in a Design Database (DJE, FMT), pp. 344–350.
DAC-1988-WolfL #data transformation #modelling: Object Type Oriented Data Modeling for VLSI Data Management (PvdW, TGRvL), pp. 351–356.
DAC-1988-WidyaLW #concurrent #database #design: Concurrency Control in a VLSI Design Database (IW, TGRvL, PvdW), pp. 357–362.
DAC-1988-KonczykowskaB #automation #design: Automated Design Software for Switched-Capacitor IC’s with Symbolic Simulator SCYMBAL (AK, MB), pp. 363–368.
DAC-1988-BerkcandL #compilation: Analog Compilation Based on Successive Decompositions (EB, MAd, WL), pp. 369–375.
DAC-1988-VisweswariahCC #development #verification: Model Development and Verification for High Level Analog Blocks (CV, RC, CFC), pp. 376–382.
DAC-1988-Boyer #bibliography #layout #perspective: Symbolic Layout Compaction Review (DGB), pp. 383–389.
DAC-1988-Schiele #constraints #incremental: Compaction with Incremental Over-Constraint Resolution (WLS), pp. 390–395.
DAC-1988-MarpleSH #layout #performance: An Efficient Compactor for 45° Layout (DM, MS, HH), pp. 396–402.
DAC-1988-ZandenG #architecture #logic #named: MILO: A Microarchitecture and Logic Optimizer (NVZ, DG), pp. 403–408.
DAC-1988-WeiRJ #behaviour #named #synthesis: BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping (RSW, SGR, JYJ), pp. 409–414.
DAC-1988-TsengWRTB #behaviour #named #synthesis: Bridge: A Versatile Behavioral Synthesis System (CJT, RSW, SGR, MMT, AKB), pp. 415–420.
DAC-1988-WeyC #named: PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs (CLW, TYC), pp. 421–426.
DAC-1988-HelliwellP #algorithm #multi #performance: A Fast Algorithm to Minimize Multi-Output Mixed-Polarity Generalized Reed-Muller Forms (MH, MAP), pp. 427–432.
DAC-1988-WolfKA #algorithm #kernel #logic #multi: A Kernel-Finding State Assignment Algorithm for Multi-Level Logic (WW, KK, JA), pp. 433–438.
DAC-1988-ShiraishiSKTS #generative #logic: A High Packing Density Module Generator for CMOS Logic Cells (YS, JS, MK, AT, TS), pp. 439–444.
DAC-1988-BaltusA #generative #named #performance: SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit Schematics (DGB, JA), pp. 445–452.
DAC-1988-ObermeierK #layout #physics: An Electrical Optimizer that Considers Physical Layout (FWO, RHK), pp. 453–459.
DAC-1988-StarkH #network #power management #using: Analyzing CMOS Power Supply Networks Using Ariel (DS, MH), pp. 460–464.
DAC-1988-HenkelG #layout #named #set #verification: RISCE — A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification (VH, UG), pp. 465–470.
DAC-1988-ChiangNL #algorithm #analysis #performance: Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2 (KWC, SN, CYL), pp. 471–475.
DAC-1988-Bryant #design: CAD Tool Needs for System Designers (REB), p. 476.
DAC-1988-BorrielloD #synthesis: High-Level Synthesis: Current Status and Future Directions (GB, ED), pp. 477–482.
DAC-1988-MicheliK #named #synthesis: HERCULES — a System for High-Level Synthesis (GDM, DCK), pp. 483–488.
DAC-1988-Composano #compilation #design #process: Design Process Model in the Yorktown Silicon Compiler (RC), pp. 489–494.
DAC-1988-BeattyB #analysis #incremental #performance #using: Fast Incremental Circuit Analysis Using Extracted Hierarchy (DLB, REB), pp. 495–500.
DAC-1988-ChoiHB #algorithm #simulation: Incremental-in-time Algorithm for Digital Simulation (KC, SYH, TB), pp. 501–505.
DAC-1988-Adler #logic #simulation: A Dynamically-Directed Switch Model for MOS Logic Simulation (DA), pp. 506–511.
DAC-1988-TakashimaIKTSS #comparison #functional #morphism #rule-based: A Circuit Comparison System with Rule-Based Functional Isomorphism Checking (MT, AI, SK, TT, TS, JiS), pp. 512–516.
DAC-1988-Boehner #automation #logic #named: LOGEX — an Automatic Logic Extractor Form Transistor to Gate Level for CMOS Technology (MB), pp. 517–522.
DAC-1988-Papaspyrdis #prolog #verification: A Prolog-Based Connectivity Verification Tool (ACP), pp. 523–527.
DAC-1988-Dunlop #generative #question #standard: Will Cell Generation Displace Standard Cells? (AED), p. 528.
DAC-1988-BlackburnTK #behaviour #design: CORAL II: Linking Behavior and Structure in an IC Design System (RLB, DET, PMK), pp. 529–535.
DAC-1988-Pangre #approach #heuristic #named: Splicer: A Heuristic Approach to Connectivity Binding (BMP), pp. 536–541.
DAC-1988-JainPP #pipes and filters #synthesis: Module Selection for Pipelined Synthesis (RJ, ACP, NP), pp. 542–547.
DAC-1988-Razouk #modelling #petri net #pipes and filters: The Use of Petri Nets for Modeling Pipelined Processors (RRR), pp. 548–553.
DAC-1988-KuoCS #algorithm #performance: Fast Algorithm for Optimal Layer Assignment (YSK, TCC, WKS), pp. 554–559.
DAC-1988-Cai88a #layout: Connectivity Biased Channel Construction and Ordering for Building-Block Layout (HC), pp. 560–565.
DAC-1988-YaoYL #approach #problem: A New Approach to the Pin Assignment Problem (XY, MY, CLL), pp. 566–572.
DAC-1988-XiongK #design #problem: The Constrained Via Minimization Problem for PCB and VLSI Design (XMX, ESK), pp. 573–578.
DAC-1988-ChaoG #fault #modelling: Micro-operation Perturbations in Chip Level Fault Modeling (CHC, FGG), pp. 579–582.
DAC-1988-HillAHS #algorithm #fault #simulation: A New Two Task Algorithm for Clock Mode Fault Simulation in Sequential Circuits (FJH, EA, WKH, GQS), pp. 583–586.
DAC-1988-Cirit #analysis #random #testing: Switch Level Random Pattern Testability Analysis (MAC), pp. 587–590.
DAC-1988-MaoC #algorithm #generative #metric #named #self #testing #using: Dytest: A Self-Learning Algorithm Using Dynamic Testability Measures to Accelerate Test Generation (WM, MDC), pp. 591–596.
DAC-1988-GaedeRMB #automation #concurrent #named #parallel #testing #using: CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology (RKG, DER, MRM, KMB), pp. 597–600.
DAC-1988-HarelK #approach #fault #graph #simulation: A Graph Compaction Approach to Fault Simulation (DH, BK), pp. 601–604.
DAC-1988-LinH #automation #functional #generative: Automatic Functional Test Program Generation for Microprocessors (CSL, HFH), pp. 605–608.
DAC-1988-KuoF #configuration management #scalability: Spare Allocation and Reconfiguration in Large Area VLSI (SYK, WKF), pp. 609–612.
DAC-1988-Meyer #data type: A Data Structure for Circuit Net Lists (SM), pp. 613–616.
DAC-1988-HeydemannPD #architecture #simulation: The Architecture of a Highly Integrated Simulation System (MH, AP, DD), pp. 617–621.
DAC-1988-Diss #compilation: Circuit Compilers don’t have to be Slow (WCD), pp. 622–627.
DAC-1988-LyG #constraints #design #object-oriented: Constraint Propagation in an Object-Oriented IC Design Environment (TAL, EFG), pp. 628–633.
DAC-1988-Chang #automation #component #design #industrial: Design Automation for the Component Parts Industry (SSLC), pp. 634–637.
DAC-1988-Jabri #automation #graph: Automatic Building of Graphs for Rectangular Dualisation (MAJ), pp. 638–641.
DAC-1988-OgawaTK #automation #layout: Automatic Layout Procedures for Serial Routing Devices (YO, HT, TK), pp. 642–645.
DAC-1988-HartleyC #compilation: A Digit-Serial Silicon Compiler (RIH, PFC), pp. 646–649.
DAC-1988-HouOI #named: DECOMPOSER: A Synthesizer for Systolic Systems (PPH, RMO, MJI), pp. 650–653.
DAC-1988-BergstraesserGHW #architecture #named #synthesis #tool support: SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture (TB, JG, KH, SW), pp. 654–657.
DAC-1988-ChakravertiC #algorithm #array #metaprogramming: Routing Algorithm for Gate Array Macro Cells (AC, MJC), pp. 658–662.
DAC-1988-CongW #how: How to Obtain More Compactable Channel Routing Solutions (JC, DFW), pp. 663–666.
DAC-1988-Lunow #multi: A Channelless, Multilayer Router (REL), pp. 667–671.
DAC-1988-ArnoldS #interactive: An Interactive Maze Router with Hints (MHA, WSS), pp. 672–676.
DAC-1988-ChengD: Improved Channel Routing by Via Minimization and Shifting (CKC, DND), pp. 677–680.
DAC-1988-BhandariHS #problem #towards: The Min-cut Shuffle: Toward a Solution for the Global Effect Problem of Min-cut Placement (ISB, MH, DPS), pp. 681–685.
DAC-1988-DubaRAR #distributed #fault #simulation: Fault Simulation in a Distributed Environment (PAD, RKR, JAA, WAR), pp. 686–691.
DAC-1988-GaiMS #algorithm #concurrent #fault #performance #simulation: The Performance of the Concurrent Fault Simulation Algorithms in MOZART (SG, PLM, FS), pp. 692–697.
DAC-1988-MotoharaMUMS #approach #fault #performance #simulation: An Approach to Fast Hierarchical Fault Simulation (AM, MM, MU, YM, MS), pp. 698–703.
DAC-1988-Savir #design #verification #why: Why Partial Design Verification Works Better Than It Should (JS), pp. 704–707.
DAC-1988-LathropHDAK #abstraction #functional #roadmap: Advances in Functional Abstraction from Structure (RHL, RJH, GD, KMA, RSK), pp. 708–711.
DAC-1988-Hansen #compilation #hardware #logic #simulation: Hardware Logic Simulation by Compilation (CH), pp. 712–716.
DAC-1988-TakamineMNMK #algorithm #development: Clock Event Suppression Algorithm of VELVET and Its Application to S-820 Development (YT, SM, SN, MM, SK), pp. 716–719.
DAC-1988-YenGD #algorithm #analysis: A Path Selection Algorithm for Timing Analysis (HCY, SG, DHCD), pp. 720–723.
DAC-1988-Sherman #algorithm #analysis #generative: Algorithms for Timing Requirement Analysis and Generation (SKS), pp. 724–727.

Dennis W. Shaklee, A. Richard NewtonProceedings of the 25th Design Automation ConferenceDAC, 1988.

Contents (129 items)

Dennis W. Shaklee, A. Richard Newton
Proceedings of the 25th Design Automation Conference
DAC, 1988.