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Travelled to:
1 × Germany
1 × USA
Collaborated with:
N.Vijaykrishnan L.Li P.Mangalagiri Y.Xie K.Sarpatwari
Talks about:
architectur (1) simultan (1) frequenc (1) lifetim (1) partit (1) assign (1) fpga (1) flaw (1) chip (1) awar (1)

Person: Suresh Srinivasan

DBLP DBLP: Srinivasan:Suresh

Contributed to:

DAC 20062006
DATE 20052005

Wrote 2 papers:

DAC-2006-SrinivasanMXVS #named
FLAW: FPGA lifetime awareness (SS, PM, YX, NV, KS), pp. 630–635.
DATE-2005-SrinivasanLV #architecture #clustering
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures (SS, LL, NV), pp. 218–223.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.