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Travelled to:
1 × Germany
Collaborated with:
B.B.Sukhwani J.M.Wang
Talks about:
nanotechnolog (1) statist (1) equival (1) conduct (1) circuit (1) design (1) simul (1) wise (1) step (1) nano (1)

Person: Uday Padmanabhan

DBLP DBLP: Padmanabhan:Uday

Contributed to:

DATE 20052005

Wrote 1 papers:

DATE-2005-SukhwaniPW #design #named #statistics
Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design (BBS, UP, JMW), pp. 758–763.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.