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Travelled to:
1 × Germany
1 × USA
Collaborated with:
Y.Wu X.Yang T.Lam C.L.Zhou W.Lo
Talks about:
remov (2) wire (2) perturb (1) netlist (1) circuit (1) almost (1) solut (1) model (1) logic (1) fpgas (1)

Person: Wai-Chung Tang

DBLP DBLP: Tang:Wai=Chung

Contributed to:

DATE 20122012
DAC 20072007

Wrote 2 papers:

DATE-2012-YangLTW #modelling
Almost every wire is removable: A modeling and solution for removing any circuit wire (XY, TKL, WCT, YLW), pp. 1573–1578.
DAC-2007-ZhouTLW #how #logic
How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs (CLZ, WCT, WHL, YLW), pp. 922–927.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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