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Stem wire$ (all stems)

115 papers:

DATEDATE-2015-KarkarTMY #communication #distributed #multi
Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting (AK, KFT, TSTM, AY), pp. 794–799.
CSCWCSCW-2015-WhiteP
Expertise in the Wired Wild West (JIW, LP), pp. 662–675.
LCTESLCTES-2015-ProcterHGBA #design #hardware #implementation #semantics #verification
Semantics Driven Hardware Design, Implementation, and Verification with ReWire (AMP, WLH, IG, MB, GA), p. 10.
CASECASE-2014-SuKLLHKK #array #design #recognition
Design of tactile sensor array on electric gripper jaws for wire gripping recognition (JYS, WCK, YCL, CHL, JSH, HCK, CCK), pp. 1014–1019.
DACDAC-2014-LinRGDS #algorithm #performance
An Efficient Wire Routing and Wire Sizing Algorithm for Weight Minimization of Automotive Systems (CWL, LR, PG, JD, ALSV), p. 6.
DACDAC-2014-PengPL #optimisation #performance
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling (YP, DP, SKL), p. 6.
DATEDATE-2014-KarkarDATMY #architecture #communication #hybrid
Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip (AK, ND, RAD, KT, TSTM, AY), pp. 1–4.
DACDAC-2012-WeiSVLARHTKS #evaluation #named
GLARE: global and local wiring aware routability evaluation (YW, CCNS, NV, ZL, CJA, LNR, ADH, GET, DK, SSS), pp. 768–773.
DATEDATE-2012-YangCJTZ #multi #protocol #smarttech
A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system (GY, JC, FJ, HT, LRZ), pp. 443–448.
DATEDATE-2012-YangLTW #modelling
Almost every wire is removable: A modeling and solution for removing any circuit wire (XY, TKL, WCT, YLW), pp. 1573–1578.
DATEDATE-2011-PasettiCTSDSF
Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects (GP, NC, FT, RS, PD, SS, LF), pp. 1119–1120.
CASECASE-2010-EderK #design #framework
Design of an experimental platform for an X-by-wire car with four-wheel steering (ME, AK), pp. 656–661.
DATEDATE-2010-SchulzBUES #modelling #transaction
Transmitting TLM transactions over analogue wire models (SS, JB, TU, KE, SS), pp. 1608–1613.
VLDBVLDB-2010-WoodsTA #detection
Complex Event Detection at Wire Speed with FPGAs (LW, JT, GA), pp. 660–669.
CHICHI-2010-LiCEDL #automation #interactive #logic #named #prototype #testing
FrameWire: a tool for automatically extracting interaction logic from paper prototyping tests (YL, XC, KE, MD, JAL), pp. 503–512.
ICPRICPR-2010-CandamoGKG #detection #using
Detecting Wires in Cluttered Urban Scenes Using a Gaussian Model (JC, DBG, RK, SG), pp. 432–435.
KEODKEOD-2010-Occelli #policy
Reconciling Tempus and Hora — Policy Knowledge in an Information Wired Environment (SO), pp. 213–217.
VLDBVLDB-2009-MullerTA #compilation #query
Streams on Wires — A Query Compiler for FPGAs (RM, JT, GA), pp. 229–240.
PEPMPEPM-2009-SalamaMTGO #consistency #dependent type #using
Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions (CS, GM, WT, JG, JO), pp. 121–130.
DATEDATE-2008-ChenL #architecture
Wire Sizing Alternative — An Uniform Dual-rail Routing Architecture (FWC, YYL), pp. 796–799.
DATEDATE-2008-MelaniBMLDF #monitoring
Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring (MM, LB, MDM, PL, FD, LF), pp. 342–347.
ICPRICPR-2008-CandamoG #detection #video
Wire detection in low-altitude, urban, and low-quality video frames (JC, DBG), pp. 1–4.
DACDAC-2007-ChoXPP #named
TROY: Track Router with Yield-driven Wire Planning (MC, HX, RP, DZP), pp. 55–58.
DACDAC-2007-PimentelP #analysis
Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application (JRP, JP), pp. 290–293.
DACDAC-2007-RizzoM #concurrent
Concurrent Wire Spreading, Widening, and Filling (OR, HM), pp. 350–353.
DACDAC-2007-SundaresanM #analysis #distributed
An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires (KS, NRM), pp. 515–520.
DACDAC-2007-ZhaoPRFMCSY
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise (MZ, RP, BR, YF, TM, SC, SS, SY), pp. 162–167.
DATEDATE-2007-NiM #self
Self-heating-aware optimal wire sizing under Elmore delay model (MN, SOM), pp. 1373–1378.
DACDAC-2006-GuthausSB #programming #using
Clock buffer and wire sizing using sequential programming (MRG, DS, RBB), pp. 1041–1046.
DATEDATE-2006-LeeKKCY #adaptation #using
A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes (SJL, KK, HK, NC, HJY), pp. 79–80.
DATEDATE-2005-CasuM #design #pipes and filters
A New System Design Methodology for Wire Pipelined SoC (MRC, LM), pp. 944–945.
STOCSTOC-2005-KouckyPT #bound
Bounded-depth circuits: separating wires from gates (MK, PP, DT), pp. 257–265.
HPCAHPCA-2005-BalasubramonianMRV #architecture #performance
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures (RB, NM, KR, VV), pp. 28–39.
DACDAC-2004-LiuM #estimation
Pre-layout wire length and congestion estimation (QL, MMS), pp. 582–587.
DACDAC-2004-NookalaS
A method for correcting the functionality of a wire-pipelined circuit (VN, SSS), pp. 570–575.
DATEDATE-v2-2004-LinZ #fixpoint
Wire Retiming for System-on-Chip by Fixpoint Computation (CL, HZ), pp. 1092–1097.
ITiCSEITiCSE-2004-JippingKKL #network #programmable #using
Investigating wired and wireless networks using a java-based programmable sniffer (MJJ, AJK, NK, KL), pp. 12–16.
DACDAC-2003-HuM #clustering #predict
Wire length prediction based clustering and its application in placement (BH, MMS), pp. 800–805.
DATEDATE-2003-GoelM #architecture #design
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization (SKG, EJM), pp. 10738–10741.
DATEDATE-2003-HuangCW #nondeterminism
Global Wire Bus Configuration with Minimum Delay Uncertainty (LDH, HMC, DFW), pp. 10050–10055.
DATEDATE-2003-LaiYC #evaluation #performance
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees (STWL, EFYY, CCNC), pp. 10856–10861.
DATEDATE-2002-MacchiaruloMP #energy
Wire Placement for Crosstalk Energy Minimization in Address Buses (LM, EM, MP), pp. 158–162.
PEPMASIA-PEPM-2002-Amarasinghe #architecture #compilation
Defying the speed of light: : a spatially-aware compiler for wire-exposed architectures (SPA), p. 70.
ASPLOSASPLOS-2002-KimBK #adaptation
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (CK, DB, SWK), pp. 211–222.
DACDAC-2001-AlpertHSV #resource management
A Practical Methodology for Early Buffer and Wire Resource Allocation (CJA, JH, SSS, PV), pp. 189–194.
DACDAC-2001-DallyT #network
Route Packets, Not Wires: On-Chip Interconnection Networks (WJD, BT), pp. 684–689.
ITiCSEITiCSE-2001-CarnianiD #comprehension #education #network
The NetWire emulator: a tool for teaching and understanding networks (EC, RD), pp. 153–156.
DATEDATE-2000-GaoW #using
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model (YG, DFW), pp. 512–516.
ICLPCL-2000-ErdemLW #satisfiability
Wire Routing and Satisfiability Planning (EE, VL, MDFW), pp. 822–836.
DACDAC-1999-ChenM #using
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (CPC, NM), pp. 502–506.
DACDAC-1999-JiangJC #optimisation #performance
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation (IHRJ, JYJ, YWC), pp. 90–95.
DACDAC-1999-SaxenaL #using
Crosstalk Minimization Using Wire Perturbations (PS, CLL), pp. 100–103.
DACDAC-1999-YimK #design
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design (JSY, CMK), pp. 485–490.
DATEDATE-1998-ChuW #algorithm #polynomial
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing (CCNC, DFW), pp. 479–485.
DATEDATE-1998-GhoshKBH #benchmark #equivalence #invariant #metric #synthesis
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking (DG, NK, FB, JEHI), pp. 656–663.
DACDAC-1997-AlpertD
Wire Segmenting for Improved Buffer Insertion (CJA, AD), pp. 588–593.
DACDAC-1997-ChenW
Optimal Wire-Sizing Function with Fringing Capacitance Consideration (CPC, DFW), pp. 604–607.
DATEEDTC-1997-Fishburn
Shaping a VLSI wire to minimize Elmore delay (JPF), pp. 244–251.
DACDAC-1996-ChenCW96a
Optimal Wire-Sizing Formular Under the Elmore Delay Model (CPC, YPC, DFW), pp. 487–490.
DACDAC-1996-LillisCLH #performance #trade-off
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing (JL, CKC, TTYL, CYH), pp. 395–400.
DACDAC-1996-Park
A New Complete Diagnosis Patterns for Wiring Interconnects (SP), pp. 203–208.
DACDAC-1995-MehrotraFS #generative #performance
Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs (SM, PDF, MBS), pp. 381–387.
STOCSTOC-1994-BrewerCL #random #scalability
Scalable expanders: exploiting hierarchical random wiring (EAB, FTC, TL), pp. 144–152.
DACDAC-1993-ChenCHK #array
The Sea-of-Wires Array Aynthesis System (IYC, GLC, FJH, SYK), pp. 188–193.
DACDAC-1993-PullelaMP #optimisation #reliability #using
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization (SP, NM, LTP), pp. 165–170.
DACDAC-1992-ChungR #architecture #named
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections (KC, JR), pp. 361–367.
DACDAC-1992-FranzonSSBMM #generative #tool support
Tools to Aid in Wiring Rule Generation for High Speed Interconnects (PDF, SS, MBS, MB, SM, TM), pp. 466–471.
DACDAC-1992-HamadaCC #equation #estimation
A Wire Length Estimation Technique Utilizing Neighborhood Density Equations (TH, CKC, PMC), pp. 57–61.
FPCAFPCA-1991-MeijerFP #functional #lens #programming
Functional Programming with Bananas, Lenses, Envelopes and Barbed Wire (EM, MMF, RP), pp. 124–144.
DACDAC-1989-Groenveld #on the
On Global Wire Ordering for Macro-Cell Routing (PG), pp. 155–160.
DACDAC-1987-OdawaraHIYD #rule-based
A Rule-Based Placement System for Printed Wiring Boards (GO, TH, KI, TY, YD), pp. 777–785.
DACDAC-1986-LukTW #design
Hierarchial global wiring for custom chip design (WKL, DTT, CKW), pp. 481–489.
DACDAC-1986-TadaH #performance #scalability
Router system for printed wiring boards of very high-speed, very large-scale computers (TT, AH), pp. 791–797.
DACDAC-1985-OdawaraIW #knowledge-based
Knowledge-based placement technique for printed wiring boards (GO, KI, KW), pp. 616–622.
DACDAC-1984-Dupenloup #array
A wire routing scheme for double-layer cell arrays (GD), pp. 32–37.
DACDAC-1984-SastryP #logic #on the #slicing
On the relation between wire length distributions and placement of logic on master slice ICs (SS, ACP), pp. 710–711.
DACDAC-1983-Moulton
Laying the power and ground wires on a VLSI chip (ASM), pp. 754–755.
DACDAC-1983-Schiele
Improved compaction by minimized length of wires (WLS), pp. 121–127.
DACDAC-1982-NairHLV
Global wiring on a wire routing machine (RN, SJH, SL, RV), pp. 224–231.
DACDAC-1982-Robbins
Making the wire frame solid (DR), pp. 650–654.
DACDAC-1981-Hlynka #design
A simulator to replace wire rules for high speed computer design (AH), pp. 113–117.
DACDAC-1981-TsukiyamaKS #multi #on the #problem
On the layering problem of multilayer PWB wiring (ST, ESK, IS), pp. 738–745.
DACDAC-1981-WallaceH #probability
Some properties of a probabilistic model for global wiring (DW, LH), pp. 660–667.
STOCSTOC-1981-DolevKSSU
Optimal Wiring between Rectangles (DD, KK, AS, AS, JDU), pp. 312–317.
DACDAC-1980-NishiokaKNYCNFU #automation #multi
An automatic routing system for high density multilayer printed wiring boards (IN, TK, HN, SY, TC, TN, TF, MU), pp. 520–527.
DACDAC-1980-Skinner #interactive
Interactive wiring system (FDS), pp. 296–308.
STOCSTOC-1980-Tompa #problem
An Optimal Solution to a Wire-Routing Problem (Preliminary Version) (MT), pp. 161–176.
DACDAC-1979-Foster #lookahead #multi
A “lookahead” router for multilayer printed wiring boards (JCF), pp. 486–493.
DACDAC-1979-SaharaKN #interactive #layout
An interactive layout system of analog printed wiring boards (KiS, KiK, IN), pp. 506–512.
DACDAC-1979-WangB #automation
A software system for Automated Placement And Wiring of LSI chips (PTW, PB), pp. 327–329.
DACDAC-1978-NishiokaKYSO #approach
An approach to gate assignment and module placement for printed wiring boards (IN, TK, SY, IS, HO), pp. 60–69.
DACDAC-1977-ChenFKNS #automation #layout #problem
The chip layout problem: An automatic wiring procedure (KAC, MF, KHK, NN, SS), pp. 298–302.
DACDAC-1977-HellerMD #predict #requirements
Prediction of wiring space requirements for LSI (WRH, WFM, WED), pp. 32–42.
DACDAC-1977-NishiokaKN #automation #layout
A minicomputerized automatic layout system for two-layer printed wiring boards (IN, TK, HN), pp. 1–11.
DACDAC-1976-IkemotoSIK
Correction and wiring check-system for master-slice LSI (YI, TS, KI, HK), pp. 336–343.
DACDAC-1976-PiscatelliT
A solution to closeness checking of non-orthogonal printed circuit board wiring (RNP, PT), pp. 172–178.
DACDAC-1975-BrinsfieldT #design #multi
Computer aids for multilayer printed wiring board design (JGB, SRT), pp. 296–305.
DACDAC-1975-MironT #automation
The automatic printed wire routing system of BACKIS (GJM, SRT), pp. 311–316.
DACDAC-1975-Welt #layout #named
NOMAD: A printed wiring board layout system (MJW), pp. 152–161.
DACDAC-1974-CalafioreF #layout #multi
A system for multilayer printed wiring layout (RLC, JCF), pp. 322–326.
DACDAC-1974-Rubin
An iterative technique for printed wire routing (FR), pp. 308–313.
DACDAC-1974-SlemakerMLL #programmable
A programmable printed-wiring router (CSS, RCM, LWL, AGL), pp. 314–321.
DACDAC-1973-Foster #multi
A router for multilayer printed wiring backplanes (JCF), pp. 44–49.
DACDAC-1973-Rubin
Assigning wires to layers of a printed circuit board (FR), pp. 22–32.
DACDAC-1973-So #multi
Pin assignment of circuit cards and the routability of multilayer printed wiring backplanes (HCS), pp. 33–43.
DACDAC-1973-TokunagaKMLO #assembly #diagrams #named
WIDAS — Wiring Diagram Assembly System (MT, TK, MM, CL, FO), pp. 199–204.
DACDAC-1971-HashimotoS #optimisation #scalability
Wire routing by optimizing channel assignment within large apertures (AH, JGS), pp. 155–169.
DACDAC-1971-KriewallM #design #generative #interactive #named
CIBOL — an interactive graphics program used in the design of printed wiring boards and generation of associated artmasters (TJK, NRM), pp. 304–313.
DACDAC-1970-Koga
A checking method of wiring (YK), pp. 173–177.
DACDAC-1969-Garcia #integration
WICOP a wire integration computer program (LG), pp. 269–280.
DACDAC-1969-GinsbergMW #multi
An updated multilayer printed wiring C-A-D capability (GLG, CRMJ, EHW), pp. 145–154.
DACDAC-1969-Sr #modelling
Cellular wiring and the cellular modeling technique (RBHS), pp. 25–41.
DACDAC-1967-FreemanGRW #design #multi
Multilayer printed wiring — computer aided design (MFF, AG, MR, EAW).
DACDAC-1967-Richards #automation #equation #logic #named #programming #simulation
SWAP — a programming system for automatic simulation, wiring and placement of logical equations (DLR).
DACSHARE-1965-Frayne #problem
Three levels of the wiring interconnection problem (DKF).

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