Travelled to:1 × USA
2 × Germany
Collaborated with:R.Thompson I.Pomeranz S.M.Reddy M.Beck O.Barondeau M.Kaibel F.Poehl R.Press
Talks about:test (3) generat (2) design (2) clock (2) scan (2) implement (1) qualiti (1) partial (1) multipl (1) coverag (1)
Person: Xijiang Lin
DBLP: Lin:Xijiang
Contributed to:
2005
20031999Wrote 3 papers:
- DATE-2005-BeckBKPLP #design #generative #implementation #logic #quality
- Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality (MB, OB, MK, FP, XL, RP), pp. 56–61.
- DAC-2003-LinT #design #generative #multi #testing
- Test generation for designs with multiple clocks (XL, RT), pp. 662–667.
- DATE-1999-LinPR #fault
- Full Scan Fault Coverage With Partial Scan (XL, IP, SMR), pp. 468–472.