Stem clock$ (all stems)

250 papers:

CASE-2015-DepariFLS #industrial #network

Inexpensive SDR-based longwave radio controlled clock for time dissemination in industrial wireless sensor networks (AD, AF, ML, ES), pp. 125–130.

DAC-2015-DaiKB #equivalence

Sequential equivalence checking of clock-gated circuits (YYD, KYK, RKB), p. 6.

DAC-2015-EwetzJK #configuration management #design

Construction of reconfigurable clock trees for MCMM designs (RE, SJ, CKK), p. 6.

DAC-2015-HanLKNL #framework #multi #optimisation #reduction

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction (KH, JL, ABK, SN, JL), p. 6.

DATE-2015-ConstantinWKCB

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment (JC, LW, GK, AC, AB), pp. 381–386.

DATE-2015-GheolbanoiuPC #adaptation #hybrid

Hybrid adaptive clock management for FPGA processor acceleration (AG, LP, SC), pp. 1359–1364.

DATE-2015-LiuHDCPKKTR

Clock domain crossing aware sequential clock gating (JL, MSH, KTD, JYC, JP, MK, MK, NT, AR), pp. 1–6.

DATE-2015-SamieBHH #multi #online

Online binding of applications to multiple clock domains in shared FPGA-based systems (FS, LB, CMH, JH), pp. 25–30.

FASE-2015-NgoTGG #compilation #validation

Translation Validation for Clock Transformations in a Synchronous Compiler (VCN, JPT, TG, PLG), pp. 171–185.

SAC-2015-LeeKKE #algorithm #architecture #hybrid #memory management #named

M-CLOCK: migration-optimized page replacement algorithm for hybrid DRAM and PCM memory architecture (ML, DK, JK, YIE), pp. 2001–2006.

ICSE-v1-2015-YuanWWLYHFLCG #concurrent #debugging #named #using

ReCBuLC: Reproducing Concurrency Bugs Using Local Clocks (XY, CW, ZW, JL, PCY, JH, XF, YL, YC, YG), pp. 824–834.

CAV-2015-ErezN #automation #bound #graph #smt #using

Finding Bounded Path in Graph Using SMT for Automatic Clock Routing (AE, AN), pp. 20–36.

CASE-2014-HuangYTC #design #identification

Design of client device identification by clock skew in clouds (DJH, KTY, WCT, GMC), pp. 1133–1138.

DATE-2014-KufelWHAWM #embedded

Clock-modulation based watermark for protection of embedded processors (JK, PRW, SH, BMAH, PNW, JM), pp. 1–6.

DATE-2014-ParkKK #design #multi #synthesis

Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs (KP, GK, TK), pp. 1–4.

DATE-2014-YehHN #power management

Leakage-power-aware clock period minimization (HHY, SHH, YTN), pp. 1–6.

TACAS-2014-HerreraWP #network #query #reduction

Quasi-Equal Clock Reduction: More Networks, More Queries (CH, BW, AP), pp. 295–309.

FSE-2014-JiangZZZLSSGS #embedded #modelling #multi #named #synthesis #tool support #validation

Tsmart-GalsBlock: a toolkit for modeling, validation, and synthesis of multi-clocked embedded systems (YJ, HZ, HZ, XZ, HL, CS, XS, MG, JGS), pp. 711–714.

CC-2014-FeautrierVK #performance #source code

Improving the Performance of X10 Programs by Clock Removal (PF, EV, AK), pp. 113–132.

HPCA-2014-ZhaoVZLZ0 #memory management #specification

Over-clocked SSD: Safely running beyond flash memory chip I/O clock specs (KZ, KSV, XZ, JL, NZ, TZ), pp. 536–545.

DAC-2013-KahngKL #reduction

Smart non-default routing for clock power reduction (ABK, SK, HL), p. 7.

DAC-2013-KimJK #algorithm #problem

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem (JK, DJ, TK), p. 6.

DATE-2013-TuHC

Co-synthesis of data paths and clock control paths for minimum-period clock gating (WPT, SHH, CHC), pp. 1831–1836.

DATE-2013-YaoKLMK #named #network #physics

ClockPUF: physical unclonable functions based on clock networks (YY, MK, JL, ILM, FK), pp. 422–427.

STOC-2013-BuchbinderNS #clustering #exponential #multi #problem

Simplex partitioning via exponential clocks and the multiway cut problem (NB, JN, RS), pp. 535–544.

ICALP-v2-2013-FearnleyJ #automaton #reachability

Reachability in Two-Clock Timed Automata Is PSPACE-Complete (JF, MJ), pp. 212–223.

KDD-2013-LeeNBC #predict #social

Link prediction with social vector clocks (CL, BN, UB, PC), pp. 784–792.

ESEC-FSE-2013-JiangLZDSGS #design #embedded #multi #optimisation #using

Design and optimization of multi-clocked embedded systems using formal technique (YJ, ZL, HZ, YD, XS, MG, JS), pp. 703–706.

DAC-2012-ChenH #3d #synthesis

Clock tree synthesis with methodology of re-use in 3D IC (FWC, TH), pp. 1094–1099.

DAC-2012-HuCG #synthesis

Library-aware resonant clock synthesis (LARCS) (XH, WJC, MRG), pp. 145–150.

DATE-2012-Chaturvedi #static analysis

Static analysis of asynchronous clock domain crossings (SC), pp. 1122–1125.

DATE-2012-FanKGSH #design #integration

Exploring pausible clocking based GALS design for 40-nm system integration (XF, MK, EG, BS, CH), pp. 1118–1121.

DATE-2012-Gamatie #design #streaming #using

Design of streaming applications on MPSoCs using abstract clocks (AG), pp. 763–768.

DATE-2012-KarimiCGP #fault #generative #testing

Test generation for clock-domain crossing faults in integrated circuits (NK, KC, PG, SP), pp. 406–411.

DATE-2012-SassoneCMMPGMBR #dependence #network

Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks (AS, AC, AM, EM, MP, RG, VM, EB, SR), pp. 165–166.

DATE-2012-YeYZX #scheduling

Clock skew scheduling for timing speculation (RY, FY, HZ, QX), pp. 929–934.

ICPR-2012-Yu #locality #using #video

Localization and extraction of the four clock-digits using the knowledge of the digital video clock (XY), pp. 1217–1220.

DAC-2011-ChenO #fault #statistics

Diagnosing scan clock delay faults through statistical timing pruning (MC, AO), pp. 423–428.

DAC-2011-HuG #distributed #grid #synthesis

Distributed Resonant clOCK grid Synthesis (ROCKS) (XH, MRG), pp. 516–521.

DAC-2011-JooK #fine-grained #named

WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing (DJ, TK), pp. 522–527.

DAC-2011-LiLZ #multi #scheduling

Optimal multi-domain clock skew scheduling (LL, YL, HZ), pp. 152–157.

DAC-2011-LinH #satisfiability #using

Using SAT-based Craig interpolation to enlarge clock gating functions (THL, CY(H), pp. 621–626.

DAC-2011-LungSHSC #3d #fault tolerance #network

Fault-tolerant 3D clock network (CLL, YSS, SHH, YS, SCC), pp. 645–651.

DATE-2011-ButtrickK #3d #network #on the #testing #using

On testing prebond dies with incomplete clock networks in a 3D IC using DLLs (MB, SK), pp. 1418–1423.

DATE-2011-GaoHL #debugging #multi

Eliminating data invalidation in debugging multiple-clock chips (JG, YH, XL), pp. 691–696.

DATE-2011-HsuL #optimisation

Clock gating optimization with delay-matching (SJH, RBL), pp. 643–648.

DATE-2011-LuHCT #bound

Steiner tree based rotary clock routing with bounded skew and capacitive load balancing (JL, VH, XC, BT), pp. 455–460.

DATE-2011-MistryAFH #power management

Sub-clock power-gating technique for minimising leakage power during active mode (JNM, BMAH, DF, SH), pp. 106–111.

DATE-2011-SterponeCMWF #configuration management #power management

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.

DATE-2011-YangSSL #reduction #testing

A clock-gating based capture power droop reduction methodology for at-speed scan testing (BY, AS, SS, CL), pp. 197–203.

DATE-2011-ZhiLZYZZ #algorithm #multi #performance #scheduling

An efficient algorithm for multi-domain clock skew scheduling (YZ, WSL, HZ, CY, HZ, XZ), pp. 1364–1369.

CIAA-2011-OrtizLS #automaton #distributed

Distributed Event Clock Automata — Extended Abstract (JJO, AL, PYS), pp. 250–263.

QAPL-2011-Rutkowski #automaton #game studies

Two-Player Reachability-Price Games on Single-Clock Timed Automata (MR), pp. 31–46.

LCTES-2011-GamatieG #design #embedded #multi #performance #source code #static analysis

Static analysis of synchronous programs in signal for efficient design of multi-clocked embedded systems (AG, LG), pp. 71–80.

DAC-2010-ChenDC #synthesis

Clock tree synthesis under aggressive buffer insertion (YYC, CD, DC), pp. 86–89.

DAC-2010-GuthausWR #linear #optimisation #programming

Non-uniform clock mesh optimization with linear programming buffer insertion (MRG, GW, RR), pp. 74–79.

DAC-2010-KimK #3d #design #synthesis #testing

Clock tree synthesis with pre-bond testability for 3D stacked IC designs (TYK, TK), pp. 723–728.

DAC-2010-ShihC #independence #performance #synthesis

Fast timing-model independent buffered clock-tree synthesis (XWS, YWC), pp. 80–85.

DATE-2010-HallerB #low cost #performance

High-speed clock recovery for low-cost FPGAs (IH, ZFB), pp. 610–613.

DATE-2010-JanapsatyaIPP #adaptation #algorithm #policy

Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm (AJ, AI, JP, SP), pp. 920–925.

DATE-2010-LeeM #named #network #optimisation

Contango: Integrated optimization of SoC clock networks (DL, ILM), pp. 1468–1473.

DATE-2010-LeeYCC #embedded #metric

An embedded wide-range and high-resolution CLOCK jitter measurement circuit (YL, CYY, NCDC, JJC), pp. 1637–1640.

DATE-2010-LongM10a #dependence #scheduling

Inversed Temperature Dependence aware clock skew scheduling for sequential circuits (JL, SOM), pp. 1657–1660.

DATE-2010-LungZCC #optimisation

Clock skew optimization considering complicated power modes (CLL, ZYZ, CHC, SCC), pp. 1474–1479.

DATE-2010-PeiLL #generative #testing

An on-chip clock generation scheme for faster-than-at-speed delay testing (SP, HL, XL), pp. 1353–1356.

DATE-2010-SrinivasJ #clustering #graph #performance

Clock gating approaches by IOEX graphs and cluster efficiency plots (JS, SJ), pp. 638–641.

DATE-2010-SuCG #multi

A general method to make multi-clock system deterministic (MS, YC, XG), pp. 1480–1485.

DATE-2010-TieDWC #performance #reduction #scheduling

Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement (MT, HD, TW, XC), pp. 520–525.

DATE-2010-WuM #scheduling

Clock skew scheduling for soft-error-tolerant sequential circuits (KCW, DM), pp. 717–722.

ICPR-2010-AhmadNSNN #distributed #estimation #network #on the

On Clock Offset Estimation in Wireless Sensor Networks with Weibull Distributed Network Delays (AA, AN, ES, HNN, MNN), pp. 2322–2325.

LICS-2010-EndrullisHK #combinator #composition #fixpoint

Modular Construction of Fixed Point Combinators and Clocked Bohm Trees (JE, DH, JWK), pp. 111–119.

CASE-2009-FagioliniMB #distributed

Set-valued consensus for distributed clock synchronization (AF, SM, AB), pp. 116–121.

DAC-2009-ArbelER

Resurrecting infeasible clock-gating functions (EA, CE, OR), pp. 160–165.

DAC-2009-ChattopadhyayZ #configuration management

Serial reconfigurable mismatch-tolerant clock distribution (AC, ZZ), pp. 611–612.

DAC-2009-JangK

Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization (HJ, TK), pp. 794–799.

DAC-2009-OnaissiHN #optimisation #process

Clock skew optimization via wiresizing for timing sign-off covering all process corners (SO, KRH, FNN), pp. 196–201.

DAC-2009-TuncerCL #adaptation

Enabling adaptability through elastic clocks (ET, JC, LL), pp. 8–10.

DATE-2009-BaeMV #scheduling

Exploiting clock skew scheduling for FPGA (SB, PM, NV), pp. 1524–1529.

DATE-2009-BolzaniCMMP #concurrent #design #industrial #power management

Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.

DATE-2009-ChakrabortyGRP #analysis #optimisation

Analysis and optimization of NBTI induced clock skew in gated clock trees (AC, GG, AR, DZP), pp. 296–299.

DATE-2009-FlynnGG #configuration management

Bitstream relocation with local clock domains for partially reconfigurable FPGAs (AF, AGR, ADG), pp. 300–303.

DATE-2009-MohammadZadehMJZ #multi #network

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network (NM, MM, AJ, MSZ), pp. 833–838.

DATE-2009-NagarajK #case study #process

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation (KN, SK), pp. 292–295.

DATE-2009-SinhaRBS #design #multi #protocol #using

Multi-clock Soc design using protocol conversion (RS, PSR, SB, ZS), pp. 123–128.

LATA-2009-VerwerWW #automaton

One-Clock Deterministic Timed Automata Are Efficiently Identifiable in the Limit (SV, MdW, CW), pp. 740–751.

FM-2009-HeidarianSV #analysis #network #protocol

Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks (FH, JS, FWV), pp. 516–531.

SAC-2009-LeeBPCLN #configuration management #named #precise

CPS-SIM: configurable and accurate clock precision solid state drive simulator (JL, EB, HP, JC, DL, SHN), pp. 318–325.

CC-2009-VasudevanTDE #analysis #concurrent #source code

Compile-Time Analysis and Specialization of Clocks in Concurrent Programs (NV, OT, JD, SAE), pp. 48–62.

CASE-2008-ScheitererNOSG #performance #precise #protocol

Synchronization performance of the Precision Time Protocol in the face of slave clock frequency drift (RLS, CN, DO, GS, DG), pp. 554–559.

DAC-2008-ChangHHLWL

Type-matching clock tree for zero skew clock gating (CMC, SHH, YKH, JZL, HPW, YSL), pp. 714–719.

DAC-2008-FraerKM #paradigm #synthesis

A new paradigm for synthesis and propagation of clock gating conditions (RF, GK, MKM), pp. 658–663.

DAC-2008-Hurst #automation #logic #synthesis

Automatic synthesis of clock gating logic with controlled netlist perturbation (APH), pp. 654–657.

DAC-2008-MohalikRDRSPJ #analysis #embedded #latency #model checking #realtime

Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts (SM, ACR, MGD, SR, PVS, PKP, SJ), pp. 296–299.

DAC-2008-NiM #power management #reduction #scheduling

Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction (MN, SOM), pp. 610–613.

DAC-2008-OgrasMM #adaptation #feedback #multi

Variation-adaptive feedback control for networks-on-chip with multiple clock domains (ÜYO, RM, DM), pp. 614–619.

DAC-2008-RajaramP #design #robust #synthesis

Robust chip-level clock tree synthesis for SOC designs (AR, DZP), pp. 720–723.

DAC-2008-WangLZTYTCN #scheduling

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays (YW, WSL, XZ, JT, CY, JT, WC, JN), pp. 223–226.

DATE-2008-ChattopadhyayZ #debugging #online

Built-in Clock Skew System for On-line Debug and Repair (AC, ZZ), pp. 248–251.

DATE-2008-CorderoK #using

Clock Distribution Scheme using Coplanar Transmission Lines (VHCC, SPK), pp. 985–990.

DATE-2008-GhoshNR #adaptation #fault tolerance #novel #using

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking (SG, PN, KR), pp. 366–371.

DATE-2008-ZhangZYZSPZCMSIC #multi #network

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.

ITiCSE-2008-NorrisBFRR #developer #how #named

ClockIt: collecting quantitative data on how beginning software developers really work (CN, EFB, JBFJ, KR, JR), pp. 37–41.

FM-2008-KitchinPM #distributed #logic #simulation

Simulation, Orchestration and Logical Clocks (DK, EP, JM), p. 34.

ICPR-2008-YuLL #detection #recognition #robust #video

Robust time recognition of video clock based on digit transition detection and digit-sequence recognition (XY, YL, WSL), pp. 1–4.

LCTES-2008-BiernackiCHP #code generation #composition #data flow

Clock-directed modular code generation for synchronous data-flow languages (DB, JLC, GH, MP), pp. 121–130.

LICS-2008-BaierBBBG #automaton #infinity #model checking

Almost-Sure Model Checking of Infinite Paths in One-Clock Timed Automata (CB, NB, PB, TB, MG), pp. 217–226.

DAC-2007-HuangCCN

Clock Period Minimization with Minimum Delay Insertion (SHH, CHC, CMC, YTN), pp. 970–975.

DAC-2007-RoyMC #nondeterminism

Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew (AR, NHM, MHC), pp. 184–187.

DAC-2007-YuL #design

Design of Rotary Clock Based Circuits (ZY, XL), pp. 43–48.

DATE-2007-BjerregaardSS #architecture #scalability

A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method (TB, MBS, JS), pp. 648–653.

DATE-2007-ButtSRPS #optimisation #synthesis

System level clock tree synthesis for power optimization (SAB, SS, JR, AP, ES), pp. 1677–1682.

DATE-2007-FengZTC #design #fault #metric #validation

Clock domain crossing fault model and coverage metric for validation of SoC design (YF, ZZ, DT, XC), pp. 1385–1390.

DATE-2007-MondalRKRLVM #3d #robust

Thermally robust clocking schemes for 3D integrated circuits (MM, AJR, SK, TR, GML, NV, YM), pp. 1206–1211.

DATE-2007-SirowyWLV07a #multi

Clock-frequency assignment for multiple clock domain systems-on-a-chip (SS, YW, SL, FV), pp. 397–402.

FoSSaCS-2007-BouyerLM #automaton #model checking

Model-Checking One-Clock Priced Timed Automata (PB, KGL, NM), pp. 108–122.

TACAS-2007-JurdzinskiLS #automaton #model checking #probability

Model Checking Probabilistic Timed Automata with One or Two Clocks (MJ, FL, JS), pp. 170–184.

DAC-2006-GuthausSB #programming #using

Clock buffer and wire sizing using sequential programming (MRG, DS, RBB), pp. 1041–1046.

DAC-2006-HuangCNY

Register binding for clock period minimization (SHH, CHC, YTN, WCY), pp. 439–444.

DAC-2006-WangDC #approach #named #scheduling #tool support

ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling (KW, LD, XC), pp. 951–954.

DATE-2006-Albrecht #incremental #latency #performance #scalability #scheduling

Efficient incremental clock latency scheduling for large circuits (CA), pp. 1091–1096.

DATE-2006-BanerjeeRMB #fine-grained #logic #power management #synthesis #using

Low power synthesis of dynamic logic circuits using fine-grained clock gating (NB, KR, HMM, SB), pp. 862–867.

DATE-2006-CarbognaniBFKF #power management

Two-phase resonant clocking for ultra-low-power hearing aid applications (FC, FB, NF, HK, WF), pp. 73–78.

DATE-2006-ChakrabortySDMMP #bound #optimisation

Thermal resilient bounded-skew clock tree optimization methodology (AC, PS, KD, AM, EM, MP), pp. 832–837.

DATE-2006-HuangG #fault

Diagnosis of defects on scan enable and clock trees (YH, KG), pp. 436–437.

DATE-2006-KimH

Associative skew clock routing for difficult instances (MSK, JH), pp. 762–767.

DATE-2006-LiuI #optimisation #scheduling #using

Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking (CL, VI), pp. 652–657.

DATE-2006-ReddyWM #architecture #nondeterminism

Analyzing timing uncertainty in mesh-based clock architectures (SMR, GRW, RM), pp. 1097–1102.

DATE-2006-VenkataramanHLS #optimisation

Integrated placement and skew optimization for rotary clocking (GV, JH, FL, CCNS), pp. 756–761.

DATE-2006-YonedaMF #multi #scheduling

Power-constrained test scheduling for multi-clock domain SoCs (TY, KM, HF), pp. 297–302.

DATE-DF-2006-CarvalhoPJF #algorithm #fault tolerance #implementation

A practical implementation of the fault-tolerant daisy-chain clock synchronization algorithm on CAN (FCC, CEP, ETSJ, EPdF), pp. 189–194.

SAS-2006-Bertrane #communication #proving

Proving the Properties of Communicating Imperfectly-Clocked Synchronous Systems (JB), pp. 370–386.

ICPR-v4-2006-LiXWYY #recognition #reliability #video

Reliable Video Clock Time Recognition (YL, CX, KW, XY, XY), pp. 128–131.

DAC-2005-HuangNL #scheduling

Race-condition-aware clock skew scheduling (SHH, YTN, FPL), pp. 475–478.

DAC-2005-LuoYYB #design #network #power management #using

Low power network processor design using clock gating (YL, JY, JY, LNB), pp. 712–715.

DAC-2005-LuSHZCHH #navigation #network

Navigating registers in placement for clock network minimization (YL, CCNS, XH, QZ, YC, LH, JH), pp. 176–181.

DAC-2005-NiehHH

Minimizing peak current via opposite-phase clock tree (YTN, SHH, SYH), pp. 182–185.

DATE-2005-BeckBKPLP #design #generative #implementation #logic #quality

Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality (MB, OB, MK, FP, XL, RP), pp. 56–61.

DATE-2005-ChandyC #interactive #performance

Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions (AC, TC), pp. 984–985.

DATE-2005-MullerTAL #design #multi #power management #top-down

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit (PM, AT, SMA, YL), pp. 258–263.

DATE-2005-VargheseCY #analysis #using

Systematic Analysis of Active Clock Deskewing Systems Using Control Theory (VV, TC, PMY), pp. 820–825.

HPCA-2005-JacobsonBHBZEEGLST #performance

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors (HMJ, PB, ZH, AB, VVZ, RJE, LE, JG, DL, BS, JMT), pp. 238–242.

HPCA-2005-WuJMC #adaptation #multi

Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors (QW, PJ, MM, DWC), pp. 178–189.

DAC-2004-RajaramHM #variability

Reducing clock skew variability via cross links (AR, JH, RNM), pp. 18–23.

DAC-2004-WangM #constraints #power management

Buffer sizing for clock power minimization subject to general skew constraints (KW, MMS), pp. 159–164.

DATE-DF-2004-DiazS #physics

Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit (JCD, MS), pp. 134–139.

DATE-v1-2004-BabighianBM #algorithm #scalability

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks (PB, LB, EM), pp. 500–505.

DATE-v1-2004-BadarogluWPDGM #reduction

Digital Ground Bounce Reduction by Phase Modulation of the Clock (MB, PW, GVdP, SD, GGEG, HDM), pp. 88–93.

DATE-v1-2004-XuN #design #multi #testing

Wrapper Design for Testing IP Cores with Multiple Clock Domains (QX, NN), pp. 416–421.

DATE-v2-2004-SinghT #architecture #multi

Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures (MS, MT), pp. 1008–1013.

TACAS-2004-LugiezNZ #approach #automaton #explosion #partial order #problem #semantics

A Partial Order Semantics Approach to the Clock Explosion Problem of Timed Automata (DL, PN, SZ), pp. 296–311.

AdaEurope-2004-ZamoranoAPP #ada #implementation

Implementing Execution-Time Clocks for the Ada Ravenscar Profile (JZ, AA, JAP, JAdlP), pp. 132–143.

ASPLOS-2004-WuJMC #multi #online

Formal online methods for voltage/frequency control in multiple clock domain microprocessors (QW, PJ, MM, DWC), pp. 248–259.

LICS-2004-AbdullaDM #multi #network

Multi-Clock Timed Networks (PAA, JD, PM), pp. 345–354.

DAC-2003-DonnoIBM #optimisation

Clock-tree power optimization based on RTL clock-gating (MD, AI, LB, EM), pp. 622–627.

DAC-2003-Heydari

Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators (PH), pp. 532–537.

DAC-2003-LinT #design #generative #multi #testing

Test generation for designs with multiple clocks (XL, RT), pp. 662–667.

DAC-2003-ManeatisKMMS #generative #multi #self

Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL (JGM, JK, IM, JM, MS), pp. 688–690.

DAC-2003-OMahonyYHW #design #network #using

Design of a 10GHz clock distribution network using coupled standing-wave oscillators (FO, CPY, MH, SSW), pp. 682–687.

DAC-2003-SengerMMGKGB

A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference (RMS, EDM, MSM, FHG, KLK, MRG, RBB), pp. 520–525.

DATE-2003-SirisantanaR #logic #power management

Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies (NS, KR), pp. 11160–11161.

DATE-2003-VelenisPF #network #nondeterminism #performance

Reduced Delay Uncertainty in High Performance Clock Distribution Networks (DV, MCP, EGF), pp. 10068–10075.

TACAS-2003-FersmanMPY #analysis #scheduling #using

Schedulability Analysis Using Two Clocks (EF, LM, PP, WY), pp. 224–239.

ICALP-2003-EisnerFHMC

The Definition of a Temporal Clock Operator (CE, DF, JH, AM, DVC), pp. 857–870.

AdaEurope-2003-GonzalezH #ada

A Proposal to Integrate the POSIX Execution-Time Clocks into Ada 95 (FJMG, MGH), pp. 344–358.

HPCA-2003-LiBCVR #reduction

Deterministic Clock Gating for Microprocessor Power Reduction (HL, SB, YC, TNV, KR), pp. 113–122.

DAC-2002-AbramoviciYR #low cost

Low-cost sequential ATPG with clock-control DFT (MA, XY, EMR), pp. 243–248.

DAC-2002-BadarogluTDWMVG #optimisation #reduction #using

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.

DAC-2002-JungKK #logic

Low-swing clock domino logic incorporating dual supply and dual threshold voltages (SOJ, KWK, SMK), pp. 467–472.

DAC-2002-LiouWCDMKW #fault #multi #performance #testing #using

Enhancing test efficiency for delay fault testing using multiple-clocked schemes (JJL, LCW, KTC, JD, MRM, RK, TWW), pp. 371–374.

DAC-2002-RakhmatovVC #scalability

Battery-conscious task sequencing for portable devices including voltage/clock scaling (DNR, SBKV, CC), pp. 189–194.

DAC-2002-SanderJ #communication #design #refinement

Transformation based communication and clock domain refinement for system design (IS, AJ), pp. 281–286.

DATE-2002-HassounCC #verification

Verifying Clock Schedules in the Presence of Cross Talk (SH, ECG, CC), pp. 346–350.

DATE-2002-MukherjeeWCM #component

Sizing Power/Ground Meshes for Clocking and Computing Circuit Components (AM, KW, LHC, MMS), pp. 176–183.

ICGT-2002-GyapayHV #graph transformation #logic

Graph Transformation with Time: Causality and Logical Clocks (SG, RH, DV), pp. 120–134.

HPCA-2002-SemeraroMBADS #design #energy #multi #scalability #using

Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling (GS, GM, RB, DHA, SD, MLS), pp. 29–42.

DAC-2001-SavojR #communication #design

Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems (JS, BR), pp. 121–126.

DATE-2001-SaitohAT #clustering #performance #scheduling

Clustering based fast clock scheduling for light clock-tree (MS, MA, AT), pp. 240–245.

AdaEurope-2001-ZamoranoRP #ada #implementation #kernel #realtime

Implementing Ada.Real_Time.Clock and Absolute Delays in Real-Time Kernels (JZ, JFR, JAdlP), pp. 317–327.

CAV-2001-Dang #analysis #automaton #reachability

Binary Reachability Analysis of Pushdown Timed Automata with Dense Clocks (ZD), pp. 506–518.

DAC-2000-LiuNPS

Impact of interconnect variations on the clock skew of a gigahertz microprocessor (YL, SRN, LTP, AJS), pp. 168–171.

DAC-2000-NouraniCP

Synthesis-for-testability of controller-datapath pairs that use gated clocks (MN, JC, CAP), pp. 613–618.

DAC-2000-RaoN #power management #using

Power minimization using control generated clocks (MSR, SKN), pp. 794–799.

DATE-2000-CiricYS #implementation #logic #using

Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic (JC, GY, CS), pp. 277–282.

DATE-2000-DemirF #evaluation #modelling #performance #probability

Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits (AD, PF), pp. 340–344.

DATE-2000-SchonherrS #algorithm #automation #equivalence

Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level (JS, BS), p. 759.

OSDI-2000-GrunwaldLFMN #policy #scheduling

Policies for Dynamic Clock Scheduling (DG, PL, KIF, CBMI, MN), pp. 73–86.

CAV-2000-AnnichiniAB #parametricity #reasoning

Symbolic Techniques for Parametric Reasoning about Counter and Clock Systems (AA, EA, AB), pp. 419–434.

DAC-1999-HemaniMKPONOEL #design #power management #using

Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style (AH, TM, SK, AP, TO, PN, JÖ, PE, DL), pp. 873–878.

DAC-1999-LiuPF #performance #scheduling

Maximizing Performance by Retiming and Clock Skew Scheduling (XL, MCP, EGF), pp. 231–236.

DAC-1999-YimBK

A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (JSY, SOB, CMK), pp. 766–771.

DATE-1999-SantosoMRA #generative #named #testing #using

FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy (YS, MCM, EMR, MA), p. 747–?.

DATE-1999-ShinKK #bound #multi #testing

At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks (JS, HK, SK), p. 473–?.

FASE-1999-AttanasioCI #performance #realtime #specification

Yet Another Real-Time Specification for the Steam Boiler: Local Clocks to Statically Measure Systems Performance (CA, FC, PI), pp. 45–59.

FM-v2-1999-SmarandacheGG #calculus #constraints #realtime #validation

Validation of Mixed SIGNAL-ALPHA Real-Time Systems through Affine Calculus on Clock Synchronisation Constraints (IMS, TG, PLG), pp. 1364–1383.

HPCA-1999-CondonHPS #memory management #modelling #using

Using Lamport Clocks to Reason about Relaxed Memory Models (AC, MDH, MP, DJS), pp. 270–278.

CAV-1999-BehrmannLPWY #analysis #diagrams #difference #performance #reachability #using

Efficient Timed Reachability Analysis Using Clock Difference Diagrams (GB, KGL, JP, CW, WY), pp. 341–353.

DATE-1998-MaheshwariS #performance #scalability

Efficient Minarea Retiming of Large Level-Clocked Circuits (NM, SSS), pp. 840–845.

DATE-1998-Mutz #modelling

Register Transfer Level VHDL Models without Clocks (MM), pp. 153–158.

DATE-1998-OhP

Gated Clock Routing Minimizing the Switched Capacitance (JO, MP), pp. 692–697.

FM-1998-GeserK #verification

Structured Formal Verification of a Fragment of the IBM S/390 Clock Chip (AG, WK), pp. 92–106.

AdaEurope-1998-HarbourRGG #ada #execution #implementation #realtime #using

Implementing and Using Execution Time Clocks in Ada Hard Real-Time Applications (MGH, MAR, JJGG, JCPG), pp. 90–101.

HPDC-1998-ZhangSL #message passing #source code #using

Dynamically Instrumenting Message-Passing Programs Using Virtual Clocks (KZ, CS, KCL), pp. 340–341.

DAC-1997-CongW #pipes and filters #synthesis

FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (JC, CW), pp. 644–649.

DAC-1997-KahngT #bound

More Practical Bounded-Skew Clock Routing (ABK, CWAT), pp. 594–599.

DAC-1997-RainaBNMB #design #performance #testing

Efficient Testing of Clock Regenerator Circuits in Scan Designs (RR, RB, CN, RFM, CB), pp. 95–100.

EDTC-1997-BeniniMMPS #logic #network #optimisation #synthesis

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (LB, GDM, EM, MP, RS), pp. 514–520.

EDTC-1997-FavalliM #testing

Testing scheme for IC’s clocks (MF, CM), pp. 445–449.

TACAS-1997-RaskinS #abstraction #logic #realtime

Real-Time Logics: Fictitious Clock as an Abstraction of Dense Time (JFR, PYS), pp. 165–182.

DAC-1996-ChenCW #optimisation #performance

Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation (CPC, YWC, DFW), pp. 405–408.

DAC-1996-DesaiCJ #cpu #network #performance

Sizing of Clock Distribution Networks for High Performance CPU Chips (MPD, RC, JJ), pp. 389–394.

DAC-1996-NevesF #process #scheduling

Optimal Clock Skew Scheduling Tolerant to Process Variations (JLN, EGF), pp. 623–628.

DAC-1996-PanL

Optimal Clock Period FPGA Technology Mapping for Sequential Circuits (PP, CLL), pp. 720–725.

DAC-1996-PapachristouSN #design #effectiveness #multi #power management

An Effective Power Management Scheme for RTL Design Based on Multiple Clocks (CAP, MS, MN), pp. 337–342.

DAC-1996-XiD #design #power management

Useful-Skew Clock Routing With Gate Sizing for Low Power Design (JGX, WWMD), pp. 383–388.

DAC-1995-DeokarS #fresh look #optimisation

A Fresh Look at Retiming Via Clock Skew Optimization (RBD, SSS), pp. 310–315.

DAC-1995-HuangKT #bound #on the #problem

On the Bounded-Skew Clock and Steiner Routing Problems (DJHH, ABK, CWAT), pp. 508–513.

DAC-1995-JainBJ #abstraction #automation

Automatic Clock Abstraction from Sequential Circuits (SJ, REB, AJ), pp. 707–711.

DAC-1995-VittalM #design

Power Optimal Buffered Clock Tree Design (AV, MMS), pp. 497–502.

DAC-1995-XiD #power management #process

Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution (JGX, WWMD), pp. 491–496.

SIGMOD-1995-AdyaGLM #concurrent #performance #using

Efficient Optimistic Concurrency Control Using Loosely Synchronized Clocks (AA, RG, BL, UM), pp. 23–34.

PEPM-1995-Jensen #analysis #data flow #source code

Clock Analysis of Synchronous Dataflow Programs (TPJ), pp. 156–167.

ICALP-1995-HenzingerKW #power of

The Expressive Power of Clocks (TAH, PWK, HWT), pp. 417–428.

DAC-1994-BhattacharyaDB #optimisation #resource management

Clock Period Optimization During Resource Sharing and Assignment (SB, SD, FB), pp. 195–200.

DAC-1994-FangG #low cost #testing

Clock Grouping: A Low Cost DFT Methodology for Delay Testing (WCF, SKG), pp. 94–99.

DAC-1994-LiuSC #clustering #data flow #latency

Data Flow Partitioning for Clock Period and Latency Minimization (LTL, MS, CKC), pp. 658–663.

DAC-1994-ZhuW94a

Clock Skew Minimization During FPGA Placement (KZ, DFW), pp. 232–237.

ESOP-1994-AndersenM #algebra #multi

An Asynchronous Algebra with Multiple Clocks (HRA, MM), pp. 58–73.

STOC-1994-Patt-ShamirR #formal method

A theory of clock synchronization (extended abstract) (BPS, SR), pp. 810–819.

ASPLOS-1994-UptonHMB #resource management

Resource Allocation in a High Clock Rate Microprocessor (MU, TH, TNM, RBB), pp. 98–109.

DAC-1993-ChoS #algorithm #performance

A Nuffer Distribution Algorithm for High-Speed Clock Routing (JDC, MS), pp. 537–543.

DAC-1993-KawarabayashiSS #verification

A Verification Technique for Gated Clock (MK, NVS, ALSV), pp. 123–127.

DAC-1993-PapaefthymiouR #named

TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry (MCP, KHR), pp. 497–502.

DAC-1993-PullelaMP #optimisation #reliability #using

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization (SP, NM, LTP), pp. 165–170.

ECOOP-1993-SatohT #calculus #distributed

A Timed Calculus for Distributed Objects with Clocks (IS, MT), pp. 326–345.

DAC-1992-ChaoHH

Zero Skew Clock Net Routing (THC, YCH, JMH), pp. 518–523.

DAC-1992-Szymanski

Computing Optimal Clock Schedules (TGS), pp. 399–404.

ICALP-1992-HenzingerMP #question #what

What Good Are Digital Clocks? (TAH, ZM, AP), pp. 545–558.

DAC-1991-JoyC #multi

Placement for Clock Period Minimization With Multiple Wave Propagation (DAJ, MJC), pp. 640–643.

DAC-1991-KahngCR #geometry #recursion

High-Performance Clock Routing Based on Recursive Geometric Aatching (ABK, JC, GR), pp. 322–327.

DAC-1990-JacksonSK

Clock Routing for High-Performance ICs (MABJ, AS, ESK), pp. 573–579.

LICS-1990-HarelLP #logic

Explicit Clock Temporal Logic (EH, OL, AP), pp. 402–413.

DAC-1988-HillAHS #algorithm #fault #simulation

A New Two Task Algorithm for Clock Mode Fault Simulation in Sequential Circuits (FJH, EA, WKH, GQS), pp. 583–586.

DAC-1988-TakamineMNMK #algorithm #development

Clock Event Suppression Algorithm of VELVET and Its Application to S-820 Development (YT, SM, SN, MM, SK), pp. 716–719.

DAC-1987-CanrightH #logic

Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic (REC, ARH), pp. 133–139.

SLP-1987-GorlickK87 #prolog #source code

Timing Prolog Programs without Clock (MMG, CK), pp. 426–434.

DAC-1985-Chan #analysis #development #multi #network

Development of a timing analysis program for multiple clocked network (EC), pp. 816–819.

DAC-1985-ParkP #synthesis

Synthesis of optimal clocking schemes (NP, ACP), pp. 489–495.

STOC-1984-DolevHS #on the

On the Possibility and Impossibility of Achieving Clock Synchronization (DD, JYH, HRS), pp. 504–511.

DAC-1983-Ulrich #concurrent #design #simulation #verification

A design verification methodology based on concurrent simulation and clock suppression (EU), pp. 709–712.

SOSP-1981-CarrH #algorithm #effectiveness #memory management #named

WSClock — A Simple and Effective Algorithm for Virtual Memory Management (RWC, JLH), pp. 87–95.