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Collaborated with:
T.Shinsha T.Kubo J.Koshishita K.Ishihara
Talks about:
logic (2) increment (1) synthesi (1) structur (1) identif (1) gate (1)

Person: Y. Sakataya

DBLP DBLP: Sakataya:Y=

Contributed to:

DAC 19861986

Wrote 1 papers:

DAC-1986-ShinshaKSKI #identification #incremental #logic #synthesis
Incremental logic synthesis through gate logic structure identification (TS, TK, YS, JK, KI), pp. 391–397.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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