9 papers:
ASPLOS-2004-WangCWKGCYSMS #framework #multi #thread- Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform (PHW, JDC, HW, DK, BG, KMC, ABY, TS, SFM, JPS), pp. 144–155.
CGO-2004-LukMPCL #architecture #named- Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture (CKL, RM, HP, RSC, PGL), pp. 15–26.
- CGO-2004-Winkel #performance #scheduling
- Exploring the Performance Potential of Itanium® Processors with ILP-based Scheduling (SW), pp. 189–200.
DAC-2003-StinsonR #generative- A 1.5GHz third generation itanium® 2 processor (JS, SR), pp. 706–709.
WCRE-2003-SnavelyDA #bytecode #reverse engineering- Unscheduling, Unpredication, Unspeculation: Reverse Engineering Itanium Executables (NS, SKD, GRA), pp. 4–13.
- CGO-2003-CollardL #optimisation
- Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor (JFC, DML), pp. 105–114.
- CGO-2003-SettleCHL #architecture #optimisation #stack
- Optimization for the Intel® Itanium ®Architectur Register Stack (AS, DAC, GH, DML), pp. 115–124.
- CGO-2003-Thomas
- Inlining of Mathematical Functions in HP-UX for Itanium ® 2 (JWT), pp. 135–148.
HPCA-2002-WangWCGKS #execution #memory management- Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation (PHW, HW, JDC, EG, RMK, JPS), pp. 187–196.
