BibSLEIGH corpus
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Used together with:
optim (3)
larg (2)
structur (1)
nanoelectron (1)
allevi (1)

Stem plas$ (all stems)

11 papers:

DATEDATE-2007-RaoOK #fault tolerance #interactive #logic
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs (WR, AO, RK), pp. 865–869.
River PLAs: a regular circuit structure (FM, RKB), pp. 201–206.
Crosstalk Alleviation for Dynamic PLAs (TKT, TKT, SCC), pp. 683–687.
DACDAC-1990-UpadhyayaT #case study
BIST PLAs, Pass or Fail — A Case Study (SJU, JAT), pp. 724–727.
DACDAC-1990-WeyDC #design
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement (CLW, JD, TYC), pp. 327–332.
DACDAC-1988-WeyC #named
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs (CLW, TYC), pp. 421–426.
DACDAC-1985-Hedlund #optimisation
Electrical optimization of PLAs (KSH), pp. 681–687.
DACDAC-1983-Chuquillanqui #problem #scalability
Internal connection problem in large optimized PLAs (SC), pp. 795–802.
DACDAC-1982-ChuquillanquiS #named #optimisation #scalability
PAOLA: A tool for topological optimization of large PLAS (SC, TPS), pp. 300–306.
Silicon compilation-a hierarchical use of PLAs (RA), pp. 314–326.
DACDAC-1978-Cha #testing
A testing strategy for PLAs (CWC), pp. 326–334.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.