BibSLEIGH
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Used together with:
toler (3)
fault (3)
approach (2)
challeng (2)
research (1)

Stem nanoelectron$ (all stems)

6 papers:

DATEDATE-2011-HaronH #fault tolerance #hybrid #low cost
Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories (NZH, SH), pp. 265–268.
DATEDATE-2010-Antoniadis #challenge
Nanoelectronics challenges for the 21st century (DA), p. 1487.
DACDAC-2009-Welser #challenge #industrial #motivation #research
The semiconductor industry’s nanoelectronics research initiative: motivation and challenges (JW), pp. 298–300.
DATEDATE-2008-RaoO #fault tolerance #parallel #towards
Towards fault tolerant parallel prefix adders in nanoelectronic systems (WR, AO), pp. 360–365.
DATEDATE-2007-RaoOK #fault tolerance #interactive #logic
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs (WR, AO, RK), pp. 865–869.
DATEDATE-2006-SoffkeZMG #analysis #approach #combinator #statistics
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits (OS, PZ, TM, MG), pp. 632–637.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.