4 papers:
DATE-2008-BinkleyGGR #design- From Transistor to PLL — Analogue Design and EDA Methods (DB, HEG, GGEG, JSR).
DAC-2003-ManeatisKMMS #generative #multi #self- Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL (JGM, JK, IM, JM, MS), pp. 688–690.
- DATE-2003-MounirMF #automation #behaviour #performance #verification
- Automatic Behavioural Model Calibration for Efficient PLL System Verification (AM, AM, MF), pp. 20280–20285.
- DAC-2002-Perrott #behaviour #performance #simulation
- Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits (MHP), pp. 498–503.
