BibSLEIGH
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Used together with:
rout (1)
buffer (1)
skew (1)
optim (1)
sign (1)

Stem wires$ (all stems)

2 papers:

DACDAC-2009-OnaissiHN #optimisation #process
Clock skew optimization via wiresizing for timing sign-off covering all process corners (SO, KRH, FNN), pp. 196–201.
DACDAC-2000-LaiW
Maze routing with buffer insertion and wiresizing (ML, DFW), pp. 374–378.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.