Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling
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Daniel Thiele, Philip Axer, Rolf Ernst
Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling
DAC, 2015.

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@inproceedings{DAC-2015-ThieleAE,
	author        = "Daniel Thiele and Philip Axer and Rolf Ernst",
	booktitle     = "{Proceedings of the 52nd Annual Design Automation Conference}",
	doi           = "10.1145/2744769.2744854",
	isbn          = "978-1-4503-3520-1",
	pages         = "6",
	publisher     = "{ACM}",
	title         = "{Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling}",
	year          = 2015,
}

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