Proceedings of the 52nd Annual Design Automation Conference
DAC, 2015.
@proceedings{DAC-2015, acmid = "2744769", address = "San Francisco, California, USA", isbn = "978-1-4503-3520-1", publisher = "{ACM}", title = "{Proceedings of the 52nd Annual Design Automation Conference}", year = 2015, }
Contents (200 items)
- DAC-2015-Bowen #performance #quality
- Walking a thin line: performance and quality grading vs. yield overcut (CB), p. 2.
- DAC-2015-Hayes #challenge #probability
- Introduction to stochastic computing and its challenges (JPH), p. 3.
- DAC-2015-ShererRO #functional #safety
- Ensuring functional safety compliance for ISO 26262 (ADS, JR, RO), p. 3.
- DAC-2015-WolfF #architecture #continuation #question #what
- What don’t we know about CPS architectures? (MW, EF), p. 4.
- DAC-2015-LiuWLCWBQ #challenge #design #security
- Cloning your mind: security challenges in cognitive system designs and their solutions (BL, CW, HL, YC, QW, MB, QQ), p. 5.
- DAC-2015-SeshiaSS #formal method
- Formal methods for semi-autonomous driving (SAS, DS, SSS), p. 5.
- DAC-2015-AgostaBPS #information management
- Information leakage chaff: feeding red herrings to side channel attackers (GA, AB, GP, MS), p. 6.
- DAC-2015-AsadJ #programming #using #verification
- Verifying inevitability of phase-locking in a charge pump phase lock loop using sum of squares programming (HuA, KDJ), p. 6.
- DAC-2015-BadrTG #hybrid #synthesis
- Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias (YB, AT, PG), p. 6.
- DAC-2015-BalajiFDGA #abstraction #architecture #cyber-physical #modelling
- Models, abstractions, and architectures: the missing links in cyber-physical systems (BB, MAAF, NDD, RKG, YA), p. 6.
- DAC-2015-BeaulieuSSTWW #lightweight
- The SIMON and SPECK lightweight block ciphers (RB, DS, JS, STC, BW, LW), p. 6.
- DAC-2015-BeckertE #design #independence #realtime
- Designing time partitions for real-time hypervisor with sufficient temporal independence (MB, RE), p. 6.
- DAC-2015-BockHKS #algorithm #modelling
- Local search algorithms for timing-driven placement under arbitrary delay models (AB, SH, NK, US), p. 6.
- DAC-2015-BokhariJSHP #architecture #manycore #named
- SuperNet: multimode interconnect architecture for manycore chips (HB, HJ, MS, JH, SP), p. 6.
- DAC-2015-BrasserMSWK #named #trust
- TyTAN: tiny trust anchor for tiny devices (FFB, BEM, ARS, CW, PK), p. 6.
- DAC-2015-BuiniPG #automation #cyber-physical #design #modelling #physics #variability
- Including variability of physical models into the design automation of cyber-physical systems (HMB, SP, TG), p. 6.
- DAC-2015-CampbellLMC #debugging #detection #fault #hybrid #synthesis #using #validation
- Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles (KAC, DL, SM, DC), p. 6.
- DAC-2015-CampbellVPC #detection #fault #low cost #synthesis
- High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths (KAC, PV, DZP, DC), p. 6.
- DAC-2015-CavigelliMB #embedded #network #realtime
- Accelerating real-time embedded scene labeling with convolutional networks (LC, MM, LB), p. 6.
- DAC-2015-ChaariENTK #approach #modelling #safety
- A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems (MC, WE, CN, BAT, TK), p. 6.
- DAC-2015-ChangCKLL #memory management #performance
- Achieving SLC performance with MLC flash memory (YMC, YHC, TWK, YCL, HPL), p. 6.
- DAC-2015-ChangHLW #analysis #encoding #functional #named
- TA-FTA: transition-aware functional timing analysis with a four-valued encoding (JCCC, RHMH, LYZL, CHPW), p. 6.
- DAC-2015-ChangLF #challenge
- EUV and e-beam manufacturability: challenges and solutions (YWC, RGL, SYF), p. 6.
- DAC-2015-ChanNKDS #2d #3d #estimation #implementation
- 3DIC benefit estimation and implementation guidance from 2DIC implementation (WTJC, SN, ABK, YD, KS), p. 6.
- DAC-2015-ChenC #architecture
- Routing-architecture-aware analytical placement for heterogeneous FPGAs (SYC, YWC), p. 6.
- DAC-2015-ChenCX #classification #named #power management #video
- DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification (XC, YC, CJX), p. 6.
- DAC-2015-ChengZZ0SI
- Core vs. uncore: the heart of darkness (HYC, JZ, JZ, YX, JS, MJI), p. 6.
- DAC-2015-ChenH #equivalence #logic #probability
- Equivalence among stochastic logic circuits and its application (THC, JPH), p. 6.
- DAC-2015-ChenMRC #execution #paradigm #performance
- Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks (HC, DM, SR, KC), p. 6.
- DAC-2015-ChenSC #flexibility
- A SPICE model of flexible transition metal dichalcogenide field-effect transistors (YYC, ZS, DC), p. 6.
- DAC-2015-ChenSZDJ #optimisation
- Optimizing data placement for reducing shift operations on domain wall memories (XC, EHMS, QZ, PD, WJ), p. 6.
- DAC-2015-ChenTSHK #analysis #modelling #multi #reliability
- Interconnect reliability modeling and analysis for multi-branch interconnect trees (HBC, SXDT, VS, XH, TK), p. 6.
- DAC-2015-ChiangCLJ #design #power management #scalability
- Scalable sequence-constrained retention register minimization in power gating design (TWC, KHC, YTL, JHRJ), p. 6.
- DAC-2015-ChoCSM #component #comprehension #fault
- Understanding soft errors in uncore components (HC, CYC, TS, SM), p. 6.
- DAC-2015-ChungRPG #energy #memory management
- Domain wall memory based digital signal processors for area and energy-efficiency (JC, KR, JP, SG), p. 6.
- DAC-2015-CiesielskiYBLR #verification
- Verification of gate-level arithmetic circuits by function extraction (MJC, CY, WB, DL, AR), p. 6.
- DAC-2015-CongGHRY #architecture #network
- On-chip interconnection network for accelerator-rich architectures (JC, MG, YH, GR, BY), p. 6.
- DAC-2015-CuiWCZNP #energy #grid #smarttech
- Optimal control of PEVs for energy cost minimization and frequency regulation in the smart grid accounting for battery state-of-health degradation (TC, YW, SC, QZ, SN, MP), p. 6.
- DAC-2015-DaiKB #equivalence
- Sequential equivalence checking of clock-gated circuits (YYD, KYK, RKB), p. 6.
- DAC-2015-DaviHPSKSAJ #named
- HAFIX: hardware-assisted flow integrity extension (LD, MH, DP, ARS, PK, DS, OA, YJ), p. 6.
- DAC-2015-DingCM #self
- Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography (YD, CCNC, WKM), p. 6.
- DAC-2015-DingCZ #algorithm #invariant #performance
- An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT (YD, CCNC, XZ), p. 6.
- DAC-2015-DunbarQ
- A practical circuit fingerprinting method utilizing observability don’t care conditions (CD, GQ), p. 6.
- DAC-2015-DuraisamyKCLPMM #energy #manycore #performance #pipes and filters #platform
- Energy efficient MapReduce with VFI-enabled multicore platforms (KD, RGK, WC, GL, PPP, RM, DM), p. 6.
- DAC-2015-Engblom #integration #platform #using
- Virtual to the (near) end: using virtual platforms for continuous integration (JE), p. 6.
- DAC-2015-EspinosaHAAR #analysis #correlation #robust #set #verification
- Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification (JE, CH, JA, DdA, JCR), p. 6.
- DAC-2015-EwetzJK #configuration management #design
- Construction of reconfigurable clock trees for MCMM designs (RE, SJ, CKK), p. 6.
- DAC-2015-FernandezJAQVC #bound #realtime
- Increasing confidence on measurement-based contention bounds for real-time round-robin buses (GF, JJ, JA, EQ, TV, FJC), p. 6.
- DAC-2015-FernandezJAQVC15a #manycore #off the shelf #resource management
- Resource usage templates and signatures for COTS multicore processors (GF, JJ, JA, EQ, TV, FJC), p. 6.
- DAC-2015-Foster #functional #industrial #roadmap #verification
- Trends in functional verification: a 2014 industry study (HDF), p. 6.
- DAC-2015-GanapathyKTB #fault
- Mitigating the impact of faults in unreliable memories for error-resilient applications (SG, GK, AT, AB), p. 6.
- DAC-2015-GangopadhyayNR #power management
- Integrated power management in IoT devices under wide dynamic ranges of operation (SG, SBN, AR), p. 6.
- DAC-2015-GnadSKRSH #named #variability
- Hayat: harnessing dark silicon and variability for aging deceleration and balancing (DG, MS, FK, SR, DS, JH), p. 6.
- DAC-2015-GrafRGTP #architecture #component #design #platform #robust
- Robust design of E/E architecture component platforms (SG, SR, MG, JT, DP), p. 6.
- DAC-2015-GuoDJFM #formal method #perspective #security #validation #verification
- Pre-silicon security verification and validation: a formal perspective (XG, RGD, YJ, FF, PM), p. 6.
- DAC-2015-GuoTFD #anti #obfuscation #reverse engineering
- Investigation of obfuscation-based anti-reverse engineering for printed circuit boards (ZG, MT, DF, JD), p. 6.
- DAC-2015-GuoWHWLC #design #latency #named #novel #reduction
- FlexLevel: a novel NAND flash storage system design for LDPC latency reduction (JG, WW, JH, DW, HL, YC), p. 6.
- DAC-2015-GuSZCH #embedded #memory management #performance
- Area and performance co-optimization for domain wall memory in application-specific embedded systems (SG, EHMS, QZ, YC, JH), p. 6.
- DAC-2015-HahnKL #garbage collection
- To collect or not to collect: just-in-time garbage collection for high-performance SSDs with long lifetimes (SSH, JK, SL), p. 6.
- DAC-2015-HanF #analysis #approach #cpu #gpu #graph #scalability
- Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems (LH, ZF), p. 6.
- DAC-2015-HanKL #design #evaluation #using
- Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router (KH, ABK, HL), p. 6.
- DAC-2015-HanLKNL #framework #multi #optimisation #reduction
- A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction (KH, JL, ABK, SN, JL), p. 6.
- DAC-2015-HelalBH #parallel #simulation #using
- Parallel circuit simulation using the direct method on a heterogeneous cloud (AEH, AMB, YYH), p. 6.
- DAC-2015-HenkelKPS #roadmap
- New trends in dark silicon (JH, HK, SP, MS), p. 6.
- DAC-2015-HerdtLD #simulation #using #verification
- Verifying SystemC using stateful symbolic simulation (VH, HML, RD), p. 6.
- DAC-2015-HeyseS
- Avoiding transitional effects in dynamic circuit specialisation on FPGAs (KH, DS), p. 6.
- DAC-2015-HuangCZL #behaviour #named #realtime #scheduling
- PASS: priority assignment of real-time tasks with dynamic suspending behavior under fixed-priority scheduling (WHH, JJC, HZ, CL), p. 6.
- DAC-2015-HuangFYZL #estimation #multi #performance
- Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits (QH, CF, FY, XZ, XL), p. 6.
- DAC-2015-IsmailLS #performance #worst-case
- Improving worst-case cache performance through selective bypassing and register-indexed cache (MI, DL, GES), p. 6.
- DAC-2015-JangKGY0 #design
- Bandwidth-efficient on-chip interconnect designs for GPGPUs (HJ, JK, PG, KHY, EJK), p. 6.
- DAC-2015-JangPGB #self
- Self-correcting STTRAM under magnetic field attacks (JWJ, JP, SG, SB), p. 6.
- DAC-2015-JassiMS #delivery #design #grammarware #integration #named
- GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs (MJ, DMG, US), p. 6.
- DAC-2015-JiangLZYW #effectiveness #feature model #image #performance
- A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction (GJ, LL, WZ, SY, SW), p. 6.
- DAC-2015-JiangWS #clustering #power management #sorting
- A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space (ZJ, QW, MS), p. 6.
- DAC-2015-JungC #embedded #multi #named #performance #platform #simulation
- ΣVP: host-GPU multiplexing for efficient simulation of multiple embedded GPUs on virtual platforms (YJ, LPC), p. 6.
- DAC-2015-KadjoAKG #approach #cpu #energy #gpu #mobile #performance #platform
- A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms (DK, RA, MK, PVG), p. 6.
- DAC-2015-KagalwallaG #effectiveness #modelling #reduction
- Effective model-based mask fracturing for mask cost reduction (AAK, PG), p. 6.
- DAC-2015-Kahng #game studies
- New game, new goal posts: a recent history of timing closure (ABK), p. 6.
- DAC-2015-KashyapGS #design #reliability
- Achieving power and reliability sign-off for automotive semiconductor designs (AK, SG, SS), p. 6.
- DAC-2015-KehrQBS #communication #execution #legacy #manycore #parallel
- Parallel execution of AUTOSAR legacy applications on multicore ECUs with timed implicit communication (SK, EQ, BB, GS), p. 6.
- DAC-2015-KhdrPSH #resource management
- Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips (HK, SP, MS, JH), p. 6.
- DAC-2015-KimLRJR
- Vibration-based secure side channel for medical devices (YK, WSL, VR, NKJ, AR), p. 6.
- DAC-2015-KleebergerRC #design #verification
- Design & verification of automotive SoC firmware (VBK, SR, RC), p. 6.
- DAC-2015-KlineXMJ #energy #memory management
- Domain-wall memory buffer for low-energy NoCs (DKJ, HX, RGM, AKJ), p. 6.
- DAC-2015-KoJKLS #design #guidelines
- Guidelines to design parity protected write-back L1 data cache (YK, RJ, YK, KL, AS), p. 6.
- DAC-2015-KonukMMRSTZ #design
- Design for low test pattern counts (HK, EKM, NM, JR, DS, JT, JZ), p. 6.
- DAC-2015-KrishnaNRT #analysis #composition #modelling #product line
- Compositional modeling and analysis of automotive feature product lines (SNK, GKN, SR, AT), p. 6.
- DAC-2015-LahiouelZT #smt #towards #using
- Towards enhancing analog circuits sizing using SMT-based techniques (OL, MHZ, ST), p. 6.
- DAC-2015-LeeCC #mobile
- Evaluating battery aging on mobile devices (JL, YC, HC), p. 6.
- DAC-2015-LeeHLP #data flow #debugging #information management #interface #performance
- Efficient dynamic information flow tracking on a processor with core debug interface (JL, IH, YL, YP), p. 6.
- DAC-2015-LeeNL #optimisation #performance
- Optimizing stream program performance on CGRA-based systems (HL, DN, JL), p. 6.
- DAC-2015-LiBTO #communication #energy #performance
- Complementary communication path for energy efficient on-chip optical interconnects (HL, SLB, YT, IO), p. 6.
- DAC-2015-LiCSHLWY #hybrid #power management
- A STT-RAM-based low-power hybrid register file for GPGPUs (GL, XC, GS, HH, YL, YW, HY), p. 6.
- DAC-2015-LiLSH #approximate #optimisation #precise #synthesis
- Joint precision optimization and high level synthesis for approximate computing (CL, WL, SSS, JH), p. 6.
- DAC-2015-LinYP #constraints #performance
- High performance dummy fill insertion with coupling and uniformity constraints (YL, BY, DZP), p. 6.
- DAC-2015-LiuHWSJHL #assessment #detection #smarttech
- Impact assessment of net metering on smart home cyberattack detection (YL, SH, JW, YS, YJ, YH, XL), p. 6.
- DAC-2015-LiuKDK #data access #network #reduction
- Network footprint reduction through data access and computation placement in NoC-based manycores (JL, JK, WD, MTK), p. 6.
- DAC-2015-LiuLCLWH #named
- Vortex: variation-aware training for memristor X-bar (BL, HL, YC, XL, QW, TH), p. 6.
- DAC-2015-LiuLLWLMLCJ0SY #energy
- Ambient energy harvesting nonvolatile processors: from circuit to system (YL, ZL, HL, YW, XL, KM, SL, MFC, SJ, YX, JS, HY), p. 6.
- DAC-2015-LiuMLLCLWJBWY #configuration management #design #named
- RENO: a high-efficient reconfigurable neuromorphic computing accelerator design (XL, MM, BL, HL, YC, BL, YW, HJ, MB, QW, JY), p. 6.
- DAC-2015-LiuSZLQ #generative #statistics
- A statistical methodology for noise sensor placement and full-chip voltage map generation (XL, SS, PZ, XL, HQ), p. 6.
- DAC-2015-LiuYYSLLCLWJ #design
- A spiking neuromorphic design with resistive crossbar (CL, BY, CY, LS, ZL, BL, YC, HL, QW, HJ), p. 6.
- DAC-2015-LiuZ #configuration management #performance
- A reconfigurable analog substrate for highly efficient maximum flow computation (GL, ZZ), p. 6.
- DAC-2015-LiuZWYX #analysis #difference #encryption #fault #named
- DERA: yet another differential fault attack on cryptographic devices based on error rate analysis (YL, JZ, LW, FY, QX), p. 6.
- DAC-2015-LiXGWY #interface
- Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system (BL, LX, PG, YW, HY), p. 6.
- DAC-2015-LiZHLHX #automation #compilation #performance #stack
- Compiler directed automatic stack trimming for efficient non-volatile processors (QL, MZ, JH, YL, YH, CJX), p. 6.
- DAC-2015-LukasiewyczSS #design #embedded #performance #platform
- Efficient design space exploration of embedded platforms (ML, FS, SS), p. 6.
- DAC-2015-MaoHCL #named
- VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications (MM, JH, YC, HL), p. 6.
- DAC-2015-McLaughlin #behaviour #policy
- Blocking unsafe behaviors in control systems through static and dynamic policy enforcement (SM), p. 6.
- DAC-2015-MengYOLW #array #clustering #data access #memory management #parallel #performance
- Efficient memory partitioning for parallel data access in multidimensional arrays (CM, SY, PO, LL, SW), p. 6.
- DAC-2015-MilutinovicQAC #estimation #named #performance
- PACO: fast average-performance estimation for time-randomized caches (SM, EQ, JA, FJC), p. 6.
- DAC-2015-MiuraFNHHA #concept
- EM attack sensor: concept, circuit, and design-automation methodology (NM, DF, MN, NH, YiH, TA), p. 6.
- DAC-2015-MundhenkSLFC #analysis #architecture #model checking #probability #security #using
- Security analysis of automotive architectures using probabilistic model checking (PM, SS, ML, SAF, SC), p. 6.
- DAC-2015-NishimiyaSS #evaluation #functional #interface #mockup #modelling #network
- Evaluation of functional mock-up interface for vehicle power network modeling (KN, TS, SS), p. 6.
- DAC-2015-OuTC #self
- Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography (HCO, KHT, YWC), p. 6.
- DAC-2015-OuTLWC
- Layout-dependent-effects-aware analytical analog placement (HCO, KHT, JYL, IPW, YWC), p. 6.
- DAC-2015-PalerD #fault tolerance #quantum
- An introduction into fault-tolerant quantum computing (AP, SJD), p. 6.
- DAC-2015-PanLYXL #multi #question
- Pushing multiple patterning in sub-10nm: are we ready? (DZP, LL, BY, XX, YL), p. 6.
- DAC-2015-PanthSDL #3d #clustering #delivery #mobile #power management #trade-off
- Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications (SP, KS, YD, SKL), p. 6.
- DAC-2015-PapamichaelMH #algorithm #automation #design #named #performance #search-based #using
- Nautilus: fast automated IP design space search using guided genetic algorithms (MKP, PM, JCH), p. 6.
- DAC-2015-Peeters #architecture #security
- SoC security architecture: current practices and emerging needs (EP), p. 6.
- DAC-2015-PengKPPJCL #3d #architecture #delivery #design #policy
- Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM (YP, BWK, YSP, KIP, SJJ, JSC, SKL), p. 6.
- DAC-2015-PetersWPKD #constraints #modelling #representation #uml
- A generic representation of CCSL time constraints for UML/MARTE models (JP, RW, NP, UK, RD), p. 6.
- DAC-2015-PetrenkoTR #challenge #modelling #testing
- Model-based testing of automotive software: some challenges and solutions (AP, ONT, SR), p. 6.
- DAC-2015-PolianF #architecture #automation #challenge #design #quantum #scalability
- Design automation challenges for scalable quantum architectures (IP, AGF), p. 6.
- DAC-2015-Pomeranz #generative #testing
- Generation of close-to-functional broadside tests with equal primary input vectors (IP), p. 6.
- DAC-2015-RahimiCMGB #clustering #embedded #hardware #memory management #scheduling #variability
- Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters (AR, DC, AM, RKG, LB), p. 6.
- DAC-2015-RajendranVK #detection
- Detecting malicious modifications of data in third-party intellectual property cores (JR, VV, RK), p. 6.
- DAC-2015-RakshitWLGM #design #power management #robust
- Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design (JR, RW, KTL, JG, KM), p. 6.
- DAC-2015-RamprasathV #algorithm #optimisation #performance #statistics
- An efficient algorithm for statistical timing yield optimization (SR, VV), p. 6.
- DAC-2015-RanjanVFRR #approximate #energy #performance
- Approximate storage for energy efficient spintronic memories (AR, SV, XF, KR, AR), p. 6.
- DAC-2015-RayYBB #correctness #design #security #validation
- Correctness and security at odds: post-silicon validation of modern SoC designs (SR, JY, AB, SB), p. 6.
- DAC-2015-RoloffSHT #architecture #parallel #simulation
- Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures (SR, DS, FH, JT), p. 6.
- DAC-2015-RoseM #analysis #design #performance
- Performance analysis of a memristive crossbar PUF design (GSR, CAM), p. 6.
- DAC-2015-RoyLUP #multi #named #optimisation #paradigm #performance
- OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions (SR, DL, JU, DZP), p. 6.
- DAC-2015-RozicYDV #generative #performance #random
- Highly efficient entropy extraction for true random number generators on FPGAs (VR, BY, WD, IV), p. 6.
- DAC-2015-SadeghiWW #challenge #industrial #internet #privacy #security
- Security and privacy challenges in industrial internet of things (ARS, CW, MW), p. 6.
- DAC-2015-SantosVK #adaptation #configuration management #embedded #reliability
- Dynamically adaptive scrubbing mechanism for improved reliability in reconfigurable embedded systems (RS, SV, AK), p. 6.
- DAC-2015-SarmaMBDN #energy #linux #named #performance
- SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs (SS, TM, LADB, NDD, AN), p. 6.
- DAC-2015-SchatzVZ #automation #component #deployment
- Automating design-space exploration: optimal deployment of automotive SW-components in an ISO26262 context (BS, SV, SZ), p. 6.
- DAC-2015-SeyedzadehMJM #encoding #memory management #named #pseudo #reduction
- PRES: pseudo-random encoding scheme to increase the bit flip reduction in the memory (SMS, RM, AKJ, RGM), p. 6.
- DAC-2015-ShafiqueAHH #configuration management #latency
- A low latency generic accuracy configurable adder (MS, WA, RH, JH), p. 6.
- DAC-2015-ShafiqueKTH #anti #energy #named #video
- EnAAM: energy-efficient anti-aging for on-chip video memories (MS, MUKK, AOT, JH), p. 6.
- DAC-2015-ShreejithF #embedded #generative #network #security
- Security aware network controllers for next generation automotive embedded systems (SS, SAF), p. 6.
- DAC-2015-SonghoriHSK #logic #nearest neighbour #privacy #synthesis #using
- Compacting privacy-preserving k-nearest neighbor search using logic synthesis (EMS, SUH, ARS, FK), p. 6.
- DAC-2015-SripadaP #approach #graph
- A timing graph based approach to mode merging (SS, MP), p. 6.
- DAC-2015-SuC #complexity
- Nanowire-aware routing considering high cut mask complexity (YHS, YWC), p. 6.
- DAC-2015-SumbulVZFP #design #in memory #synthesis
- A synthesis methodology for application-specific logic-in-memory designs (HES, KV, QZ, FF, LP), p. 6.
- DAC-2015-SztipanovitsBNK #cyber-physical #design #lessons learnt
- Design tool chain for cyber-physical systems: lessons learned (JS, TB, SN, XDK, EKJ), p. 6.
- DAC-2015-TashjianD #identification #on the #using
- On using control signals for word-level identification in a gate-level netlist (ET, AD), p. 6.
- DAC-2015-TatsuokaWOHZOLT #design #synthesis
- Physically aware high level synthesis design flow (MT, RW, TO, TH, QZ, RO, XL, TT), p. 6.
- DAC-2015-TavanaHPSH #named #scalability
- ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling (MKT, MHH, DP, IS, HH), p. 6.
- DAC-2015-TeimouriTS #challenge
- Revisiting accelerator-rich CMPs: challenges and solutions (NT, HT, GS), p. 6.
- DAC-2015-TenaceCMP #logic #synthesis
- One-pass logic synthesis for graphene-based Pass-XNOR logic circuits (VT, AC, EM, MP), p. 6.
- DAC-2015-ThieleAE #analysis #scheduling
- Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling (DT, PA, RE), p. 6.
- DAC-2015-TodmanSL #configuration management #design #monitoring #runtime #verification
- In-circuit temporal monitors for runtime verification of reconfigurable designs (TT, SS, WL), p. 6.
- DAC-2015-TretterKT #multi #probability
- Interleaved multi-bank scratchpad memories: a probabilistic description of access conflicts (AT, PK, LT), p. 6.
- DAC-2015-TsaiYPLTCC #design #energy #in memory #memory management #using
- Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI (HJT, KHY, YCP, CCL, YHT, MFC, TFC), p. 6.
- DAC-2015-TsengLHS #synthesis
- Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping (TMT, BL, TYH, US), p. 6.
- DAC-2015-TziantzioulisGF #correlation #fault #float #integer #named
- b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units (GT, AMG, SMF, NH, SOM, SP), p. 6.
- DAC-2015-VasudevanR #algorithm #performance
- An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form (VV, MR), p. 6.
- DAC-2015-VatanparvarF
- Battery lifetime-aware automotive climate control for electric vehicles (KV, MAAF), p. 6.
- DAC-2015-VenkataramaniCR #approximate #performance
- Approximate computing and the quest for computing efficiency (SV, STC, KR, AR), p. 6.
- DAC-2015-VenkataramaniRL #classification #energy #machine learning
- Scalable-effort classifiers for energy-efficient machine learning (SV, AR, JL, MS), p. 6.
- DAC-2015-WachsI #challenge #design #hardware #integration #security
- Design and integration challenges of building security hardware IP (MW, DI), p. 6.
- DAC-2015-WangH0LL #logic #memory management #named
- ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing (YW, YH, LZ, HL, XL), p. 6.
- DAC-2015-WangHWLL #assembly #memory management #named
- RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory (YW, YH, CW, HL, XL), p. 6.
- DAC-2015-WangJSX #adaptation #architecture #human-computer #interface
- Adaptive compressed sensing architecture in wireless brain-computer interface (AW, ZJ, CS, WX), p. 6.
- DAC-2015-WangJZWY #energy #performance
- Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM (RW, LJ, YZ, LW, JY), p. 6.
- DAC-2015-WangJZWY15a #memory management
- Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory (RW, LJ, YZ, LW, JY), p. 6.
- DAC-2015-WangLPC #automation #hybrid
- Joint automatic control of the powertrain and auxiliary systems to enhance the electromobility in hybrid electric vehicles (YW, XL, MP, NC), p. 6.
- DAC-2015-WangLYSOC #grid #novel #power management #reduction
- Novel power grid reduction method based on L1 regularization (YW, ML, XY, ZS, MO, CC), p. 6.
- DAC-2015-WangLZYW #architecture #configuration management #control flow
- Acceleration of control flows on reconfigurable architecture with a composite method (JW, LL, JZ, SY, SW), p. 6.
- DAC-2015-WangR #design #tool support
- Design tools for oscillator-based computing systems (TW, JR), p. 6.
- DAC-2015-WasicekLKGIA #simulation
- System simulation from operational data (AW, EAL, HK, LG, AI, IA), p. 6.
- DAC-2015-WenWHLHLC #framework #hybrid #scalability
- An EDA framework for large scale hybrid neuromorphic computing systems (WW, CRW, XH, BL, TYH, XL, YC), p. 6.
- DAC-2015-XiaoGWYTW #layout #optimisation #self #verification
- Layout optimization and template pattern verification for directed self-assembly (DSA) (ZX, DG, MDFW, HY, MCT, HSPW), p. 6.
- DAC-2015-XieLXCJJ
- Jump test for metallic CNTs in CNFET-based SRAM (FX, XL, QX, KC, NJ, LJ), p. 6.
- DAC-2015-XieZPHLX #energy
- Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor (MX, MZ, CP, JH, YL, CJX), p. 6.
- DAC-2015-XuLP #adaptation #modelling #physics #statistics #using
- Adaptive characterization and emulation of delay-based physical unclonable functions using statistical models (TX, DL, MP), p. 6.
- DAC-2015-XuYGHP #named #self
- PARR: pin access planning and regular routing for self-aligned double patterning (XX, BY, JRG, CLH, DZP), p. 6.
- DAC-2015-YangCK #design
- Virtual flash chips: rethinking the layer design of flash devices to improve data recoverability (MCY, YHC, TWK), p. 6.
- DAC-2015-YangTJ #analysis
- Criticality-dependency-aware timing characterization and analysis (YMY, KHT, IHRJ), p. 6.
- DAC-2015-YaoHC #constraints #named
- PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips (HY, TYH, YC), p. 6.
- DAC-2015-YoonSMC #behaviour #detection #embedded #heatmap #memory management #realtime #using
- Memory heat map: anomaly detection in real-time embedded systems using memory behavior (MKY, LS, SM, JC), p. 6.
- DAC-2015-YuJTSS #challenge #integration #modelling
- The challenge of interoperability: model-based integration for automotive control software (HY, PJ, JPT, SKS, SS), p. 6.
- DAC-2015-YunPB #adaptation #named #parallel #runtime #self #thread
- HARS: a heterogeneity-aware runtime system for self-adaptive multithreaded applications (JY, JP, WB), p. 6.
- DAC-2015-YuUK
- Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks (WY, OAU, SK), p. 6.
- DAC-2015-ZaheerWGL #markov #named #performance #process
- mTunes: efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process (MZ, FW, CG, XL), p. 6.
- DAC-2015-ZhangHXHC #compilation #framework #named
- CMOST: a system-level FPGA compilation framework (PZ, MH, BX, HH, JC), p. 6.
- DAC-2015-ZhangLSLWXY #energy #migration #scheduling
- Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration (DZ, YL, XS, JL, TW, CJX, HY), p. 6.
- DAC-2015-ZhangMMWSS #3d #design
- A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC (RZ, KM, BHM, KW, KS, MRS), p. 6.
- DAC-2015-ZhanOGZ0 #approach #named #network #power management #towards
- DimNoC: a dim silicon approach towards power-efficient on-chip network (JZ, JO, FG, JZ, YX), p. 6.
- DAC-2015-ZhaoTDZ #pipes and filters #synthesis
- Area-efficient pipelining for FPGA-targeted high-level synthesis (RZ, MT, SD, ZZ), p. 6.
- DAC-2015-ZhengLDGZS #design #security #verification
- Design and verification for transportation system security (BZ, WL, PD, LG, QZ, NS), p. 6.
- DAC-2015-ZhouAZYUGUJ #detection #embedded #hardware #using
- Detecting hardware trojans using backside optical imaging of embedded watermarks (BZ, RA, MZ, TY, AU, BBG, MSÜ, AJ), p. 6.
- DAC-2015-ZhuangYKWC #algorithm #exponential #framework #performance #scalability #simulation #using
- An algorithmic framework for efficient large-scale circuit simulation using exponential integrators (HZ, WY, IK, XW, CKC), p. 6.
- DAC-2015-ZiegenbeinH #design
- Timing-aware control software design for automotive systems (DZ, AH), p. 6.
- DAC-2015-ZolotovF #integer #linear #programming
- Variation aware cross-talk aggressor alignment by mixed integer linear programming (VZ, PF), p. 6.
- DAC-2015-WangSBS #feedback #implementation #probability
- Randomness meets feedback: stochastic implementation of logistic map dynamical system (ZW, NS, KB, AS), p. 7.
34 ×#design
32 ×#performance
30 ×#named
16 ×#using
15 ×#energy
13 ×#architecture
12 ×#memory management
12 ×#modelling
10 ×#analysis
10 ×#synthesis
32 ×#performance
30 ×#named
16 ×#using
15 ×#energy
13 ×#architecture
12 ×#memory management
12 ×#modelling
10 ×#analysis
10 ×#synthesis