XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks
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Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu 0005, Jae-sun Seo, Shimeng Yu
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks
DATE, 2018.

DATE 2018
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@inproceedings{DATE-2018-SunYPLSY,
	author        = "Xiaoyu Sun and Shihui Yin and Xiaochen Peng and Rui Liu 0005 and Jae-sun Seo and Shimeng Yu",
	booktitle     = "{Proceedings of the 22nd Conference and Exhibition on Design, Automation and Test in Europe}",
	doi           = "10.23919/DATE.2018.8342235",
	isbn          = "978-3-9819263-0-9",
	pages         = "1423--1428",
	publisher     = "{IEEE}",
	title         = "{XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks}",
	year          = 2018,
}


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