BibSLEIGH — Proceedings of the 22nd Conference and Exhibition on Design, Automation and Test in Europe

Jan Madsen, Ayse K. Coskun
Proceedings of the 22nd Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2018.

SYS

@proceedings{DATE-2018,
	editor        = "Jan Madsen and Ayse K. Coskun",
	ee            = "https://ieeexplore.ieee.org/xpl/conhome/8337149/proceeding",
	isbn          = "978-3-9819263-0-9",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 22nd Conference and Exhibition on Design, Automation and Test in Europe}",
	year          = 2018,
}

Contents (311 items)

DATE-2018-KimHMACS: MATIC: Learning around errors for efficient low-voltage neural network accelerators (SK, PH, TM, AA, LC, VS0), pp. 1–6.
DATE-2018-ParkKYK: Maximizing system performance by balancing computation loads in LSTM accelerators (JP, JK, WY, JJK), pp. 7–12.
DATE-2018-ChenCH: moDNN: Memory optimal DNN training on GPUs (XC0, DZC, XSH), pp. 13–18.
DATE-2018-StamoulisCJM: HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks (DS, EC, DCJ, DM), pp. 19–24.
DATE-2018-HsiaoA: Sensei: An area-reduction advisor for FPGA high-level synthesis (HH, JHA), pp. 25–30.
DATE-2018-DuttS: A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis (SD, OS), pp. 31–36.
DATE-2018-BansalHCA: High-level synthesis of software-customizable floating-point cores (SB, HH, TSC, JHA), pp. 37–42.
DATE-2018-GoldbergGKM: Efficient verification of multi-property designs (The benefit of wrong assumptions) (EG, MG, DK, RM), pp. 43–48.
DATE-2018-SeufertS: Combining PDR and reverse PDR for hardware model checking (TS, CS), pp. 49–54.
DATE-2018-FadihehUNMBSK: Symbolic quick error detection using symbolic initial state for pre-silicon verification (MRF, JU, SSN, SM, CWB, DS, WK), pp. 55–60.
DATE-2018-LiangMKM: Verification of tree-based hierarchical read-copy update in the Linux kernel (LL, PEM, DK, TM), pp. 61–66.
DATE-2018-TanY: HVSM: Hardware-variability aware streaming processors' management policy in GPUs (JT, KY), pp. 67–72.
DATE-2018-PunyalaMKA: Throughput optimization and resource allocation on GPUs under multi-application execution (SRP, TM, AK, IA), pp. 73–78.
DATE-2018-LiJDLZJ: Set variation-aware shared LLC management for CPU-GPU heterogeneous architecture (ZL, LJ, HD, XL, MZ, ZJ), pp. 79–84.
DATE-2018-RezaeiSKGZ: Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks (AR, YS, SK, JG, HZ), pp. 85–90.
DATE-2018-ZhangLYPS: TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing (GLZ, BL0, BY0, DZP, US), pp. 91–96.
DATE-2018-PatnaikRKSR: Advancing hardware security using polymorphic and stochastic spin-hall effect devices (SP, NR, JK, OS, SR), pp. 97–102.
DATE-2018-KomalanRHSTGKFC: Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks (MK, OHR, MH, SS, CT, JIG, GSK, AF, FC, SS, DN, AG, LT), pp. 103–108.
DATE-2018-YanCZSLC: Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices (BY, FC, YZ, CS, HL0, YC), pp. 109–112.
DATE-2018-GebregiorgisBT: Spintronic normally-off heterogeneous system-on-chip design (AG, RB, MBT), pp. 113–118.
DATE-2018-KangCZLHZZ: Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers (WK, XC, DZ, SL, YH, YZ, WZ), pp. 119–124.
DATE-2018-MotamanKG: Novel application of spintronics in computing, sensing, storage and cybersecurity (SM, MNIK, SG), pp. 125–130.
DATE-2018-AnBOK: Large scale, high density integration of all spin logic (QA, SLB, IO, JOK), pp. 131–136.
DATE-2018-SoekenHR: Programming quantum computers using design automation (MS, TH, MR), pp. 137–146.
DATE-2018-PahlevanQZBRBA: Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not? (AP, YMQ, MZ, AB, DR, LB, DA), pp. 147–152.
DATE-2018-TianZWX: Lookup table allocation for approximate computing with memory under quality constraints (YT, QZ0, TW0, QX0), pp. 153–158.
DATE-2018-LongSM: Accelerating biophysical neural network simulation with region of interest based approximation (YL, XS, SM), pp. 159–164.
DATE-2018-ZhangTS: DS-DSE: Domain-specific design space exploration for streaming applications (JZ, HT, GS), pp. 165–170.
DATE-2018-ZhouWCHMZY: Variation-aware task allocation and scheduling for improving reliability of real-time MPSoCs (JZ, TW, MC, XSH, YM0, GZ, JY), pp. 171–176.
DATE-2018-QianLM: Topology-aware virtual resource management for heterogeneous multicore systems (JQ, JL0, RM), pp. 177–182.
DATE-2018-ParkK: Structure optimizations of neuromorphic computing architectures for deep neural network (HP, TK), pp. 183–188.
DATE-2018-LiYLJGWL: CCR: A concise convolution rule for sparse neural network accelerators (JL, GY, WL, SJ, SG, JW, XWL), pp. 189–194.
DATE-2018-HaineSFB: Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics (TH, JS, DF, DB), pp. 195–200.
DATE-2018-KraakATHWCC: Degradation analysis of high performance 14nm FinFET SRAM (DK, IA, MT, SH, PW, SC, FC), pp. 201–206.
DATE-2018-AhmadianTLKA: Investigating power outage effects on reliability of solid-state drives (SA, FT, ML, MK, HA), pp. 207–212.
DATE-2018-RenBSLWT: Workload-aware harmonic partitioned scheduling for probabilistic real-time systems (JR, RB, XS, QL0, GW, GT), pp. 213–218.
DATE-2018-IndrusiakBN: Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs (LSI, AB, BN), pp. 219–224.
DATE-2018-HasanMPB: A design-space exploration for allocating security tasks in multicore real-time systems (MH, SM, RP, RBB), pp. 225–230.
DATE-2018-NguyenOGFPR: Design and analysis of semaphore precedence constraints: A model-based approach for deterministic communications (TDN, YO, EG, JF, CP, PR), pp. 231–236.
DATE-2018-JiSJLC: ReCom: An efficient resistive accelerator for compressed deep neural networks (HJ, LS, LJ0, HHL, YC), pp. 237–240.
DATE-2018-ZhuJCT: SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity (JZ, JJ, XC, CYT), pp. 241–244.
DATE-2018-StevensDKR: ACCLIB: Accelerators as libraries (JRS, YD, VK, AR), pp. 245–248.
DATE-2018-AhmadPS: HPXA: A highly parallel XML parser (IA, SP, SRS), pp. 249–252.
DATE-2018-NabavinejadZAGR: QoR-aware power capping for approximate big data processing (SMN, XZ, RA, MG, SR), pp. 253–256.
DATE-2018-NeubauerWSH: Exact multi-objective design space exploration using ASPmT (KN, PW, TS, CH), pp. 257–260.
DATE-2018-TomeSCAA: HIPE: HMC instruction predication extension applied on database processing (DGT, PCS, LC, ECdA, MAZA), pp. 261–264.
DATE-2018-NairBT: Parametric failure modeling and yield analysis for STT-MRAM (SMN, RB, MBT), pp. 265–268.
DATE-2018-Schoeberl: One-way shared memory (MS), pp. 269–272.
DATE-2018-XuJTGXT: An efficient resource-optimized learning prefetcher for solid state drives (RX, XJ, LT, SG, ZX, TT), pp. 273–276.
DATE-2018-UngureanuMS: Bridging discrete and continuous time models with atoms (GU, JEGdM, IS), pp. 277–280.
DATE-2018-BucsFLAT0: OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation (RLB, MF, RL, GA, ST, AH0), pp. 281–284.
DATE-2018-WuCLT: A highly efficient full-system virtual prototype based on virtualization-assisted approach (HIW, CKC, TYL, RST), pp. 285–288.
DATE-2018-ZandrahimiDCA: Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling (MZ, PD, AC, ZAA), pp. 289–292.
DATE-2018-MathewSRSWW0: An analysis on retention error behavior and power consumption of recent DDR4 DRAMs (DMM, MS, CCR, CS, CW, NW, MJ0), pp. 293–296.
DATE-2018-DalpassoBF: A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices (MD, DB, MF), pp. 297–300.
DATE-2018-GulveS: ATPG power guards: On limiting the test power below threshold (RG, VS), pp. 301–304.
DATE-2018-Kulikov: Improving circuit size upper bounds using SAT-solvers (ASK), pp. 305–308.
DATE-2018-SoekenHTMABM: Practical exact synthesis (MS, WH, ET, AM, LGA, RKB, GDM), pp. 309–314.
DATE-2018-DebnathMJO: SAT-based redundancy removal (KD, RM, MJ, JO), pp. 315–318.
DATE-2018-HashemiTBR: Approximate computing for biometrie security systems: A case study on iris scanning (SH, HT, FB, SR), pp. 319–324.
DATE-2018-WuMC: Flash read disturb management using adaptive cell bit-density with in-place reprogramming (TCW, YpM, LPC), pp. 325–330.
DATE-2018-AlbaqsamiHB: HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors (AA, MSH, NB), pp. 331–336.
DATE-2018-PandaZGJ: CAMP: Accurate modeling of core and memory locality for proxy generation of big-data applications (RP, XZ, AG, LKJ), pp. 337–342.
DATE-2018-LiYLJGWL18a: SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators (JL, GY, WL, SJ, SG, JW, XL0), pp. 343–348.
DATE-2018-SchmidtCD: Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation (TS, ZC, RD), pp. 349–354.
DATE-2018-BalRC: Trident: A comprehensive timing error resilient technique against choke points at NTC (AB, SR, KC), pp. 355–360.
DATE-2018-KimY: Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoring (BSK, JSY), pp. 361–366.
DATE-2018-ChekuriKSM: Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations (VCKC, MK, AS, SM), pp. 367–372.
DATE-2018-MondalC: Pre-assembly testing of interconnects in embedded multi-die interconnect bridge (EMIB) dies (SM, KC), pp. 373–378.
DATE-2018-KuentzerJA: On the reuse of timing resilient architecture for testing path delay faults in critical paths (FAK, LRJ, AMA), pp. 379–384.
DATE-2018-BurchardE0: Characterization of possibly detected faults by accurately computing their detection probability (JB, DE, BB0), pp. 385–390.
DATE-2018-MathewSSK: Ultra-low energy circuit building blocks for security technologies (SM, SS, VBS, RK), pp. 391–394.
DATE-2018-LeviRFK: Embedded randomness and data dependencies design paradigm: Advantages and challenges (IL, YR, AF, OK), pp. 395–400.
DATE-2018-SinghKMRDM: Exploiting on-chip power management for side-channel security (AS, MK, SM, AR, VD, SM), pp. 401–406.
DATE-2018-LinXZSCGCCWY: Rescuing memristor-based computing with non-linear resistance levels (JL, LX, ZZ, HS, YC, HG, MC, XC0, YW0, HY), pp. 407–412.
DATE-2018-AkbariKAPS: PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture (OA, MK, AAK, MP, MS0), pp. 413–418.
DATE-2018-AmiriHMN: Multi-precision convolutional neural networks on heterogeneous hardware (SA, MH, SMS, JLNY), pp. 419–424.
DATE-2018-TunaliA: Logic synthesis and defect tolerance for memristive crossbar arrays (OT, MA), pp. 425–430.
DATE-2018-ProbstlPNSC: SOH-aware active cell balancing strategy for high power battery packs (AP, SP, SN, SS, SC), pp. 431–436.
DATE-2018-VincoBPAMP: GIS-based optimal photovoltaic panel floorplanning for residential installations (SV, LB, EP, AA, EM, MP), pp. 437–442.
DATE-2018-FickenscherSHTB: Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs (JF, JS, FH, JT, MEB), pp. 443–448.
DATE-2018-PourshiraziBZM: WALL: A writeback-aware LLC management for PCM-based main memory systems (BP, MVB, ZZ, GM), pp. 449–454.
DATE-2018-BenedicteHAC: Design and integration of hierarchical-placement multi-level caches for real-time systems (PB, CH, JA, FJC), pp. 455–460.
DATE-2018-KuanA: LARS: Logically adaptable retention time STT-RAM cache for embedded systems (KK, TA), pp. 461–466.
DATE-2018-MispanSZH: Cost-efficient design for modeling attacks resistant PUFs (MSM, HS, MZ, BH), pp. 467–472.
DATE-2018-AriasRTJ: Device attestation: Past, present, and future (OA, FR, MT, YJ), pp. 473–478.
DATE-2018-AramoonCQ: A reconfigurable scan network based IC identification for embedded devices (OA, XC, GQ), pp. 479–484.
DATE-2018-WooZH: Early detection of system-level anomalous behaviour using hardware performance counters (LLW, MZ, BH), pp. 485–490.
DATE-2018-ShaoHLBBC: Compact modeling of carbon nanotube thin film transistors for flexible circuit design (LS, TCH, TL, ZB, RGB, KTC), pp. 491–496.
DATE-2018-FletcherDM: A high-speed design methodology for inductive coupling links in 3D-ICs (BJF, SD, TSTM), pp. 497–502.
DATE-2018-WalterWGTD: An exact method for design exploration of quantum-dot cellular automata (MW, RW, DG, FST, RD), pp. 503–508.
DATE-2018-ShahsavaniZP: Accurate margin calculation for single flux quantum logic cells (SNS, BZ, MP), pp. 509–514.
DATE-2018-MaCDH: Improving reliability for real-time systems through dynamic recovery (YM0, TC, RPD, XSH), pp. 515–520.
DATE-2018-BundLM: Optimal metastability-containing sorting networks (JB, CL, MM), pp. 521–526.
DATE-2018-WuTL: MAUI: Making aging useful, intentionally (KCW, THT, SCL), pp. 527–532.
DATE-2018-SoDKSL: EXPERT: Effective and flexible error protection by redundant multithreading (HS, MD, YK, AS, KL), pp. 533–538.
DATE-2018-ForsbergBM: HePREM: Enabling predictable GPU execution on heterogeneous SoC (BF, LB, AM), pp. 539–544.
DATE-2018-ScarabottoloAP: Circuit carving: A methodology for the design of approximate hardware (IS, GA, LP), pp. 545–550.
DATE-2018-NeshatpourBHS: ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation (KN, FB, HH, AS), pp. 551–556.
DATE-2018-PathaniaH: Task scheduling for many-cores with S-NUCA caches (AP, JH), pp. 557–562.
DATE-2018-WuLC: KVSSD: Close integration of LSM trees and flash translation layer for write-efficient KV store (SMW, KHL, LPC), pp. 563–568.
DATE-2018-PangZLLCLJ: In-growth test for monolithic 3D integrated SRAM (PP, YZ, TL, SKL, QC, XL, LJ0), pp. 569–572.
DATE-2018-DijkVBCS: A co-design methodology for scalable quantum processors and their classical electronic interface (JPGvD, AV, MB, EC, FS), pp. 573–576.
DATE-2018-BoroumandPB: Approximate quaternary addition with the fast carry chains of FPGAs (SB, HPA, PB), pp. 577–580.
DATE-2018-HongLP: NN compactor: Minimizing memory and logic resources for small neural networks (SH, IL, YP), pp. 581–584.
DATE-2018-LamprechtNS: Improving fast charging efficiency of reconfigurable battery packs (AL, SN, SS), pp. 585–588.
DATE-2018-AdiththanRS: Cloud-assisted control of ground vehicles using adaptive computation offloading techniques (AA, SR, SS), pp. 589–592.
DATE-2018-VasilakisPTS: FusionCache: Using LLC tags for DRAM cache (EV, VP, PT, IS), pp. 593–596.
DATE-2018-NiemannWD: Improved synthesis of Clifford+T quantum functionality (PN, RW, RD), pp. 597–600.
DATE-2018-WangSWHFBC: Energy-efficient channel alignment of DWDM silicon photonic transceivers (YW, MAS, RW, JH, MF, RGB, KTC), pp. 601–604.
DATE-2018-RaiRWRHBTMW0: A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs (SR, AR, DW, MR, AH, TB, JT, CM, WMW, AK0), pp. 605–608.
DATE-2018-Mueller-Gritschneder: ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques (DMG, MD, JW, EC, SM, US), pp. 609–612.
DATE-2018-TonettoNB: Precise evaluation of the fault sensitivity of OoO superscalar processors (RBT, GLN, ACSB), pp. 613–616.
DATE-2018-KimHS: StreamFTL: Stream-level address translation scheme for memory constrained flash storage (HK, KH, DS), pp. 617–620.
DATE-2018-ReddyMAS: Online concurrent workload classification for multi-core energy management (BKR, GVM, BMAH, AKS0), pp. 621–624.
DATE-2018-XieLGHW0: AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory (MX, SL, AOG, JH, YW, YX0), pp. 625–628.
DATE-2018-ShenRZ: SAT-based bit-flipping attack on logic encryptions (YS, AR, HZ), pp. 629–632.
DATE-2018-SpeicherMAWH: AMS verification methodology regarding supply modulation in RF SoCs induced by digital standard cells (FS, JM, SA, RW, SH), pp. 633–636.
DATE-2018-RestaGBALCRMG: Towards high-performance polarity-controllable FETs with 2D materials (GVR, JRG, YB, TA, DL, FC, IPR, GDM, PEG), pp. 637–641.
DATE-2018-VigJL: Dynamic skewed tree for fast memory integrity verification (SV, GJ, SKL), pp. 642–647.
DATE-2018-ReinbrechtFZS: Earthquake - A NoC-based optimized differential cache-collision attack for MPSoCs (CR, BF, AZ, JS), pp. 648–653.
DATE-2018-StanglLD: A fast and resource efficient FPGA implementation of secret sharing for storage applications (JS, TL, SMPD), pp. 654–659.
DATE-2018-Pessoa0MPH: Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel (TP, NL0, RM0, RP, NH), pp. 660–665.
DATE-2018-MiorandiSFQ: A SystemC-based Simulator for design space exploration of smart wireless systems (GM, FS, FF, DQ), pp. 666–671.
DATE-2018-DingCHBLBPR: A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoT (MD0, GC, PH, BB, YHL, CB, KP, AHMvR), pp. 672–675.
DATE-2018-LoraCQF: Automatic integration of cycle-accurate descriptions with continuous-time models for cyber-physical virtual platforms (ML, SC, DQ, FF), pp. 676–681.
DATE-2018-MahfouziASREP: Stability-aware integrated routing and scheduling for control applications in Ethernet networks (RM, AA, SS, AR, PE, ZP), pp. 682–687.
DATE-2018-LiCCZWCH: Feedback control of real-time EtherCAT networks for reliability enhancement in CPS (LL, PC, KC, JZ, TW, MC, XSH), pp. 688–693.
DATE-2018-ChangRHC: Cache-aware task scheduling for maximizing control performance (WC, DR, XSH, SC), pp. 694–699.
DATE-2018-GauenDLPLBC: Three years of low-power image recognition challenge: Introduction to special session (KG, RD, YHL, EP, WL0, ACB, YC), pp. 700–703.
DATE-2018-YuGHNQMYTLWY: Real-time object detection towards high power efficiency (JY, KG, YH, XN, JQ, HM, SY, TT, BL, YW0, HY), pp. 704–708.
DATE-2018-WangQLHLL: A retrospective evaluation of energy-efficient object detection solutions on embedded devices (YW0, ZQ, JL, YH, HL, XL0), pp. 709–714.
DATE-2018-KangKKYH: Joint optimization of speed, accuracy, and energy for embedded image recognition systems (DK, DK, JK, SY, SH), pp. 715–720.
DATE-2018-NavehKWB: Theoretical and practical aspects of verification of quantum computers (YN, EK, JRW, KB), pp. 721–730.
DATE-2018-BaruahSDKR: Airavat: Improving energy efficiency of heterogeneous applications (TB, YS, SD, DRK, NR), pp. 731–736.
DATE-2018-PagliariPCCMP: All-digital embedded meters for on-line power estimation (DJP, VP, YC, AC, EM, MP), pp. 737–742.
DATE-2018-ZoniCF: PowerProbe: Run-time power modeling through automatic RTL instrumentation (DZ, LC, WF), pp. 743–748.
DATE-2018-ParkC: Design optimization of photovoltaic arrays on curved surfaces (SP, SC), pp. 749–754.
DATE-2018-AmaruSVLMOBM: Improvements to boolean resynthesis (LGA, MS, PV, JL, AM, JO, RKB, GDM), pp. 755–760.
DATE-2018-LeeWLCW: Logic optimization with considering boolean relations (TYL, CCW, CCL, YCC, CYW), pp. 761–766.
DATE-2018-RaiR0: Technology mapping flow for emerging reconfigurable silicon nanowire transistors (SR, MR, AK0), pp. 767–772.
DATE-2018-LaiLWCW: Efficient synthesis of approximate threshold logic circuits with an error rate guarantee (YAL, CCL, CCW, YCC, CYW), pp. 773–778.
DATE-2018-SongAL: Row-buffer hit harvesting in orchestrated last-level cache and DRAM scheduling for heterogeneous multicore systems (YS0, OA, BL), pp. 779–784.
DATE-2018-TeimooriHE0: AdAM: Adaptive approximation management for the non-volatile memory hierarchies (MTT, MAH, AE, MS0), pp. 785–790.
DATE-2018-SayedBOT: A cross-layer adaptive approach for performance and power optimization in STT-MRAM (NS, RB, FO, MBT), pp. 791–796.
DATE-2018-PanLYLYLW: Low-cost high-accuracy variation characterization for nanoscale IC technologies via novel learning-based techniques (ZP, ML, JY, HL0, ZY, YL, YW), pp. 797–802.
DATE-2018-WangKKK: Mitigation of NBTI induced performance degradation in on-chip digital LDOs (LW, SKK, URK, SK), pp. 803–808.
DATE-2018-PrevilonKKR: Evaluating the impact of execution parameters on program vulnerability in GPU applications (FGP, CK, DRK, PR), pp. 809–814.
DATE-2018-LiSCQCL: ReRAM-based accelerator for deep learning (BL0, LS, FC, XQ, YC, HHL), pp. 815–820.
DATE-2018-ChenCGSV: Exploiting approximate computing for deep learning acceleration (CYC, JC, KG, VS, SV), pp. 821–826.
DATE-2018-ShafiqueTBHKHR: An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era (MS, TT, CSB, MAH, FK, RH, SR), pp. 827–832.
DATE-2018-PreusserGFB: Inference of quantized neural networks on heterogeneous all-programmable devices (TBP, GG, NJF, MB), pp. 833–838.
DATE-2018-NuzzoLFS: CHASE: Contract-based requirement engineering for cyber-physical system design (PN, ML, YAF, ALSV), pp. 839–844.
DATE-2018-LeHGD: Resilience evaluation via symbolic fault injection on intermediate code (HML, VH, DG, RD), pp. 845–850.
DATE-2018-DeckerDGHLLSWW: Online analysis of debug trace data for embedded systems (ND, BD, PG, CH, AL, ML, TS, SW, AW), pp. 851–856.
DATE-2018-HassanGLVED: Testbench qualification for SystemC-AMS timed data flow models (MH, DG, HML, TV, KE, RD), pp. 857–860.
DATE-2018-MedeirosUS: An algebra for modeling continuous time systems (JEGdM, GU, IS), pp. 861–864.
DATE-2018-JacobZZBCT: TTW: A Time-Triggered Wireless design for CPS (RJ, LZ, MZ, JB, SC, LT), pp. 865–868.
DATE-2018-KonstantinouCM: PHYLAX: Snapshot-based profiling of real-time embedded devices via JTAG interface (CK, EC, MM), pp. 869–872.
DATE-2018-HoKDC: Characterizing display QoS based on frame dropping for power management of interactive applications on smartphones (KTH, CTK, BD, YJC), pp. 873–876.
DATE-2018-YangKDLKBNLBC: Prediction-based fast thermoelectric generator reconfiguration for energy harvesting from vehicle radiators (HY, FK, CD, JL0, JK, DB, SN, XL, PB, NC), pp. 877–880.
DATE-2018-FengYZL: A parameterized timing-aware flip-flop merging algorithm for clock power reduction (CF, DY, ZZ, ZL), pp. 881–884.
DATE-2018-KimHKK: Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study (SK, KJH, YK, SK), pp. 885–888.
DATE-2018-FrohlichGD: Approximate hardware generation using symbolic computer algebra employing grobner basis (SF, DG, RD), pp. 889–892.
DATE-2018-Imana: Reconfigurable implementation of GF(2m) bit-parallel multipliers (JLI), pp. 893–896.
DATE-2018-SantosOLACB: Processing in 3D memories to speed up operations on complex data structures (PCS, GFO, JPCdL, MAZA, LC, ACSB), pp. 897–900.
DATE-2018-ChiuCL: An efficient NBTI-aware wake-up strategy for power-gated designs (KWC, YGC, ICL), pp. 901–904.
DATE-2018-BonnoitBZN: Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution (TB, FB, NEZ, MN), pp. 905–908.
DATE-2018-Schoeberl18a: Design of a time-predictable multicore processor: The T-CREST project (MS), pp. 909–912.
DATE-2018-HanifH0: Error resilience analysis for systematically employing approximate computing in convolutional neural networks (MAH, RH, MS0), pp. 913–916.
DATE-2018-PrabakaranRHUM0: DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems (BSP, SR, MAH, SU, GM, AK0, MS0), pp. 917–920.
DATE-2018-DonyanavardRMMD: Gain scheduled control for nonlinear power management in CMPs (BD, AMR, TM, KM, NDD), pp. 921–924.
DATE-2018-LefeuvreFCGKPD: Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction (TL, IF, CC, GG, EKK, IP, SD), pp. 925–930.
DATE-2018-TahooriNBSMMTBG: Using multifunctional standardized stack as universal spintronic technology for IoT (MBT, SMN, RB, SS, JM, FM, LT, PB, AG, PN, FO, GS, KJ, PV, AA, IF, GdP, GP), pp. 931–936.
DATE-2018-UhligLLRDNDOKGA: Progress on carbon nanotube BEOL interconnects (BU, JL, JL, RR, AD, NN, JD, HO, DK, VPG, AA, SMA, LW, CM, FK, BG, GG, BC, RRP, RC, ATS), pp. 937–942.
DATE-2018-RederMBBSB: A WCET-aware parallel programming model for predictability enhanced multi-core architectures (SR, LM, HB, TDtB, TS, JB0), pp. 943–948.
DATE-2018-IranfarPZZKA: Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation (AI, AP, MZ, MZ, MK, DA), pp. 949–954.
DATE-2018-SamiePBH: Highly efficient and accurate seizure prediction on constrained IoT devices (FS, SP, LB, JH), pp. 955–960.
DATE-2018-AbubakarSA: A wearable long-term single-lead ECG processor for early detection of cardiac arrhythmia (SMA, WS, MABA), pp. 961–966.
DATE-2018-KyrkouPTVB: DroNet: Efficient convolutional neural network detector for real-time UAV applications (CK, GP, TT, SIV, CSB), pp. 967–972.
DATE-2018-HuangDWY: HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processing (TH, GD, YW0, HY), pp. 973–978.
DATE-2018-SchornGA: Accurate neuron resilience prediction for a flexible reliability management in neural network accelerators (CS, AG, GA), pp. 979–984.
DATE-2018-NeggazYNEK: Rapid in-memory matrix multiplication using associative processor (MAN, HEY, SN, AME, FJK), pp. 985–990.
DATE-2018-RathoreCSSRLS: HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems (VR, VC, AKS, TS, RR, SKL, MS0), pp. 991–996.
DATE-2018-SivadasanSHCA: NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI (AS, RJS, VH, FC, LA), pp. 997–998.
DATE-2018-ZandrahimiDCA18a: An industrial case study of low cost adaptive voltage scaling using delay test patterns (MZ, PD, AC, ZAA), pp. 999–1000.
DATE-2018-WangSHTYZ: A case study for using dynamic partitioning based solution in volume diagnosis (TW, ZS, JH, HT, WY, JZ), pp. 1001–1002.
DATE-2018-Schat: On-line RF built-in self-test using noise injection and transmitter signal modulation by phase shifter (JS), pp. 1003–1004.
DATE-2018-ChengDHHN0RT: Neural networks for safety-critical applications - Challenges, experiments and perspectives (CHC, FD, GH, YH, GN, MR0, HR, MTL), pp. 1005–1006.
DATE-2018-MaurinDCS: IoT security assessment through the interfaces P-SCAN test bench platform (TM, LFD, GC, PS), pp. 1007–1008.
DATE-2018-RokickiRD: Supporting runtime reconfigurable VLIWs cores through dynamic binary translation (SR, ER, SD), pp. 1009–1014.
DATE-2018-AwekeA: uSFI: Ultra-lightweight software fault isolation for IoT-class devices (ZBA, TMA), pp. 1015–1020.
DATE-2018-RoyuelaPQ: Converging safety and high-performance domains: Integrating OpenMP into Ada (SR, LMP, EQ), pp. 1021–1026.
DATE-2018-Castro-GodinezE: Compiler-driven error analysis for designing approximate accelerators (JCG, SE, MS0, SP, JH), pp. 1027–1032.
DATE-2018-AndradePP: Overview of the state of the art in embedded machine learning (LA, APB, FP), pp. 1033–1038.
DATE-2018-CarbonPBSTBVPB: PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks (AC, JMP, OB, RS, BT, DB, NV, MP, OB), pp. 1039–1044.
DATE-2018-LinLNLDWP: FFT-based deep learning deployment in embedded systems (SL, NL0, MN, HL, CD, YW, MP), pp. 1045–1050.
DATE-2018-TagliaviniMRMB: A transprecision floating-point platform for ultra-low power computing (GT, SM, DR, AM, LB), pp. 1051–1056.
DATE-2018-QiuCXX0S: A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN (KQ, WC, YX, LX, YW0, ZS), pp. 1057–1062.
DATE-2018-LucasLJ: Optimal DC/AC data bus inversion coding (JL, SL, BHHJ), pp. 1063–1068.
DATE-2018-Balasubramanian: LASER: A hardware/software approach to accelerate complicated loops on CGRAs (MB, SD, AS, RJ), pp. 1069–1074.
DATE-2018-LiJMF: A time-multiplexed FPGA overlay with linear interconnect (XL, AKJ, DLM, SAF), pp. 1075–1080.
DATE-2018-DaveBS: URECA: Unified register file for CGRAs (SD, MB, AS), pp. 1081–1086.
DATE-2018-ZhaoLSKWM: Optimizing the data placement and transformation for multi-bank CGRA computing system (ZZ, YL, WS, TK, QW, ZM), pp. 1087–1092.
DATE-2018-BielskiSKSRTAPP: dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter (MB, IS, KK, DS, AR, DT, NA, DNP, EHP, GZ, VM, AS, AR, JFZ, SLB, MT, FZ, ME, ÓGdD), pp. 1093–1098.
DATE-2018-KarakonstantisT: An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits (GK, KT, LM, HV, DSN, PL, PKK, MM, CDA, CK, NB, SL, SV, APP, AL, MK, AD, ZH, PN, YS, PT, GP, MK, AC, DG, SD), pp. 1099–1104.
DATE-2018-MalossiSMGTETNF: The transprecision computing paradigm: Concept, design, and applications (ACIM, MS, AM, LG, GT, AE, AT, DSN, EF, NW), pp. 1105–1110.
DATE-2018-SchellenbergG0T: An inside job: Remote power analysis attacks on FPGAs (FS, DREG, AM0, MBT), pp. 1111–1116.
DATE-2018-BachePG: Confident leakage assessment - A side-channel evaluation framework based on confidence intervals (FB, CP, TG), pp. 1117–1122.
DATE-2018-AwekeA18a: Øzone: Efficient execution with zero timing leakage for modern microarchitectures (ZBA, TMA), pp. 1123–1128.
DATE-2018-BreierJB: SCADPA: Side-channel assisted differential-plaintext attack on bit permutation based ciphers (JB, DJ, SB), pp. 1129–1134.
DATE-2018-ZulehnerPW: Efficient mapping of quantum circuits to the IBM QX architectures (AZ, AP, RW), pp. 1135–1138.
DATE-2018-GraillatMRD: Parallel code generation of synchronous programs for a many-core architecture (AG, MM, PR, BDdD), pp. 1139–1142.
DATE-2018-GadioliNPVAPCS: SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications (DG, RN, PP, EV, AHA, GP, JMPC, CS), pp. 1143–1146.
DATE-2018-Lamichhane0F: Non-intrusive program tracing of non-preemptive multitasking systems using power consumption (KL, CM0, SF), pp. 1147–1150.
DATE-2018-SantoroCPCA: Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator (GS, MRC, VP, AC, MA), pp. 1151–1154.
DATE-2018-ImaniGR: GenPIM: Generalized processing in-memory to accelerate data intensive applications (MI, SG, TR), pp. 1155–1158.
DATE-2018-JaiswalS: Universal number posit arithmetic generator on FPGA (MKJ, HKHS), pp. 1159–1162.
DATE-2018-LiLZC: Block convolution: Towards memory-efficient inference of large-scale CNNs on FPGA (GL0, FL, TZ, JC0), pp. 1163–1166.
DATE-2018-ZhangHATBMK: Examining the consequences of high-level synthesis optimizations on power side-channel (LZ, WH0, AA, YT, JB, DM, RK), pp. 1167–1170.
DATE-2018-KhairallahSSBBC: DFARPA: Differential fault attack resistant physical design automation (MK, RS, RS, JB, SB, RSC, AC, DM), pp. 1171–1174.
DATE-2018-LiuWLH: An energy-efficient stochastic computational deep belief network (YL, YW, FL, JH0), pp. 1175–1178.
DATE-2018-ZulehnerW: Pushing the number of qubits below the “minimum”: Realizing compact boolean components for quantum logic (AZ, RW), pp. 1179–1182.
DATE-2018-NiCCZQ: Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNN (YN, WC, WC, YZ, KQ), pp. 1183–1186.
DATE-2018-AzadFM: ORIENT: Organized interleaved ECCs for new STT-MRAM caches (ZA, HF, AMHM), pp. 1187–1190.
DATE-2018-CarpentTR: ERASMUS: Efficient remote attestation via self-measurement for unattended settings (XC, GT, NR), pp. 1191–1194.
DATE-2018-ChoiKH: End-to-end latency analysis of cause-effect chains in an engine management system (JC, DK, SH), pp. 1195–1198.
DATE-2018-LinH: General floorplanning methodology for 3D ICs with an arbitrary bonding style (JML, CYH), pp. 1199–1202.
DATE-2018-TraubVSSH: Digitalization in automotive and industrial systems (MT, HJV, ES, TS, JH), pp. 1203–1204.
DATE-2018-ChenYNH: Design and optimization of FeFET-based crossbars for binary convolution neural networks (XC0, XY, MTN, XSH), pp. 1205–1210.
DATE-2018-FletcherDPM: Low-power 3D integration using inductive coupling links for neurotechnology applications (BJF, SD, CSP, TSTM), pp. 1211–1216.
DATE-2018-DasWHDCS: Mapping of local and global synapses on spiking neuromorphic hardware (AD, YW, KH, FD, FC, SS), pp. 1217–1222.
DATE-2018-JiaoAJ0: Energy-efficient neural networks using approximate computation reuse (XJ, VA, YJ0, RKG0), pp. 1223–1228.
DATE-2018-MunchBT: Multi-bit non-volatile spintronic flip-flop (CM, RB, MBT), pp. 1229–1234.
DATE-2018-SwamiM: ADAM: Architecture for write disturbance mitigation in scaled phase change memory (SS, KM), pp. 1235–1240.
DATE-2018-ShiWWXL: Program error rate-based wear leveling for NAND flash memory (XS, FW0, SW, CX, ZL), pp. 1241–1246.
DATE-2018-CuiZHWY: ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs (JC, YZ, JH, WW, JY0), pp. 1247–1252.
DATE-2018-AysuOT: Binary Ring-LWE hardware with power side-channel countermeasures (AA, MO, MT), pp. 1253–1258.
DATE-2018-SchillingUMGMB: High speed ASIC implementations of leakage-resilient cryptography (RS, TU, SM, FKG, MM, LB), pp. 1259–1264.
DATE-2018-AlliniPFB: Optimization of the PLL configuration in a PLL-based TRNG design (ENA, OP, VF, FB), pp. 1265–1270.
DATE-2018-MedinaBP: Availability enhancement and analysis for mixed-criticality systems on multi-core (RM0, EB, LP), pp. 1271–1276.
DATE-2018-AwanSBAT: Mixed-criticality scheduling with memory bandwidth regulation (MAA, PFS, KB, BA, ET), pp. 1277–1282.
DATE-2018-GhoshDGMC: Design and validation of fault-tolerant embedded controllers (SKG, SD, DG, DMG, SC), pp. 1283–1288.
DATE-2018-AzizBCCDGHHIJMM: Computing with ferroelectric FETs: Devices, models, systems, and applications (AA, ETB, AC, XC0, SD, SKG, MH0, XSH, AMI, MJ, TM, HM, KN0, MTN, IO, AS, SS, SKT, XY), pp. 1289–1298.
DATE-2018-MukhopadhyayWAG: The CAMEL approach to stacked sensor smart cameras (SM, MW, MFA, EG, JHK, JK, BAM), pp. 1299–1303.
DATE-2018-WuBKB: A design tool for high performance image processing on multicore platforms (JW0, TB, WK, SSB), pp. 1304–1309.
DATE-2018-GoossensLAP: Quasar, a high-level programming language and development environment for designing smart vision systems on embedded platforms (BG, HQL, JA, WP), pp. 1310–1315.
DATE-2018-TrevisiBFCR: Concurrent focal-plane generation of compressed samples from time-encoded pixel values (MT, HCB, JFB, RCG, ÁRV), pp. 1316–1320.
DATE-2018-WeissenfeldSD: Contactless finger and face capturing on a secure handheld embedded device (AW, BS, FD), pp. 1321–1326.
DATE-2018-Fugger0NN0: A faithful binary circuit model with adversarial noise (MF, JM0, RN, TN, US0), pp. 1327–1332.
DATE-2018-AntoniadisGES: EVT-based worst case delay estimation under process variation (CA, DG, NEE, GIS), pp. 1333–1338.
DATE-2018-LinHY: Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs (JML, CYH, JYY), pp. 1339–1344.
DATE-2018-LinW: Accelerate analytical placement with GPU: A generic approach (CXL, MDFW), pp. 1345–1350.
DATE-2018-JoardarDP: High performance collective communication-aware 3D Network-on-Chip architectures (BKJ, KD, PPP), pp. 1351–1356.
DATE-2018-CoelhoCZFV: A soft-error resilient route computation unit for 3D Networks-on-Chips (AC, AC, NEZ, JAF, RV), pp. 1357–1362.
DATE-2018-KoduriA: SPA: Simple pool architecture for application resource allocation in many-core systems (JSK, IA), pp. 1364–1368.
DATE-2018-YangPWWXCD0: RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems (PY0, ZP, ZW, ZW, MX, XC, LHKD, JX0), pp. 1369–1374.
DATE-2018-DuanLLJ: HME: A lightweight emulator for hybrid memory (ZD, HL, XL, HJ0), pp. 1375–1380.
DATE-2018-ElverBJN: VerC3: A library for explicit state synthesis of concurrent systems (ME, CJB, PBJ, VN), pp. 1381–1386.
DATE-2018-XiaoNB: Prometheus: Processing-in-memory heterogeneous architecture design from a multi-layer network theoretic strategy (YX, SN, PB), pp. 1387–1392.
DATE-2018-BenzGB: Advancing source-level timing simulation using loop acceleration (JB, CG, OB0), pp. 1393–1398.
DATE-2018-BhattacharjeeWH: Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip (SB, RW, JDH, BBB), pp. 1399–1404.
DATE-2018-LaiLH: Pump-aware flow routing algorithm for programmable microfluidic devices (GRL, CYL, TYH), pp. 1405–1410.
DATE-2018-JiangLLH: Adaptive approximation in arithmetic circuits: A low-power unsigned divider design (HJ, LL, FL, JH0), pp. 1411–1416.
DATE-2018-LeeAC: Correlation manipulating circuits for stochastic computing (VTL, AA, LC), pp. 1417–1422.
DATE-2018-SunYPLSY: XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks (XS, SY, XP, RL0, JsS, SY), pp. 1423–1428.
DATE-2018-FilippouKMN: A novel fault tolerant cache architecture based on orthogonal latin squares theory (FF, GK, MM, DN), pp. 1429–1434.
DATE-2018-BhattacharjeeAC: Technology-aware logic synthesis for ReRAM based in-memory computing (DB, LGA, AC), pp. 1435–1440.
DATE-2018-ErisJKMMZ: Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon (FE, AJ, ABK, YM, SAM, TZ), pp. 1441–1446.
DATE-2018-AwanoS: Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs (HA, TS), pp. 1447–1452.
DATE-2018-WangO: Efficient helper data reduction in SRAM PUFs via lossy compression (YW0, MO), pp. 1453–1458.
DATE-2018-LongWJCZM: Improving the efficiency of thermal covert channels in multi-/many-core systems (ZL, XW, YJ, GC, LZ, TSTM), pp. 1459–1464.
DATE-2018-ShahsavaniSP: A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement (SNS, AS, MP), pp. 1465–1468.
DATE-2018-SketopoulosSS: Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies (NS, CPS, SS), pp. 1469–1472.
DATE-2018-WeiSL: LESAR: A dynamic line-end spacing aware detailed router (YCW, RS, YLL), pp. 1473–1476.
DATE-2018-FusellaC: Understanding turn models for adaptive routing: The modular approach (EF, AC), pp. 1477–1480.
DATE-2018-SarkarG: Quater-imaginary base for complex number arithmetic circuits (SS, MDG), pp. 1481–1483.
DATE-2018-MoradiICS: Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis (YM, MI0, KC, US), pp. 1484–1487.
DATE-2018-CeliaVC: Optimizing power-accuracy trade-off in approximate adders (DC, VV, NC), pp. 1488–1491.
DATE-2018-KraftSMWW0: Improving the error behavior of DRAM by exploiting its Z-channel property (KK, CS, DMM, CW, NW, MJ0), pp. 1492–1495.
DATE-2018-HeittmannN: Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells (AH, TGN), pp. 1496–1499.
DATE-2018-ParkLC: Accurate prediction of smartphones' skin temperature by considering exothermic components (JP, SL, HC), pp. 1500–1503.
DATE-2018-ChatterjeeSMC: Trustworthy proofs for sensor data using FPGA based physically unclonable functions (UC, DPS, DM, RSC), pp. 1504–1507.
DATE-2018-HerdtLGD: Towards fully automated TLM-to-RTL property refinement (VH, HML, DG, RD), pp. 1508–1511.
DATE-2018-Velasquez0: In-memory computing using paths-based logic and heterogeneous components (AV, SKJ0), pp. 1512–1515.
DATE-2018-GuimaraesLBF: Non-intrusive testing technique for detection of Trojans in asynchronous circuits (LAG, TFdPL, RPB, LF), pp. 1516–1519.
DATE-2018-Grujic0RV: Towards inter-vendor compatibility of true random number generators for FPGAs (MG, BY0, VR, IV), pp. 1520–1523.
DATE-2018-ChenSZYJZ: Efficient wear leveling for inodes of file systems on persistent memories (XC, EHMS, YZ, CY, WJ, QZ), pp. 1524–1527.
DATE-2018-VedA: Exploring non-volatile main memory architectures for handheld devices (SNV, MA), pp. 1528–1531.
DATE-2018-SadighiDKMMNRWD: Design methodologies for enabling self-awareness in autonomous systems (AS, BD, TK, KM, TM, AN, AMR, TW, NDD, RE, AH, FJK), pp. 1532–1537.
DATE-2018-AhmedFM: Directed test generation using concolic testing on RTL models (AA, FF, PM0), pp. 1538–1543.
DATE-2018-VeiraPV: Suspect set prediction in RTL bug hunting (NV, ZP, AGV), pp. 1544–1549.
DATE-2018-DaneseBP: Symbolic assertion mining for security validation (AD, VB, GP), pp. 1550–1555.
DATE-2018-RitircBK: Improving and extending the algebraic approach for verifying gate-level multipliers (DR, AB, MK), pp. 1556–1561.
DATE-2018-SokolovGM: Reconfigurable asynchronous pipelines: From formal models to silicon (DS, AdG, AM), pp. 1562–1567.
DATE-2018-FedotovS: Automatic generation of hardware checkers from formal micro-architectural specifications (AF, JS), pp. 1568–1573.
DATE-2018-IannopolloTS: Specification decomposition for synthesis from libraries of LTL Assume/Guarantee contracts (AI, ST, ALSV), pp. 1574–1579.
DATE-2018-ZhouM: Hardware-assisted rootkit detection via on-line statistical fingerprinting of process execution (LZ, YM), pp. 1580–1585.
DATE-2018-SchillingWM: Securing conditional branches in the presence of fault attacks (RS, MW, SM), pp. 1586–1591.
DATE-2018-ZamanSLSMR: Towards provably-secure performance locking (MZ, AS, DL, OS, YM, JJVR), pp. 1592–1597.
DATE-2018-CruzHMB: An automated configurable Trojan insertion framework for dynamic trust benchmarks (JC, YH, PM0, SB), pp. 1598–1603.
DATE-2018-XuFHTLL: Extending the lifetime of NVMs with compression (JX, DF0, YH0, WT, JL, CL), pp. 1604–1609.
DATE-2018-KwonIYY: Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement (TK, MI, JMY, JSY), pp. 1610–1615.
DATE-2018-XuFHTLLL: An efficient PCM-based main memory system via exploiting fine-grained dirtiness of cachelines (JX, DF0, YH0, WT, JL, CL, ZL0), pp. 1616–1621.
DATE-2018-GuoHZ: DFPC: A dynamic frequent pattern compression scheme in NVM-based main memory (YG, YH0, PZ), pp. 1622–1627.
DATE-2018-TalatiAHWRGK: Practical challenges in delivering the promises of real processing-in-memory machines (NT, AHA, RBH, NW, RR, PEG, SK), pp. 1628–1633.
DATE-2018-KooliCTGN: Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces (MK, HPC, CT, BG, JPN), pp. 1634–1639.
DATE-2018-JainSW0R: Computing-in-memory with spintronics (SJ, SSS, JW0, KR0, AR), pp. 1640–1645.
DATE-2018-YuN0TH: Memristive devices for computation-in-memory (JY, HADN, LX0, MT, SH), pp. 1646–1651.
DATE-2018-VegaBB: Energy-secure swarm power management (AV, AB, PB), pp. 1652–1657.
DATE-2018-GhaemiAAF: SMARTag: Error Correction in Cache Tag Array by Exploiting Address Locality (SGG, IA, MA, HF), pp. 1658–1663.

Jan Madsen, Ayse K. CoskunProceedings of the 22nd Conference and Exhibition on Design, Automation and Test in EuropeDATE, 2018.

Contents (311 items)

Jan Madsen, Ayse K. Coskun
Proceedings of the 22nd Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2018.