Travelled to:1 × France
Collaborated with:P.Chen D.Kadetotad Z.Xu A.Mohanty B.Lin J.Ye S.B.K.Vrudhula Y.Cao S.Yu
Talks about:technolog (1) algorithm (1) acceler (1) resist (1) design (1) point (1) optim (1) learn (1) cross (1) array (1)
Person: Jae-sun Seo
DBLP: Seo:Jae=sun
Contributed to:
2015Wrote 1 papers:
- DATE-2015-ChenKXMLYVSCY #algorithm #array #learning
- Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip (PYC, DK, ZX, AM, BL, JY, SBKV, JsS, YC, SY), pp. 854–859.