Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI
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Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang, Chutong Yang
Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI
DATE, 2019.

DATE 2019
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@inproceedings{DATE-2019-HeoKKWY,
	author        = "Sun ik Heo and Andrew B. Kahng and Minsoo Kim and Lutong Wang and Chutong Yang",
	booktitle     = "{Proceedings of the 23rd Conference and Exhibition on Design, Automation and Test in Europe}",
	doi           = "10.23919/DATE.2019.8715096",
	isbn          = "978-3-9819263-2-3",
	pages         = "830--835",
	publisher     = "{IEEE}",
	title         = "{Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI}",
	year          = 2019,
}


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