BibSLEIGH — Proceedings of the 23rd Conference and Exhibition on Design, Automation and Test in Europe

Jürgen Teich, Franco Fummi
Proceedings of the 23rd Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2019.

SYS

@proceedings{DATE-2019,
	editor        = "Jürgen Teich and Franco Fummi",
	ee            = "https://ieeexplore.ieee.org/xpl/conhome/8704855/proceeding",
	isbn          = "978-3-9819263-2-3",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 23rd Conference and Exhibition on Design, Automation and Test in Europe}",
	year          = 2019,
}

Contents (329 items)

DATE-2019-Pan0RB: One Fault is All it Needs: Breaking Higher-Order Masking with Persistent Fault Analysis (JP, FZ0, KR0, SB), pp. 1–6.
DATE-2019-ElnaggarKC: Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and Defenses (RE, RK, KC), pp. 7–12.
DATE-2019-XiongASKS: Spying on Temperature using DRAM (WX, NAA, AS, SK, JS), pp. 13–18.
DATE-2019-SinghKCM: Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation Circuit (AS, MK, NC, SM), pp. 19–24.
DATE-2019-RooseCGDM: Dual-gate self-aligned a-InGaZnO transistor model for flexible circuit applications (FDR, HC, JG, WD, KM), pp. 25–29.
DATE-2019-RasheedHBBAT: Predictive Modeling and Design Automation of Inorganic Printed Electronics (FR, MH, RB, MB, JAH, MBT), pp. 30–35.
DATE-2019-HuangLSSSLBCB: Process Design Kit and Design Automation for Flexible Hybrid Electronics (TCH, TL, LS, SS, MS, SL, ZB, KTC, RGB), pp. 36–41.
DATE-2019-FattoriFHCTC: Circuit Design and Design Automation for Printed Electronics (MF, JAF, LH, EC, FT, MC), pp. 42–47.
DATE-2019-SadiqbatchaZAHT: Hot Spot Identification and System Parameterized Thermal Modeling for Multi-Core Processors Through Infrared Thermal Imaging (SS, HZ, HA, JH, SXDT), pp. 48–53.
DATE-2019-YeA0LP: Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection (WY, MBA, ML0, YL, DZP), pp. 54–59.
DATE-2019-ReidMB: PinT: Polynomial in Temperature Decode Weights in a Neuromorphic Architecture (SR, AM, KB), pp. 60–65.
DATE-2019-IranfarPZA: Enhancing Two-Phase Cooling Efficiency through Thermal-Aware Workload Mapping for Power-Hungry Servers (AI, AP, MZ, DA), pp. 66–71.
DATE-2019-WangLSL: IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design (SHW, GHL, YYS, MPHL), pp. 72–77.
DATE-2019-Toro-FriasSPMCR: Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator (ATF, PSC, FP, PML, RCL, ER, JMM, RR, MN, FVF), pp. 78–83.
DATE-2019-LeonhardYTNLCAS: MixLock: Securing Mixed-Signal Circuits via Logic Locking (JL, MY, ST, MTN, MML, RCA, HA, OS, HGDS), pp. 84–89.
DATE-2019-ZulehnerW: Matrix-Vector vs. Matrix-Matrix Multiplication: Potential in DD-based Simulation of Quantum Computations (AZ, RW), pp. 90–95.
DATE-2019-VasicekMS: Automated Circuit Approximation Method Driven by Data Distribution (ZV, VM, LS), pp. 96–101.
DATE-2019-DettererENGBJ: Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver (PD, CE, MN, JPdG, TB, HJ), pp. 102–107.
DATE-2019-SongWRPHZL0: Approximate Random Dropout for DNN training acceleration in GPGPU (ZS, RW, DR, ZP, HH, HZ, XL, LJ0), pp. 108–113.
DATE-2019-ByunHKLL: Low-Complexity Dynamic Channel Scaling of Noise-Resilient CNN for Intelligent Edge Devices (YB, MH, JK, SL, YL), pp. 114–119.
DATE-2019-WuH: Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators (HNW, CTH), pp. 120–125.
DATE-2019-ImaniMWPR: A Binary Learning Framework for Hyperdimensional Computing (MI, JM, FW, WP, TR), pp. 126–131.
DATE-2019-HenkelKR: Smart Thermal Management for Heterogeneous Multicores (JH, HK, MR), pp. 132–137.
DATE-2019-JoardarKDP: Design and Optimization of Heterogeneous Manycore Systems Enabled by Emerging Interconnect Technologies: Promises and Challenges (BKJ, RGK, JRD, PPP), pp. 138–143.
DATE-2019-BhatGO: Power and Thermal Analysis of Commercial Mobile Platforms: Experiments and Case Studies (GB, SG, ÜYO), pp. 144–149.
DATE-2019-Saraza-Canflanca: New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors (PSC, JDF, RCL, ERM, JMM, RR, MN, FVF), pp. 150–155.
DATE-2019-FengVJRV: Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors (KF, SV, RJ, ER, SV), pp. 156–161.
DATE-2019-KraakATHWCC: Methodology for Application-Dependent Degradation Analysis of Memory Timing (DK, IA, MT, SH, PW, SC, FC), pp. 162–167.
DATE-2019-KahngMST: “Unobserved Corner” Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design (ABK, UM, LS, ST), pp. 168–173.
DATE-2019-ChenY: Dim Sum: Light Clock Tree by Small Diameter Sum (GC, EFYY), pp. 174–179.
DATE-2019-HuangXFYRFCH: Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model (YHH, ZX, GQF, TCY, HR, SYF, YC, JH), pp. 180–185.
DATE-2019-Vidal-ObiolsCPO: RTL-Aware Dataflow-Driven Macro Placement (AVO, JC, JP, MGO, FM), pp. 186–191.
DATE-2019-SongXYY: Realizing Reproducible and Reusable Parallel Floating Random Walk Solvers for Practical Usage (MS, ZX, WY, LY), pp. 192–197.
DATE-2019-MarcinkeviciusB: Optically Interrogated Unique Object with Simulation Attack Prevention (PM, IEB, NMA, CSW, RJY, UR), pp. 198–203.
DATE-2019-KhalafallaG: PUFs Deep Attacks: Enhanced modeling attacks using deep learning techniques to break the security of double arbiter PUFs (MK, CHG), pp. 204–209.
DATE-2019-ShayanBSCK: Desieve the Attacker: Thwarting IP Theft in Sieve-Valve-based Biochips (MS, SB, YAS, KC, RK), pp. 210–215.
DATE-2019-ChenWZML: PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash (JC, YW0, ACZ, RM, TL), pp. 216–221.
DATE-2019-HosseiniY: Compiler-Directed and Architecture-Independent Mitigation of Read Disturbance Errors in STT-RAM (FSH, CY), pp. 222–227.
DATE-2019-LiSXYL: A Wear Leveling Aware Memory Allocator for Both Stack and Heap Management in PCM-based Main Memory Systems (WL, ZS, CJX, MY, QL), pp. 228–233.
DATE-2019-MaldonadoCRAGC: Exploiting System Dynamics for Resource-Efficient Automotive CPS Design (LM, WC, DR, AA, DG, SC), pp. 234–239.
DATE-2019-SanchezSGB: Implementation-aware design of image-based control with on-line measurable variable-delay (RMS, SS, DG, TB), pp. 240–245.
DATE-2019-OhKSN: Optimizing Assume-Guarantee Contracts for Cyber-Physical System Design (CO, EK, SS, PN), pp. 246–251.
DATE-2019-LaurentBDP: Fault Injection on Hidden Registers in a RISC-V Rocket Processor and Software Countermeasures (JL, VB, CD, FPP), pp. 252–255.
DATE-2019-LiaoG: Methodology for EM Fault Injection: Charge-based Fault Model (HL, CHG), pp. 256–259.
DATE-2019-HettwerPGNG: Securing Cryptographic Circuits by Exploiting Implementation Diversity and Partial Reconfiguration on FPGAs (BH, JP, SG, HN, TG), pp. 260–263.
DATE-2019-PerachK: STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ (BP, SK), pp. 264–267.
DATE-2019-ZhangMP: Adaptive Transient Leakage-Aware Linearised Model for Thermal Analysis of 3-D ICs (CZ, MM, VFP), pp. 268–271.
DATE-2019-SiddhuP: FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories (LS, PRP), pp. 272–275.
DATE-2019-BarraganLCLBM: On the use of causal feature selection in the context of machine-learning indirect test (MJB, GL, FC, ELL, SB, SM), pp. 276–279.
DATE-2019-ZulehnerNDW: Accuracy and Compactness in Decision Diagrams for Quantum Computation (AZ, PN, RD, RW), pp. 280–283.
DATE-2019-FrohlichGD: One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing (SF, DG, RD), pp. 284–287.
DATE-2019-MeuliSRBM: Reversible Pebbling Game for Quantum Memory Management (GM, MS, MR, NB, GDM), pp. 288–291.
DATE-2019-RekS: TypeCNN: CNN Development Framework With Flexible Data Types (PR, LS), pp. 292–295.
DATE-2019-VogelSGA: Guaranteed Compression Rate for Activations in CNNs using a Frequency Pruning Approach (SV, CS, AG, GA), pp. 296–299.
DATE-2019-ChengNY: Runtime Monitoring Neuron Activation Patterns (CHC, GN, HY), pp. 300–303.
DATE-2019-BalefGG: Chip Health Tracking Using Dynamic In-Situ Delay Monitoring (HAB, KG, JPdG), pp. 304–307.
DATE-2019-PrevilonKTK: PCFI: Program Counter Guided Fault Injection for Accelerating GPU Reliability Assessment (FGP, CK, DT, DRK), pp. 308–311.
DATE-2019-Liu0ZWLLX: Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash (WL, FW0, MZ0, YW, ZL, XL, CX), pp. 312–315.
DATE-2019-NataleVKA: Hidden-Delay-Fault Sensor for Test, Reliability and Security (GDN, EIV, KSK, LA), pp. 316–319.
DATE-2019-YiKK: Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array (WY, YK, JJK), pp. 320–323.
DATE-2019-HyunFS: Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning (DH, YF, YS), pp. 324–327.
DATE-2019-ZhaoLWWWLK: A Mixed-Height Standard Cell Placement Flow for Digital Circuit Blocks* (YCZ, YCL, TCW, THW, YRW, HCL, SYK), pp. 328–331.
DATE-2019-RokickiRD: Aggressive Memory Speculation in HW/SW Co-Designed Machines (SR, ER, SD), pp. 332–335.
DATE-2019-DasMC: Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs (SD, KJMM, PC), pp. 336–341.
DATE-2019-KhaleghiR: Thermal-Aware Design and Flow for FPGA Performance Improvement (BK, TSR), pp. 342–347.
DATE-2019-DeBGJ: FIXER: Flow Integrity Extensions for Embedded RISC-V (AD, AB, SG, TJ), pp. 348–353.
DATE-2019-LyuAM: Automated Activation of Multiple Targets in RTL Models using Concolic Testing (YL, AA, PM0), pp. 354–359.
DATE-2019-HerdtGLD: Verifying Instruction Set Simulators using Coverage-guided Fuzzing* (VH, DG, HML, RD), pp. 360–365.
DATE-2019-HassanGLD: Data Flow Testing for SystemC-AMS Timed Data Flow Models (MH, DG, HML, RD), pp. 366–371.
DATE-2019-TenaceRBCC: SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars (VT, RGR, DB, AC, AC), pp. 372–377.
DATE-2019-AngiziSZF: GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM (SA, JS, WZ0, DF), pp. 378–383.
DATE-2019-ChangMWZZ0: CORN: In-Buffer Computing for Binary Neural Network (LC0, XM, ZW, YZ, WZ, YX0), pp. 384–389.
DATE-2019-PerriconeLMNSWH: An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology (RP, ZL, MGM, MTN, SSS, JW0, XSH), pp. 390–395.
DATE-2019-KhanNG: Hardware Trojans in Emerging Non-Volatile Memories (MNIK, KN, SG), pp. 396–401.
DATE-2019-FernC: Evaluating Assertion Set Completeness to Expose Hardware Trojans and Verification Blindspots (NF, KT(C), pp. 402–407.
DATE-2019-LyuM: Efficient Test Generation for Trojan Detection using Side Channel Analysis (YL, PM0), pp. 408–413.
DATE-2019-SenguptaNKS: A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL (AS, MN, JK, OS), pp. 414–419.
DATE-2019-ParkSS: Design Optimization of Frame Preemption in Real-Time Switched Ethernet (TP, SS, KGS), pp. 420–425.
DATE-2019-RegnathS: CUBA: Chained Unanimous Byzantine Agreement for Decentralized Platoon Management (ER, SS), pp. 426–431.
DATE-2019-LamprechtBMS: Decentralized Non-Neighbor Active Charge Balancing in Large Battery Packs (AL, MB0, TM, SS), pp. 432–437.
DATE-2019-IsuwaDSM: TEEM: Online Thermal- and Energy-Efficiency Management on CPU-GPU MPSoCs (SI, SD, AKS, KDMM), pp. 438–443.
DATE-2019-SanyalBBRC: Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis (SS, PB, AB, SR, KC), pp. 444–449.
DATE-2019-SheLM: Fast and Low-Precision Learning in GPU-Accelerated Spiking Neural Network (XS, YL, SM), pp. 450–455.
DATE-2019-SeufertS: fbPDR: In-depth combination of forward and backward analysis in Property Directed Reachability (TS, CS), pp. 456–461.
DATE-2019-RoyCC: High Coverage Concolic Equivalence Checking (PR, SC, PC), pp. 462–467.
DATE-2019-ChooSCM: Bosphorus: Bridging ANF and CNF Solvers (DC, MS, KMAC, KSM), pp. 468–473.
DATE-2019-FerrellDH: CUDA au Coq: A Framework for Machine-validating GPU Assembly Programs (BF, JD, KWH), pp. 474–479.
DATE-2019-GiorgiPK: AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform (RG, MP, FK), pp. 480–485.
DATE-2019-HamdiouiNTSGPSC: Applications of Computation-In-Memory Architectures based on Memristive Devices (SH, HADN, MT, AS, MLG, SP, SS, FC, SD, FGR, GK, AR, LB), pp. 486–491.
DATE-2019-SciontiCTG: Chip-to-Cloud: an Autonomous and Energy Efficient Platform for Smart Vision Applications (AS, SC, OT, GG), pp. 492–497.
DATE-2019-SadovykhTPWABSB: On the Use of Hackathons to Enhance Collaboration in Large Collaborative Projects : - A Preliminary Case Study of the MegaM@Rt2 EU Project - (AS, DT, PP, GW, AA, HB, PS, AB, WA, AEH), pp. 498–503.
DATE-2019-SafaltinGMAGMA: Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling (SS, OG, MCM, LA, SG, CAM, MA), pp. 504–509.
DATE-2019-EhrettAB: SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design (PE, TMA, VB), pp. 510–515.
DATE-2019-NarayanTVTC: WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs (AN, YT, PV, CFT, AKC), pp. 516–521.
DATE-2019-JoardarLDLPC: REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs (BKJ, BL0, JRD, HL0, PPP, KC), pp. 522–527.
DATE-2019-ShihabTRHSSSM: Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming (MMS, JT, GRR, BH, WS, BCS, CS, YM), pp. 528–533.
DATE-2019-Shamsi0PJ: KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation (KS, ML0, DZP, YJ), pp. 534–539.
DATE-2019-LiO: Piercing Logic Locking Keys through Redundancy Identification (LL, AO), pp. 540–545.
DATE-2019-SinglaSS: FlexiCheck: An Adaptive Checkpointing Architecture for Energy Harvesting Devices (PS, SSS, SRS), pp. 546–551.
DATE-2019-GlaserHRHB: Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters (FG, GH, DR, QH, LB), pp. 552–557.
DATE-2019-CosteroIZIOA: MAMUT: Multi-Agent Reinforcement Learning for Efficient Real-Time Multi-User Video Transcoding (LC, AI, MZ, FDI, KO, DA), pp. 558–563.
DATE-2019-AhmedSLMABC: A Compiler for Automatic Selection of Suitable Processing-in-Memory Instructions (HA, PCS, JPCdL, RFdM, MAZA, ACSB, LC), pp. 564–569.
DATE-2019-Maghazeh0EP: Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based Applications (AM, SC0, PE, ZP), pp. 570–575.
DATE-2019-KimVCR: Data Subsetting: A Data-Centric Approach to Approximate Computing (YK, SV, NC, AR), pp. 576–581.
DATE-2019-Brandalero0CB: TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration (MB, MS0, LC, ACSB), pp. 582–585.
DATE-2019-ImaniGHR: CADE: Configurable Approximate Divider for Energy Efficiency (MI, RG, AH, TR), pp. 586–589.
DATE-2019-ChenLPLLX: HCFTL: A Locality-Aware Page-Level Flash Translation Layer (HC, CL, YP, ML, YL, YX), pp. 590–593.
DATE-2019-ZhangT0: Model Checking is Possible to Verify Large-scale Vehicle Distributed Application Systems (HZ, AT, GL0), pp. 594–597.
DATE-2019-ZhaoH: Automatic Assertion Generation from Natural Language Specifications Using Subtree Analysis (JZ, IGH), pp. 598–601.
DATE-2019-LeGBD: Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing (HML, DG, NB, RD), pp. 602–605.
DATE-2019-SchonbergerBSC: Design Optimization for Hardware-Based Message Filters in Broadcast Buses (LS, GvdB, HS, JJC), pp. 606–609.
DATE-2019-HuangTLH: Vehicle Sequence Reordering with Cooperative Adaptive Cruise Control (TWH, YYT, CWL, TYH), pp. 610–613.
DATE-2019-Strnadel: Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates (JS), pp. 614–617.
DATE-2019-GoelS: Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs (AG, KAS), pp. 618–621.
DATE-2019-MasourosKZKCXCS: Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach (DM, KK, GZ, AK, AC, SX, IC, DS), pp. 622–625.
DATE-2019-KoromilasKSBMJ: Modular FPGA Acceleration of Data Analytics in Heterogenous Computing (EK, CK, DS, FJB, PM, RJP), pp. 626–629.
DATE-2019-XiaoWPSM: ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip (SX, XW, MP, AKS0, TSTM), pp. 630–633.
DATE-2019-AlhubailB: Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models (LA, NB), pp. 634–637.
DATE-2019-FayyaziSNNP: Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations (AF, SS, PN, SN, MP), pp. 638–641.
DATE-2019-WangS: Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis (ZW, BCS), pp. 642–645.
DATE-2019-AmorB: Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT (HBA, CB), pp. 646–649.
DATE-2019-ForsbergBM: Taming Data Caches for Predictable Execution on GPU-based SoCs (BF, LB, AM), pp. 650–653.
DATE-2019-TagliaviniMRMB: Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA (GT, SM, DR, AM, LB), pp. 654–657.
DATE-2019-QianLMG: vDARM: Dynamic Adaptive Resource Management for Virtualized Multiprocessor Systems (JQ, JL0, RM, HG), pp. 658–661.
DATE-2019-SchuikiSB: NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22 nm FD-SOI (FS, MS, LB), pp. 662–667.
DATE-2019-LunterenLDAHCCS: Coherently Attached Programmable Near-Memory Acceleration Platform and its application to Stencil Processing (JvL, RL, DD, FA, CH, LC, SC, GS), pp. 668–673.
DATE-2019-VivetSMCCCABVLD: Advanced 3D Technologies and Architectures for 3D Smart Image Sensors (PV, GS, LM, SC, KBC, LAC, MA, MB, AV, ML, TD, OB, ST, DL, SC, PB, FC), pp. 674–679.
DATE-2019-MudassarSLAGNKW: A Camera with Brain - Embedding Machine Learning in 3D Sensors (BAM, PS, YL, MFA, EG, TN, JHK, MW, SM), pp. 680–685.
DATE-2019-OhC0KCLPBYKSB: IoT2 - the Internet of Tiny Things: Realizing mm-Scale Sensors through 3D Die Stacking (SO, MC, XW0, YK, LXC, WL, PP, SB, KY, HSK, DS, DTB), pp. 686–691.
DATE-2019-HuangCW: Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications (NCH, SYC, KCW), pp. 692–697.
DATE-2019-TsiokanosMK: Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation (IT, LM, GK), pp. 698–703.
DATE-2019-BiasielliBCM: A Smart Fault Detection Scheme for Reliable Image Processing Applications (MB, CB, LC, AM), pp. 704–709.
DATE-2019-CardonaHAC: Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement (JC, CH, JA, FJC), pp. 710–715.
DATE-2019-Alipour0KB: FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors (MA, RK0, SK, DBS), pp. 716–721.
DATE-2019-JordanKVR: Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection (MGJ, TK, JV, MBR), pp. 722–727.
DATE-2019-SayadiMDMSRH: 2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection (HS, HMM, SMPD, TM, AS, SR, HH), pp. 728–733.
DATE-2019-KrishnanSDS: Secure Intermittent Computing Protocol: Protecting State Across Power Loss (ASK, CS, DD, PS), pp. 734–739.
DATE-2019-HwangYJLKP: RiskiM: Toward Complete Kernel Protection with Hardware Support (DH, MY, SJ, YL, DK, YP), pp. 740–745.
DATE-2019-VliegenRCM: SACHa: Self-Attestation of Configurable Hardware (JV, MMR, MC, NM), pp. 746–751.
DATE-2019-BurrelloCSBR: Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False Alarms (AB, LC, KS, LB, AR), pp. 752–757.
DATE-2019-VenutoM: Automatic Time-Frequency Analysis of MRPs for Mind-controlled Mechatronic Devices (DDV, GM), pp. 758–763.
DATE-2019-PascualAA: A Self-Learning Methodology for Epileptic Seizure Detection with Minimally-Supervised Edge Labeling (DP, AA, DA), pp. 764–769.
DATE-2019-ChhetriLWF: GAN-Sec: Generative Adversarial Network Modeling for the Security Analysis of Cyber-Physical Production Systems (SRC, ABL, JW, MAAF), pp. 770–775.
DATE-2019-DinakarraoSMNRH: Lightweight Node-level Malware Detection and Network-level Malware Confinement in IoT Networks (SMPD, HS, HMM, CN, SR, HH), pp. 776–781.
DATE-2019-BuXRYWL: Incremental Online Verification of Dynamic Cyber-Physical Systems (LB, SX, XR, YY, QW, XL), pp. 782–787.
DATE-2019-VatanparvarF: Self-Secured Control with Anomaly Detection and Recovery in Automotive Cyber-Physical Systems (KV, MAAF), pp. 788–793.
DATE-2019-YuNLTH: Time-division Multiplexing Automata Processor (JY, HADN, MAL, MT, SH), pp. 794–799.
DATE-2019-GlovaALHX: Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory (AOG, IA, SL, XH0, YX0), pp. 800–805.
DATE-2019-WuWZMSL: Towards Cross-Platform Inference on Edge Devices with Emerging Neuromorphic Architecture (SW, YW0, ACZ, RM, ZS, TL), pp. 806–811.
DATE-2019-GaborSBANPKD: Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core (RG, YS, AB, AA, CN, KP, DK, GD), pp. 812–817.
DATE-2019-BenedicteHAC: LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache (PB, CH, JA, FJC), pp. 818–823.
DATE-2019-AlcaideKHA: High-Integrity GPU Designs for Critical Real-Time Automotive Systems (SA, LK, CH, JA), pp. 824–829.
DATE-2019-HeoKKWY: Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI (SiH, ABK, MK, LW, CY), pp. 830–835.
DATE-2019-WangWSZZ: Optimizing the Energy Efficiency of Power Supply in Heterogeneous Multicore Chips with Integrated Switched-Capacitor Converters (LW, LW, DS, CZ, PZ), pp. 836–841.
DATE-2019-KahngKKSX: Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology (ABK, SK, SK, KS, BX), pp. 842–847.
DATE-2019-MocerinoTC: Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse (LM, VT, AC), pp. 848–853.
DATE-2019-CheshmikhaniFA: Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation (EC, HF, HA), pp. 854–859.
DATE-2019-TanWYDCL: UIMigrate: Adaptive Data Migration for Hybrid Non-Volatile Memory Systems (YT, BW, ZY, QD, XC, DL), pp. 860–865.
DATE-2019-YangLCZWDT: Reducing Write Amplification for Inodes of Journaling File System using Persistent Memory (CY, DL, XC, RZ, WW, MD, YT), pp. 866–871.
DATE-2019-ProbstlPSC: Cost/Privacy Co-optimization in Smart Energy Grids (AP, SP, SS, SC), pp. 872–877.
DATE-2019-SioziosS: A Low-Complexity Framework for Distributed Energy Market Targeting Smart-Grid (KS, SS), pp. 878–883.
DATE-2019-PagliariVMP: Irradiance-Driven Partial Reconfiguration of PV Panels (DJP, SV, EM, MP), pp. 884–889.
DATE-2019-RingBLWD: Better Late Than Never : Verification of Embedded Systems After Deployment (MR, FB, CL, RW, RD), pp. 890–895.
DATE-2019-ChenUBC: Efficient Computation of Deadline-Miss Probability and Potential Pitfalls (KHC, NU, GvdB, JJC), pp. 896–901.
DATE-2019-KhalidHRQ0: FAdeML: Understanding the Impact of Pre-Processing Noise Filtering on Adversarial Machine Learning (FK, MAH, SR, JQ0, MS0), pp. 902–907.
DATE-2019-OhYCCYP: Real-Time Anomalous Branch Behavior Inference with a GPU-inspired Engine for Machine Learning Models (HO, HY, HC, YC, SY, YP), pp. 908–913.
DATE-2019-AbbassiKRKJG0: TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint (IHA, FK, SR, AMK, AJ, SG, MS0), pp. 914–919.
DATE-2019-BernardiCFPPRSL: Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions (PB, RC, AF, DP, CP, AR, ES0, SdL, AS), pp. 920–923.
DATE-2019-SeoK: Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput Multipliers (JS, DHK), pp. 924–927.
DATE-2019-AnsariC0: A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy (MSA, BFC, JH0), pp. 928–931.
DATE-2019-CilardoGS: Lightweight hardware support for selective coherence in heterogeneous manycore accelerators (AC, MG, VS), pp. 932–935.
DATE-2019-SironeS: Functional Analysis Attacks on Logic Locking (DS, PS), pp. 936–939.
DATE-2019-ShenLKRZ: SigAttack: New High-level SAT-based Attack on Logic Encryptions (YS, YL, SK, AR, HZ), pp. 940–943.
DATE-2019-MayerSM: ZeroPowerTouch: Zero-Power Smart Receiver for Touch Communication and Sensing in Wearable Applications (PM, RS, MM), pp. 944–947.
DATE-2019-FerrettiAPAACR: Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors (LF, GA, LP, AA, DA, LC, PR), pp. 948–951.
DATE-2019-DemroziBTP: An indoor localization system to detect areas causing the freezing of gait in Parkinsonians (FD, VB, FT, GP), pp. 952–955.
DATE-2019-FischbachHL: Assembly-Related Chip/Package Co-Design of Heterogeneous Systems Manufactured by Micro-Transfer Printing (RF, TH, JL), pp. 956–959.
DATE-2019-MandalJOKGNRSHR: Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power (DKM, SJ, OJO, GSK, BG, GN, SKR, SS, LH, JR, EJ, BK, HW0), pp. 960–963.
DATE-2019-MarchisioH0: CapsAcc: An Efficient Hardware Accelerator for CapsuleNets with Data Reuse (AM, MAH, MS0), pp. 964–967.
DATE-2019-ChangKK: SDCNN: An Efficient Sparse Deconvolutional Neural Network Accelerator on FPGA (JWC, KWK, SJK), pp. 968–971.
DATE-2019-HussainSH: A Fine-Grained Soft Error Resilient Architecture under Power Considerations (SH, MS0, JH), pp. 972–975.
DATE-2019-PsiakisKS: Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units (RP, AK, OS), pp. 976–979.
DATE-2019-MaragkoudakiMP: Adaptive Word Reordering for Low-Power Inter-Chip Communication (EM, PM, VFP), pp. 980–983.
DATE-2019-CuiYLZG: Machine-Learning-Driven Matrix Ordering for Power Grid Analysis (GC, WY, XL, ZZ, BG), pp. 984–987.
DATE-2019-BrignonP: Assertion-Based Verification through Binary Instrumentation (EB, LP), pp. 988–991.
DATE-2019-CoxC: Hardware and firmware verification and validation: an algorithm-to-firmware development methodology (HC, HHC), pp. 992–993.
DATE-2019-FadihehSBMK: Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking (MRF, DS, CWB, SM, WK), pp. 994–999.
DATE-2019-SinghDSSGFSKBEM: Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study (ES, KD, SS, RS, KG, MRF, DS, WK, CWB, WE, SM), pp. 1000–1005.
DATE-2019-GielenXGM: Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs (GGEG, NX, KG, SM), pp. 1006–1009.
DATE-2019-LuoLW0: On Functional Test Generation for Deep Neural Network IPs (BL, YL, LW, QX0), pp. 1010–1015.
DATE-2019-RaiolaTBALW00: On Secure Data Flow in Reconfigurable Scan Networks (PR, BT, JB, AA, NL, HJW, BB0, MS0), pp. 1016–1021.
DATE-2019-WangPRSV: Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines (NW, IP, SMR, AS, SV), pp. 1022–1027.
DATE-2019-GebregiorgisT: Test Pattern Generation for Approximate Circuits Based on Boolean Satisfiability (AG, MBT), pp. 1028–1033.
DATE-2019-HemmatiBN: Adaptive Vehicle Detection for Real-time Autonomous Driving System (MH, MBA, SN), pp. 1034–1039.
DATE-2019-WeiYZZ0: An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel (XW, CY, HZ, DZ, XZ0), pp. 1040–1045.
DATE-2019-GueguenST: Accelerating Itemset Sampling using Satisfiability Constraints on FPGA (MG, OS, AT), pp. 1046–1051.
DATE-2019-HanXDSS: DS-Cache: A Refined Directory Entry Lookup Cache with Prefix-Awareness for Mobile Devices (LH, BX, XD, ZS, ZS), pp. 1052–1057.
DATE-2019-MaGCHW: Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators (SM, YG0, SC, LH, ZW), pp. 1058–1063.
DATE-2019-Qin0TLZ: QBLK: Towards Fully Exploiting the Parallelism of Open-Channel SSDs (HQ, DF0, WT, JL, YZ), pp. 1064–1069.
DATE-2019-FerragutiPSFB: A Methodology for Comparative Analysis of Collaborative Robots for Industry 4.0 (FF, AP, CS, CF, MB), pp. 1070–1075.
DATE-2019-SchoenliebPSHD: Hybrid Sensing Approach For Coded Modulation Time-of-Flight Cameras (AS, HP, CS, GH, ND), pp. 1076–1081.
DATE-2019-RazaviBK: Communication-Computation co-Design of Decentralized Task Chain in CPS Applications (SAR, EB, SSK), pp. 1082–1087.
DATE-2019-FukutomiAKN: Resource Manager for Scalable Performance in ROS Distributed Environments (DF, TA, SK, NN), pp. 1088–1093.
DATE-2019-VogelSGA19a: Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless Acceleration (SV, JS, AG, GA), pp. 1094–1099.
DATE-2019-HoVW: Multi-objective Precision Optimization of Deep Neural Networks for Edge Devices (NMH, RV, WFW), pp. 1100–1105.
DATE-2019-AhmadP: Towards Design Space Exploration and Optimization of Fast Algorithms for Convolutional Neural Networks (CNNs) on FPGAs (AA, MAP), pp. 1106–1111.
DATE-2019-LinLAT0: Accelerating Local Binary Pattern Networks with Software-Programmable FPGAs (JHL, AL, VA, ZT, RKG0), pp. 1112–1117.
DATE-2019-BadierLCG: Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment (HB, JCLL, PC, GG), pp. 1118–1123.
DATE-2019-PilatoBSRK: High-Level Synthesis of Benevolent Trojans (CP, KB, MS, FR0, RK), pp. 1124–1129.
DATE-2019-ZhaoLSZ: Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis (JZ, TL, SS, WZ0), pp. 1130–1135.
DATE-2019-WernerSUM: Protecting RISC-V Processors against Physical Attacks (MW, RS, TU, SM), pp. 1136–1141.
DATE-2019-LebedevHDKLASD: Sanctorum: A lightweight security monitor for secure enclaves (IAL, KH, JD, DK, DL, KA, DS, SD), pp. 1142–1147.
DATE-2019-FritzmannSMRSS: Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V (TF, US, DMG, CR, US, JS), pp. 1148–1153.
DATE-2019-AuerSH: A Security Architecture for RISC-V based IoT Devices (LA, CS, MH), pp. 1154–1159.
DATE-2019-CharlesLM: Real-time Detection and Localization of DoS Attacks in NoC based SoCs (SC, YL, PM0), pp. 1160–1165.
DATE-2019-WangLKB: High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin (KW, AL, AK, RCB), pp. 1166–1171.
DATE-2019-ZouWLL: Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture (KZ, YW0, HL, XL0), pp. 1172–1177.
DATE-2019-WangL: Advance Virtual Channel Reservation (BW, ZL), pp. 1178–1183.
DATE-2019-LalLJ: SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs (SL, JL, BHHJ), pp. 1184–1189.
DATE-2019-TanYSF: LoSCache: Leveraging Locality Similarity to Build Energy-Efficient GPU L2 Cache (JT, KY, SLS, XF), pp. 1190–1195.
DATE-2019-AhmadianSA: LBICA: A Load Balancer for I/O Cache Architectures (SA, RS, HA), pp. 1196–1201.
DATE-2019-MezzettiBABC: AURIX TC277 Multicore Contention Model Integration for Automotive Applications (EM, LB, JA, SB, FJC), pp. 1202–1203.
DATE-2019-KangPBCLLL: Seamless SoC Verification Using Virtual Platforms: An Industrial Case Study (KK, SP, BB, JC, SL, BL, JBL), pp. 1204–1205.
DATE-2019-FernandezFAC: Multicore Early Design Stage Guaranteed Performance Estimates for the Space Domain (MF, GF, JA, FJC), pp. 1206–1207.
DATE-2019-Lehnigk-EmdenAK: Polar Code Decoder Framework (TLE, MA, CK, NW), pp. 1208–1209.
DATE-2019-KohlerNEB: Increasing Accuracy of Timing Models: From CPA to CPA+ (LK, BN, RE, MB), pp. 1210–1215.
DATE-2019-SchoeberlSBS: Scratchpad Memories with Ownership (MS, TBS, OB, JS), pp. 1216–1221.
DATE-2019-ChenFWLS: A Container-based DoS Attack-Resilient Control Framework for Real-Time UAV Systems (JC, ZF, JYW, BL, LS), pp. 1222–1227.
DATE-2019-YalcinkayaNB: An Exact Schedulability Test for Non-Preemptive Self-Suspending Real-Time Tasks (BY, MN, BBB), pp. 1228–1233.
DATE-2019-WilleMN: IBM's Qiskit Tool Chain: Working with and Developing for Real Quantum Computers (RW, RVM, YN), pp. 1234–1240.
DATE-2019-ZhangZSLX: An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA Architectures (WZ, JZ, MS, GL, NX), pp. 1241–1244.
DATE-2019-BaoC0: A Write-Efficient Cache Algorithm based on Macroscopic Trend for NVM-based Read Cache (NB, YC, XQ0), pp. 1245–1248.
DATE-2019-ListlMSN: SRAM Design Exploration with Integrated Application-Aware Aging Analysis (AL, DMG, US, SRN), pp. 1249–1252.
DATE-2019-CentomoFP: From Multi-Level to Abstract-Based Simulation of a Production Line (SC, EF, MP), pp. 1253–1256.
DATE-2019-PencelliVAFNRRZ: Accurate Dynamic Modelling of Hydraulic Servomechanisms (MP, RV, AA, GF, MN, MR, PR, AMZ), pp. 1257–1260.
DATE-2019-PiccinelliVM: Planning with Real-Time Collision Avoidance for Cooperating Agents under Rigid Body Constraints (NP, FV, RM), pp. 1261–1264.
DATE-2019-HsiehSD: The Case for Exploiting Underutilized Resources in Heterogeneous Mobile Architectures (CYH, AAS, NDD), pp. 1265–1268.
DATE-2019-CuiLNX: Online Rare Category Detection for Edge Computing (YC, QL0, SN, CJX), pp. 1269–1272.
DATE-2019-Huang0L0YG: RAGra: Leveraging Monolithic 3D ReRAM for Massively-Parallel Graph Processing (YH0, LZ0, XL, HJ0, PY, CG), pp. 1273–1276.
DATE-2019-ServadeiZDMEW: Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision (LS, EZ, KD, MM, WE, RW), pp. 1277–1280.
DATE-2019-SmythSH: Practical Causality Handling for Synchronous Languages (SS, ASR, RvH), pp. 1281–1284.
DATE-2019-KimMSR: Application Performance Prediction and Optimization Under Cache Allocation Technology (YK, AM, ES, TR), pp. 1285–1288.
DATE-2019-HashemiR: Generalized Matrix Factorization Techniques for Approximate Logic Synthesis (SH, SR), pp. 1289–1292.
DATE-2019-YangHZWL: CARS: A Multi-layer Conflict-Aware Request Scheduler for NVMe SSDs (TY, PH, WZ, HW, LL), pp. 1293–1296.
DATE-2019-WittigHMF: Queue Based Memory Management Unit for Heterogeneous MPSoCs (RW, MH, EM, GPF), pp. 1297–1300.
DATE-2019-EckerDWHS: Embedded Systems' Automation following OMG's Model Driven Architecture Vision (WE, KD, MW, ZH, LS), pp. 1301–1306.
DATE-2019-KalyanaramanP: A Brief Survey of Algorithms, Architectures, and Challenges toward Extreme-scale Graph Analytics (AK, PPP), pp. 1307–1312.
DATE-2019-CastellanaDFFKL: A Parallel Graph Environment for Real-World Data Analytics Workflows (VGC, MD, JF, JSF, TAK, AL, JBM, AM, MM, JS, AT, MZ), pp. 1313–1318.
DATE-2019-GrintenM: Scaling up Network Centrality Computations * (AvdG, HM), pp. 1319–1324.
DATE-2019-DavilaONR: Identifying the Most Reliable Collaborative Workload Distribution in Heterogeneous Devices (GPD, DO, POAN, PR), pp. 1325–1330.
DATE-2019-LiWZCH: CE-Based Optimization for Real-time System Availability under Learned Soft Error Rate (LL, TW, JZ, MC, XSH), pp. 1331–1336.
DATE-2019-ChenZPJ: A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Wafer-Level NoC (ZC, YZ0, ZP, JJ), pp. 1337–1342.
DATE-2019-FletcherDM: CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs (BJF, SD, TSTM), pp. 1343–1348.
DATE-2019-SoekenMSM: Compiling Permutations for Superconducting QPUs (MS, FM, BS, GDM), pp. 1349–1354.
DATE-2019-El-DerhalliBT: Stochastic Computing with Integrated Optics (HED, SLB, ST), pp. 1355–1360.
DATE-2019-ErozanBAT: Inkjet-Printed True Random Number Generator based on Additive Resistor Tuning (ATE, RB, JAH, MBT), pp. 1361–1366.
DATE-2019-WuZMJ: HotR: Alleviating Read/Write Interference with Hot Read Data Replication for Flash Storage (SW, WZ, BM, HJ), pp. 1367–1372.
DATE-2019-TangWZLXWX: RAFS: A RAID-Aware File System to Reduce the Parity Update Overhead for SSD RAID (CT, JW, YZ, ZL, PX, FW0, CX), pp. 1373–1378.
DATE-2019-LiWJ: Automatic data placement for CPU-FPGA heterogeneous multiprocessor System-on-Chips (SL, YW, LJ), pp. 1379–1384.
DATE-2019-AngiolettiBBCM: A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous Multicores (DA, FB, CB, FC, AM), pp. 1385–1390.
DATE-2019-KatsaragakisMTS: DMRM: Distributed Market-Based Resource Management of Edge Computing Systems (MK, DM, VT, FS, LB, JH, DS), pp. 1391–1396.
DATE-2019-ShamsaKRLJD: Goal-Driven Autonomy for Efficient On-chip Resource Management: Transforming Objectives to Goals (ES, AK, AMR, PL, AJ, NDD), pp. 1397–1402.
DATE-2019-JiangH0: Scrub Unleveling: Achieving High Data Reliability at Low Scrubbing Cost (TJ, PH0, KZ0), pp. 1403–1408.
DATE-2019-PradoPB: Learning to infer: RL-based search for DNN primitive selection on Heterogeneous Embedded Systems (MdP, NP, LB), pp. 1409–1414.
DATE-2019-ZhaoHLYDJXWX: Memory Trojan Attack on Neural Network Accelerators (YZ, XH0, SL, JY, LD0, YJ0, JX, DW, YX0), pp. 1415–1420.
DATE-2019-CarmichaelLKLGK: Deep Positron: A Deep Neural Network Using the Posit Number System (ZC, HFL, CK, JL, JLG, DK), pp. 1421–1426.
DATE-2019-ArdakaniJG: Learning to Skip Ineffectual Recurrent Computations in LSTMs (AA, ZJ, WJG), pp. 1427–1432.
DATE-2019-BalakrishnanPQDDAF: Specifying and Evaluating Quality Metrics for Vision-based Perception Systems (AB, AGP, XQ, AD, JVD, HBA, GF), pp. 1433–1438.
DATE-2019-ChakrabortyA0GH: Cross-Layer Interactions in CPS for Performance and Certification (SC, JHA, MB0, HG, SH, RM, LT, ST, AY), pp. 1439–1444.
DATE-2019-TalpinMNSG: Towards verified programming of embedded devices (JPT, JJM, SN, DS, RG0), pp. 1445–1450.
DATE-2019-TarrafH: Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata (AT, LH), pp. 1451–1456.
DATE-2019-Zivkovic0: Nubolic Simulation of AMS Systems with Data Flow and Discrete Event Models (CZ, CG0), pp. 1457–1462.
DATE-2019-ZhangLYYZ0: Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network (SZ, WL, FY0, CY, DZ, XZ0), pp. 1463–1468.
DATE-2019-CadareanuCAKRDB: Rebooting Our Computing Models (PC, NRC, CGA, AK, AR, SD, KB, VN, MDV, PEG), pp. 1469–1476.
DATE-2019-CaoHCZ: NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support (WC, XH, AC, XZ), pp. 1477–1482.
DATE-2019-LiuLYLXJ: HolyLight: A Nanophotonic Accelerator for Deep Learning in Data Centers (WL, WL, YY, QL, YX, LJ0), pp. 1483–1488.
DATE-2019-YoonARR: Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous Drones (IY, MAA, TR, AR), pp. 1489–1494.
DATE-2019-AhnHKJLCLK: AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognition (MA, SJH, WK, SJ, YL, MC, WL, YJK), pp. 1495–1500.
DATE-2019-LeeLE: VM-aware Flush Mechanism for Mitigating Inter-VM I/O Interference (THL, ML, YIE), pp. 1501–1506.
DATE-2019-SchornGA: An Efficient Bit-Flip Resilience Optimization Method for Deep Neural Networks (CS, AG, GA), pp. 1507–1512.
DATE-2019-MoKS: Approximation-aware Task Deployment on Asymmetric Multicore Processors (LM, AK, OS), pp. 1513–1518.
DATE-2019-IbrahimBC: BioScan: Parameter-Space Exploration of Synthetic Biocircuits Using MEDA Biochips∗ (MI0, BBB, KC), pp. 1519–1524.
DATE-2019-ChenHGLHS: Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage (ZC, XH, WG, BL0, TYH, US), pp. 1525–1530.
DATE-2019-LinHLS: Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices (YHL, TYH, BL0, US), pp. 1531–1536.
DATE-2019-JiangGLL: Analyzing GEDF Scheduling for Parallel Real-Time Tasks with Arbitrary Deadlines (XJ, NG, DL, WL), pp. 1537–1542.
DATE-2019-PazzagliaBN: Simple and General Methods for Fixed-Priority Schedulability in Optimization Problems (PP, AB, MDN), pp. 1543–1548.
DATE-2019-NiknamWS: Hard Real-Time Scheduling of Streaming Applications Modeled as Cyclic CSDF Graphs (SN, PW0, TPS), pp. 1549–1554.
DATE-2019-HussainSH19a: Thermal-Awareness in a Soft Error Tolerant Architecture (SH, MS0, JH), pp. 1555–1558.
DATE-2019-SoDSL: A software-level Redundant MultiThreading for Soft/Hard Error Detection and Recovery (HS, MD, AS, KL), pp. 1559–1562.
DATE-2019-TaherJBZS: Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis (FNT, MJ, AB, ZZ, BCS), pp. 1563–1566.
DATE-2019-Zhao0YXFCP: Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis (ZZ, DL0, ZY, BX, CF, RTC, DZP), pp. 1567–1570.
DATE-2019-Papagiannopoulou: IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM (DP, SW, TM, RIB), pp. 1571–1574.
DATE-2019-MasadehHT: Using Machine Learning for Quality Configurable Approximate Computing (MM, OH, ST), pp. 1575–1578.
DATE-2019-RappPMH: Prediction-Based Task Migration on S-NUCA Many-Cores (MR, AP, TM, JH), pp. 1579–1582.
DATE-2019-LagunaNH: Design of Hardware-Friendly Memory Enhanced Neural Networks (AFL, MTN, XSH), pp. 1583–1586.
DATE-2019-ParkJKY: Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (SP, JJ, SJK, SY), pp. 1587–1590.
DATE-2019-ImaniKWGR: HDCluster: An Accurate Clustering Using Brain-Inspired High-Dimensional Computing (MI, YK, TW, SG, TR), pp. 1591–1594.
DATE-2019-AkhterRG: Finding All DC Operating Points Using Interval Arithmetic Based Verification Algorithms (IAA, JR, MRG), pp. 1595–1598.
DATE-2019-ChenLYYWZ: GENIE: QoS-guided Dynamic Scheduling for CNN-based Tasks on SME Clusters (ZC, LL, HY, JY, MW, CZ), pp. 1599–1602.
DATE-2019-MileikoSYE: A Pulse Width Modulation based Power-elastic and Robust Mixed-signal Perceptron Design (SM, RAS, AY, JE), pp. 1603–1606.
DATE-2019-BernardiniLLS: Fault Localization in Programmable Microfluidic Devices (AB, CL, BL0, US), pp. 1607–1610.
DATE-2019-LiuLCXXGJ: Thermal Sensing Using Micro-ring Resonators in Optical Network-on-Chip (WL, ML, WC, CX, YX, NG, LJ0), pp. 1611–1614.
DATE-2019-MaheshwariK: Adiabatic Implementation of Manchester Encoding for Passive NFC System (SM, IK), pp. 1615–1618.
DATE-2019-ZhangKBS: Semantic Integration Platform for Cyber-Physical System Design (QZ, TK, TB, JS), pp. 1619–1624.
DATE-2019-AbdullahD0: Worst-Case Cause-Effect Reaction Latency in Systems with Non-Blocking Communication (JA, GD, WY0), pp. 1625–1630.
DATE-2019-ApvrilleL: Harmonizing Safety, Security and Performance Requirements in Embedded Systems (LA, LWL), pp. 1631–1636.
DATE-2019-AksoyA: A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices (LA, MA), pp. 1637–1642.
DATE-2019-TestaASMVLCGM: Scalable Boolean Methods in a Modern Synthesis Flow (ET, LGA, MS, AM, PV, JL, CC, PEG, GDM), pp. 1643–1648.
DATE-2019-RienerHMMS: On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis (HR, WH, AM, GDM, MS), pp. 1649–1654.
DATE-2019-BernasconiCV: Approximate Logic Synthesis by Symmetrization (AB, VC, TV), pp. 1655–1660.
DATE-2019-LinSHNTH: Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation (TYL, CS, CCH, KN, CT, SCH), pp. 1661–1666.
DATE-2019-WellerHGBT: Bayesian Optimized Importance Sampling for High Sigma Failure Rate Estimation (DDW, MH, MSG, MB, MBT), pp. 1667–1672.
DATE-2019-XanthopoulosNBN: Wafer-Level Adaptive Vmin Calibration Seed Forecasting (CX, DN, SB, AN, YM), pp. 1673–1678.
DATE-2019-YanHSW: Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications (AY, YH, JS, XW), pp. 1679–1684.
DATE-2019-EdunVGS: Dynamic Scheduling on Heterogeneous Multicores (AE, RV, AGR, GS), pp. 1685–1690.
DATE-2019-SalaminAH: Selecting the Optimal Energy Point in Near-Threshold Computing (SS, HA, JH), pp. 1691–1696.
DATE-2019-FeyerickRV: Exploration and Design of Low-Energy Logic Cells for 1 kHz Always-on Systems (MF, JDR, MV), pp. 1697–1702.
DATE-2019-PelusoCCPTM: Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms (VP, AC, AC, MP, FT, SM), pp. 1703–1708.
DATE-2019-FradetGKN0: RDF: Reconfigurable Dataflow (PF, AG, RK, XN, AS0), pp. 1709–1714.
DATE-2019-StemmerSFGN: Probabilistic State-Based RT-Analysis of SDFGs on MPSoCs with Shared Memory Communication (RS, HS, MF, KG, WN), pp. 1715–1720.
DATE-2019-JungSDKW: Speculative Temporal Decoupling Using fork() (MJ, FS, MD, TK, NW), pp. 1721–1726.
DATE-2019-GuoZJZ: When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans (XG, HZ, YJ, XZ), pp. 1727–1732.
DATE-2019-AwanoI: Fourℚ on ASIC: Breaking Speed Records for Elliptic Curve Scalar Multiplication (HA, MI), pp. 1733–1738.
DATE-2019-BianHS: DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference (SB, MH, TS), pp. 1739–1744.
DATE-2019-MahmoudS: Timing Violation Induced Faults in Multi-Tenant FPGAs (DM, MS), pp. 1745–1750.
DATE-2019-ZhangZLLS: Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing (SZ, GLZ, BL0, HHL, US), pp. 1751–1756.
DATE-2019-FarajiNLLB: Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing (SRF, MHN, BL, DJL, KB), pp. 1757–1762.
DATE-2019-FanLLCL: RED: A ReRAM-based Deconvolution Accelerator (ZF, ZL, BL0, YC, HHL), pp. 1763–1768.
DATE-2019-LongSM: Design of Reliable DNN Accelerator with Un-reliable ReRAM (YL, XS, SM), pp. 1769–1774.

Jürgen Teich, Franco FummiProceedings of the 23rd Conference and Exhibition on Design, Automation and Test in EuropeDATE, 2019.

Contents (329 items)

Jürgen Teich, Franco Fummi
Proceedings of the 23rd Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2019.