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Travelled to:
1 × India
22 × USA
5 × France
5 × Germany
Collaborated with:
P.Gupta S.Kang I.L.Markov C.J.Alpert S.Muddu G.Robins S.Nath D.Sylvester A.E.Caldwell S.Reda B.Lin J.Cong C.A.Tsao Y.Chen P.Sharma K.Samadi Q.Wang H.Lee L.W.Hagen D.J.Huang A.Zelikovsky S.Mantik E.Sarto K.D.Boese W.J.Chan K.Han S.Shah G.Jerke I.Kang R.Kumar J.Sartori C.Park Y.C.Pati K.Jeong Y.Kim J.Yang M.Potkonjak T.Chan B.Park P.Dasgupta S.Muddu J.Huang L.Capodieci P.Groeneveld P.Tucker H.Wang G.Wolfe S.Han A.S.Vydyanathan A.Kasibhatla R.S.Ramanujam B.Li L.Peh H.Yao C.C.N.Sze A.A.Kennings R.Sharma B.A.McCoy Y.Du J.Li J.Lee T.S.Rosing R.D.Strong Y.Cheon P.Ho C.Chiang S.Sinha X.Xu Y.Zheng S.Fenstermaker D.George B.Thielges L.He D.Noice N.Shirali S.H.Yen S.Borkar J.M.Cohn A.Domic L.Scheffer J.Schoellkopf R.Collett L.Lev N.Nettleton P.K.Rodman L.v.d.Hoven H.Choi G.Qu J.L.Wong J.C.Rey N.S.Nagaraj F.Klass R.Aitken C.Hou V.Singh D.A.Antonelli D.Z.Chen T.J.Dysart X.S.Hu P.M.Kogge R.C.Murphy M.T.Niemier H.Chen C.Cheng N.Chou J.F.MacDonald P.Suaris B.Yao Z.Zhu Y.Cao F.Koushanfar H.Lu M.Oliver D.Stroobandt J.Lach W.H.Mangione-Smith
Talks about:
design (16) placement (9) partit (9) methodolog (7) power (7) optim (7) reduct (6) driven (6) time (6) base (6)

Person: Andrew B. Kahng

DBLP DBLP: Kahng:Andrew_B=

Facilitated 2 volumes:

DAC 2005Ed
DAC 2004Ed

Contributed to:

DAC 20152015
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DATE 20122012
DAC 20102010
HPCA 20102010
DATE 20092009
DAC 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DATE 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DATE v2 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DAC 20002000
DAC 19991999
DAC 19981998
DATE 19981998
DAC 19971997
DAC 19961996
DAC 19951995
DAC 19941994
DAC 19931993
DAC 19921992
DAC 19911991
DAC 19891989

Wrote 70 papers:

DAC-2015-ChanNKDS #2d #3d #estimation #implementation
3DIC benefit estimation and implementation guidance from 2DIC implementation (WTJC, SN, ABK, YD, KS), p. 6.
DAC-2015-HanKL #design #evaluation #using
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router (KH, ABK, HL), p. 6.
DAC-2015-HanLKNL #framework #multi #optimisation #reduction
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction (KH, JL, ABK, SN, JL), p. 6.
DAC-2015-Kahng #game studies
New game, new goal posts: a recent history of timing closure (ABK), p. 6.
DATE-2014-HanKNV #learning
A deep learning methodology to proliferate golden signoff timing (SSH, ABK, SN, ASV), pp. 1–6.
DATE-2014-JerkeK #case study #design
Mission profile aware IC design — A case study (GJ, ABK), pp. 1–6.
DATE-2014-KahngK #logic #memory management #scheduling
Co-optimization of memory BIST grouping, test scheduling, and logic placement (ABK, IK), pp. 1–6.
DAC-2013-Kahng #design #process #roadmap
The ITRS design technology and system drivers roadmap: process and status (ABK), p. 6.
DAC-2013-KahngKL #reduction
Smart non-default routing for clock power reduction (ABK, SK, HL), p. 7.
DATE-2013-ChanCK #adaptation #scalability
Impact of adaptive voltage scaling on aging-aware signoff (TBC, WTJC, ABK), pp. 1683–1688.
DATE-2013-KahngKP #power management #reduction
Active-mode leakage reduction with data-retained power gating (ABK, SK, BP), pp. 1209–1214.
DATE-2013-KahngLN #design #estimation #metamodelling #problem
Enhanced metamodeling techniques for high-dimensional IC design estimation problems (ABK, BL, SN), pp. 1861–1866.
DAC-2012-KahngK #approximate #configuration management #design
Accuracy-configurable adder for approximate arithmetic designs (ABK, SK), pp. 820–825.
DAC-2012-KahngLN #estimation #modelling
Explicit modeling of control and data for improved NoC router estimation (ABK, BL, SN), pp. 392–397.
DATE-2012-JeongKKRS #memory management #named #power management
MAPG: Memory access power gating (KJ, ABK, SK, TSR, RDS), pp. 1054–1059.
DAC-2010-GuptaKKS #benchmark #heuristic #metric #named
Eyecharts: constructive benchmarking of gate sizing heuristics (PG, ABK, AK, PS), pp. 597–602.
DAC-2010-KahngKKS #design #power management
Recovery-driven design: a power minimization methodology for error-tolerant processor modules (ABK, SK, RK, JS), pp. 825–830.
DAC-2010-KahngLSR #optimisation
Trace-driven optimization of networks-on-chip configurations (ABK, BL, KS, RSR), pp. 437–442.
HPCA-2010-KahngKKS #design #reliability #trade-off
Designing a processor from the ground up to allow voltage/reliability tradeoffs (ABK, SK, RK, JS), pp. 1–11.
DATE-2009-KahngLPS #design #performance
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration (ABK, BL, LSP, KS), pp. 423–428.
DAC-2008-GuptaK #bound
Bounded-lifetime integrated circuits (PG, ABK), pp. 347–348.
DAC-2008-JeongKPY #power management #reduction
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction (KJ, ABK, CHP, HY), pp. 516–521.
DAC-2008-ReyNKKAHCS #question
DFM in practice: hit or hype? (JCR, NSN, ABK, FK, RA, CH, LC, VS), pp. 898–899.
Line-End Shortening is Not Always a Failure (PG, ABK, YK, SS, DS), pp. 270–271.
DATE-2007-Kahng #challenge #design
Design challenges at 65nm and beyond (ABK), pp. 1466–1467.
Timing-driven Steiner trees are (practically) free (CJA, ABK, CCNS, QW), pp. 389–392.
DAC-2006-Kahng #challenge #design #multi
CAD challenges for leading-edge multimedia designs (ABK), p. 372.
DAC-2006-ShahGK #library #optimisation #reduction #standard
Standard cell library optimization for leakage reduction (SS, PG, ABK), pp. 983–986.
DATE-2006-KahngPSW #lens
Lens aberration aware timing-driven placement (ABK, CHP, PS, QW), pp. 890–895.
DAC-2005-CheonHKRW #power management
Power-aware placement (YC, PHH, ABK, SR, QW), pp. 795–800.
DAC-2005-GuptaKKS #analysis
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions (PG, ABK, YK, DS), pp. 365–368.
DATE-2005-ChiangKSXZ #detection
Bright-Field AAPSM Conflict Detection and Correction (CC, ABK, SS, XX, AZ), pp. 908–913.
DAC-2004-AntonelliCDHKKMN #automaton #clustering #modelling #problem
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions (DAA, DZC, TJD, XSH, ABK, PMK, RCM, MTN), pp. 363–368.
DAC-2004-CapodieciGKSY #design #towards
Toward a methodology for manufacturability-driven design rule exploration (LC, PG, ABK, DS, JY), pp. 311–316.
DAC-2004-GuptaKSS #effectiveness #runtime
Selective gate-length biasing for cost-effective runtime leakage control (PG, ABK, PS, DS), pp. 327–330.
DAC-2004-KahngR #concept #feedback
Placement feedback: a concept and method for better min-cut placements (ABK, SR), pp. 357–362.
DATE-v2-2004-KahngMR #named
Boosting: Min-Cut Placement with Improved Signal Delay (ABK, ILM, SR), pp. 1098–1103.
DAC-2003-ChenCCKMSYZ #algebra #clustering #layout #multi
An algebraic multigrid solver for analytical placement with layout based clustering (HC, CKC, NCC, ABK, JFM, PS, BY, ZZ), pp. 794–799.
DAC-2003-ChenGK #synthesis
Performance-impact limited area fill synthesis (YC, PG, ABK), pp. 22–27.
DAC-2003-GuptaKSY #off the shelf #tool support
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools (PG, ABK, DS, JY), pp. 16–21.
DAC-2003-KahngBCDGSS #design
Nanometer design: place your bets (ABK, SB, JMC, AD, PG, LS, JPS), pp. 546–547.
DATE-2003-ChenKRZZ #generative #reduction
Area Fill Generation With Inherent Data Volume Reduction (YC, ABK, GR, AZ, YZ), pp. 10868–10875.
DATE-2003-DasguptaKM #architecture #metric #novel #performance
A Novel Metric for Interconnect Architecture Performance (PD, ABK, SM), pp. 10448–10455.
DAC-2002-KahngCGLNRH #question #tool support
Tools or users: which is the bigger bottleneck? (ABK, RC, PG, LL, NN, PKR, LvdH), pp. 76–77.
DAC-2000-CaldwellCKKLMOSS #named
GTX: the MARCO GSRC technology extrapolation system (AEC, YC, ABK, FK, HL, ILM, MO, DS, DS), pp. 693–698.
DAC-2000-CaldwellKM #question #recursion
Can recursive bisection alone produce routable placements? (AEC, ABK, ILM), pp. 477–482.
DAC-2000-ChenKRZ #synthesis
Practical iterated fill synthesis for CMP uniformity (YC, ABK, GR, AZ), pp. 671–674.
DAC-2000-FenstermakerGKMT #architecture #design #metric #named #optimisation #process
METRICS: a system architecture for design process optimization (SF, DG, ABK, SM, BT), pp. 705–710.
DAC-2000-KahngMS #analysis #on the
On switch factor based analysis of coupled RC interconnects (ABK, SM, ES), pp. 79–84.
DAC-1999-CaldwellCKMPQW #design #effectiveness
Effective Iterative Techniques for Fingerprinting Design IP (AEC, HJC, ABK, SM, MP, GQ, JLW), pp. 843–848.
DAC-1999-CaldwellKKM #clustering #development #heuristic
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting (AEC, ABK, AAK, ILM), pp. 349–354.
DAC-1999-CaldwellKM #clustering
Hypergraph Partitioning with Fixed Vertices (AEC, ABK, ILM), pp. 355–359.
DAC-1999-KahngP #design
Subwavelength Lithography and Its Potential Impact on Design and EDA (ABK, YCP), pp. 799–804.
Watermarking Techniques for Intellectual Property Protection (ABK, JL, WHMS, SM, ILM, MP, PT, HW, GW), pp. 776–781.
DAC-1998-KahngMMPTWW #design #physics #robust
Robust IP Watermarking Methodologies for Physical Design (ABK, SM, ILM, MP, PT, HW, GW), pp. 782–787.
Interconnect Tuning Strategies for High-Performance Ics (ABK, SM, ES, RS), pp. 471–478.
DAC-1997-AlpertHK #clustering #multi
Multilevel Circuit Partitioning (CJA, JHH, ABK), pp. 530–533.
DAC-1997-CongHKNSY #2d #analysis
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology (JC, LH, ABK, DN, NS, SHCY), pp. 627–632.
DAC-1997-KahngT #bound
More Practical Bounded-Skew Clock Routing (ABK, CWAT), pp. 594–599.
DAC-1996-KahngM #analysis
Analysis of RC Interconnections Under Ramp Input (ABK, SM), pp. 533–538.
DAC-1995-HagenHK #heuristic #layout #quantifier
Quantified Suboptimality of VLSI Layout Heuristics (LWH, DJHH, ABK), pp. 216–221.
DAC-1995-HuangKT #bound #on the #problem
On the Bounded-Skew Clock and Steiner Routing Problems (DJHH, ABK, CWAT), pp. 508–513.
DAC-1994-AlpertK #clustering #multi #programming
Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming (CJA, ABK), pp. 652–657.
Rectilinear Steiner Trees with Minimum Elmore Delay (KDB, ABK, BAM, GR), pp. 381–386.
DAC-1994-KahngM #analysis #equation #using
Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model (ABK, SM), pp. 563–569.
DAC-1993-AlpertK #clustering #geometry #multi #performance
Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning (CJA, ABK), pp. 743–748.
High-Performance Routing Trees With Identified Critical Sinks (KDB, ABK, GR), pp. 182–187.
Net Partitions Yield Better Module Partitions (JC, LWH, ABK), pp. 47–52.
DAC-1991-KahngCR #geometry #recursion
High-Performance Clock Routing Based on Recursive Geometric Aatching (ABK, JC, GR), pp. 322–327.
DAC-1989-Kahng #performance
Fast Hypergraph Partition (ABK), pp. 762–766.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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