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Travelled to:
1 × USA
Collaborated with:
L.M.Guerra J.Fitzner C.Schläger B.Tabbara V.Zivojnovic
Talks about:
integr (1) verif (1) phase (1) model (1) accur (1) cycl (1) dsp (1)

Person: Dipankar Talukdar

DBLP DBLP: Talukdar:Dipankar

Contributed to:

DAC 19991999

Wrote 1 papers:

DAC-1999-GuerraFTSTZ #integration #modelling
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification (LMG, JF, DT, CS, BT, VZ), pp. 964–969.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.