Stem dsp$ (all stems)

71 papers:

DATE-2015-LeeSLKKL #programmable

DSP based programmable FHD HEVC decoder (SL, JS, WL, DHK, JK, SL), pp. 972–973.

DAC-2014-RoyMIT #multi #performance

Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves (DBR, DM, MI, JT), p. 6.

DAC-2013-AvinashBEPP #energy #fault #hardware

Improving energy gains of inexact DSP hardware through reciprocative error compensation (LA, AB, CCE, KVP, CP), p. 8.

SAC-2013-ShihL #kernel #manycore #named

nuKernel: MicroKernel for multi-core DSP SoCs with load sharing and priority interrupts (CSS, HYL), pp. 1525–1532.

DAC-2011-WhatmoughDBD #power management

Error-resilient low-power DSP via path-delay shaping (PNW, SD, DMB, ID), pp. 1008–1013.

DATE-2011-AbdallahLS #energy #fault #robust #statistics

Timing error statistics for energy-efficient robust DSP systems (RAA, YHL, NRS), pp. 285–288.

DATE-2010-Zhu #algorithm #multi #realtime

Retiming multi-rate DSP algorithms to meet real-time requirement (XYZ), pp. 1785–1790.

LCTES-2010-LiZ #embedded #mobile #performance

An efficient code update scheme for DSP applications in mobile embedded systems (WL, YZ), pp. 105–114.

DAC-2008-HsiehH #debugging #embedded #framework #interface

An embedded infrastructure of debug and trace interface for the DSP platform (MCH, CTH), pp. 866–871.

DAC-2008-MilderFHP #implementation #representation

Formal datapath representation and manipulation for implementing DSP transforms (PAM, FF, JCH, MP), pp. 385–390.

DATE-2008-MucciVMGDGKSCC #adaptation #array #configuration management #implementation #parallel #pipes and filters

Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array (CM, LV, IM, DG, AD, SG, JK, AS, LC, FC), pp. 1444–1449.

SAC-2008-LuizVS #framework #specification

Formal specification of DSP gateway for data transmission between processor cores of OMAP platform (SODL, GdMV, LDdS), pp. 1545–1549.

DATE-2007-CampiDPCRMLVV #adaptation #configuration management

A dynamically adaptive DSP for heterogeneous reconfigurable platforms (FC, AD, MP, LC, PLR, CM, AL, AV, LV), pp. 9–14.

DATE-2007-DabrowskiR #interactive

Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique (JD, RR), pp. 719–724.

LCTES-2007-ChenTCLYLL #compilation #distributed #embedded

Enabling compiler flow for embedded VLIW DSP processors with distributed register files (CKC, LHT, SCC, YJL, YPY, CHL, JKL), pp. 146–148.

DATE-2006-GuillotBRCGA #diagrams #performance #using

Efficient factorization of DSP transforms using taylor expansion diagrams (JG, EB, QR, MJC, DGP, SA), pp. 754–755.

DAC-2005-Magee #development #matlab #realtime #testing #verification

Matlab extensions for the development, testing and verification of real-time DSP software (DPM), pp. 603–606.

CGO-2005-ChenK #code generation #optimisation

Optimizing Address Code Generation for Array-Intensive DSP Applications (GC, MTK), pp. 141–152.

DAC-2004-DebJO #design #modelling #paradigm #transaction

System design for DSP applications in transaction level modeling paradigm (AKD, AJ, JÖ), pp. 466–471.

DATE-v1-2004-DebJO #design #using

System Design for DSP Applications Using the MASIC Methodology (AKD, AJ, JÖ), pp. 630–635.

DATE-v2-2004-RizkPW #design #embedded #source code

Designing Self Test Programs for Embedded DSP Cores (HR, CAP, FGW), pp. 816–823.

DATE-v2-2004-VerbauwhedeSPK #architecture #design #embedded #energy #multi #performance

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing (IV, PS, CP, BK), pp. 988–995.

SAC-2004-PanisHLLN #design #embedded #named

DSPxPlore: design space exploration methodology for an embedded DSP core (CP, UH, GL, WL, JN), pp. 876–883.

DAC-2003-FangRPC #modelling #performance #static analysis #towards

Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling (CFF, RAR, MP, TC), pp. 496–501.

DAC-2003-ShiG #hybrid #performance #power management

Hybrid hierarchical timing closure methodology for a high performance and low power DSP (KS, GG), pp. 850–855.

DATE-2003-DebOJ #analysis #embedded #simulation #using

Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology (AKD, JÖ, AJ), pp. 11100–11101.

DATE-2003-RinnerSW #agile #architecture #embedded #flexibility #multi #prototype

Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures (BR, MS, RW), pp. 10204–10211.

CC-2003-Leupers #algorithm #evaluation #optimisation

Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms (RL), pp. 290–302.

DAC-2002-ChoiK #code generation #scheduling

Address assignment combined with scheduling in DSP code generation (YC, TK), pp. 225–230.

DATE-2002-LiverisZSG #performance #program transformation

A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications (NDL, NDZ, DS, CEG), pp. 977–983.

DATE-2002-SassatelliTBGDCG #architecture #configuration management #scalability

Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications (GS, LT, PB, TG, CD, GC, JG), pp. 553–558.

DATE-2002-WilliamsHA #communication #parallel

Communication Mechanisms for Parallel DSP Systems on a Chip (JW, NH, BDA), pp. 420–422.

DAC-2001-Bondalapati #architecture #configuration management #using

Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching (KB), pp. 273–276.

DAC-2001-Gebotys #embedded #memory management

Utilizing Memory Bandwidth in DSP Embedded Processors (CHG), pp. 347–352.

DAC-2001-PeymandoustM #algebra #algorithm #synthesis #using

Using Symbolic Algebra in Algorithmic Level DSP Synthesis (AP, GDM), pp. 277–282.

PLDI-2001-XiongJJP #algorithm #compilation #named

SPL: A Language and Compiler for DSP Algorithms (JX, JRJ, RWJ, DAP), pp. 298–308.

FME-2001-ArditiBCS #generative #testing #validation

Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System (LA, HB, AC, VS), pp. 449–464.

CC-2001-FrankeO #array #compilation #pointer

Compiler Transformation of Pointers to Explicit Array Accesses in DSP Applications (BF, MFPO), pp. 69–85.

LCTES-OM-2001-GranstonSZ #architecture #pipes and filters

Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture (EDG, ES, JZ), pp. 138–144.

DAC-2000-CurrieHR #automation #verification

Automatic formal verification of DSP software (DWC, AJH, SPR), pp. 130–135.

DAC-2000-WangKS #clustering #latency #memory management #scheduling

Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications (ZW, MK, EHMS), pp. 540–545.

DAC-1999-ChoiYLPK #design #embedded

Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software (HC, JHY, JYL, ICP, CMK), pp. 939–944.

DAC-1999-GuerraFTSTZ #integration #modelling

Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification (LMG, JF, DT, CS, BT, VZ), pp. 964–969.

DAC-1999-KalavadeOAS #multi

Software Environment for a Multiprocessor DSP (AK, JO, BDA, KJS), pp. 827–830.

DAC-1999-KaulVGO #approach #automation #clustering #configuration management #synthesis

An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications (MK, RV, SG, IO), pp. 616–622.

DAC-1999-PeesHZM #architecture #modelling #named #programmable

LISA — Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures (SP, AH, VZ, HM), pp. 933–938.

DAC-1999-PegatoquetGAB #agile #development

Rapid Development of Optimized DSP Code from a High Level Description Through Software Estimations (AP, EG, MA, LB), pp. 823–826.

DATE-1999-CmarRSVB #design #fixpoint #refinement

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement (RC, LR, PS, SV, IB), p. 271–?.

DATE-1999-EijkJMT #algorithm #identification #symmetry

Identification and Exploitation of Symmetries in DSP Algorithms (CAJvE, ETAFJ, BM, AHT), pp. 602–608.

LCTES-1999-EcksteinK #low cost

Minimizing Cost of Local Variables Access for DSP-Processors (EE, AK), pp. 20–27.

LCTES-1999-StotzerL #architecture #scheduling

Modulo Scheduling for the TMS320C6x VLIW DSP Architecture (ES, ELL), pp. 28–34.

DAC-1998-SuttonSR #multi #using

A Multiprocessor DSP System Using PADDI-2 (RAS, VPS, JMR), pp. 62–65.

DAC-1998-WittenburgHKOBLKP #image #parallel #performance #programmable

Realization of a Programmable Parallel DSP for High Performance Image Processing Applications (JPW, WH, JK, MO, MB, HL, HK, PP), pp. 56–61.

DAC-1998-YangKNCSRKLLKYKLHKKPPLHPK #development #named

MetaCore: An Application Specific DSP Development System (JHY, BWK, SJN, JHC, SWS, CHR, YSK, DHL, JYL, JSK, HDY, JYK, KML, CSH, IHK, JSK, KIP, KHP, YHL, SHH, ICP, CMK), pp. 800–803.

DATE-1998-BasuLM #source code

Register-Constrained Address Computation in DSP Programs (AB, RL, PM), pp. 929–930.

DATE-1998-ZhaoP #self #source code #testing

Testing DSP Cores Based on Self-Test Programs (WZ, CAP), pp. 166–172.

LCTES-1998-Campbell #architecture #embedded

Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications (MC), p. 261.

DAC-1997-AdeLP #data flow #graph #memory management

Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets (MA, RL, JAP), pp. 64–69.

DAC-1997-HeinPK #prototype

RASSP Virtual Prototyping of DSP Systems (CH, JP, WK), pp. 492–497.

DAC-1997-SudarsanamLD #analysis #architecture #evaluation

Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures (AS, SYL, SD), pp. 287–292.

EDTC-1997-LeijtenMTJ #architecture #data-driven #multi #named

PROPHID: a data-driven multi-processor architecture for high-performance DSP (JAJL, JLvM, AHT, JAGJ), p. 611.

DAC-1996-GoodbyO #pseudo

Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths (LG, AO), pp. 813–818.

DAC-1995-LiaoDKTW #embedded #optimisation

Code Optimization Techniques for Embedded DSP Microprocessors (SYL, SD, KK, SWKT, ARW), pp. 599–604.

DAC-1995-TimmerSMJ #code generation #modelling #scheduling

Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores (AHT, MTJS, JLvM, JAGJ), pp. 593–598.

EDAC-1994-HuangR #behaviour #performance #throughput #using

Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations (SHH, JMR), pp. 25–30.

EDAC-1994-LiemMP #code generation

Instruction-Set Matching and Selection for DSP and ASIP Code Generation (CL, TCM, PGP), pp. 31–37.

EDAC-1994-SchoofsGM #architecture #design #multi #optimisation

Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures (KS, GG, HDM), pp. 502–506.

DAC-1993-SharmaJ #named #scheduling

InSyn: Integrated Scheduling for DSP Applications (AS, RJ), pp. 349–354.

DAC-1991-NoteGCM #architecture #named #synthesis #throughput

Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications (SN, WG, FC, HDM), pp. 597–602.

DAC-1990-CaiNSM #assembly #layout #performance

A Data Path Layout Assembler for High Performance DSP Circuits (HC, SN, PS, HDM), pp. 306–311.

DAC-1989-GoossensVM #optimisation #scheduling

Loop Optimization in Register-Transfer Scheduling for DSP-Systems (GG, JV, HDM), pp. 826–831.